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Variation study of the planar ground-plane bulk MOSFET, SOI FinFET, and trigate bulk MOSFET designs
... Recently, it has been established that the extrinsic gate capacitance is the main parameter responsible for the limited cut-off frequencies experimentally observed for triple-gate FinFETs [16]. Two RF figures of merit, namely, the current-gain cutoff frequency (fT) and the maximum oscillation frequency (fmax), are evaluated using the following equation [17]: ...
... Where Cgg = Cgge + Cggi, gmi and gdi are the intrinsic transconductance and output conductance, respectively, and Rse is the parasitic source resistance. Two RF figures of merit, namely, the current-gain cutoff frequency (f T ) and the maximum oscillation frequency (f max ), are evaluated using the following equation [17]: ...
... It is important to forecast improvement in f T and f max as traditional scaling of a FinFET is only achievable by choosing the optimal value of H fin and W fin . This phenomenon has been confirmed in [17,23]. However, manufacturing challenges and associated mechanical stresses are major concerns with taller fin devices. ...
Among multi-gate field effect transistor (FET) structures, FinFET has better short channel control and ease of manufacturability when compared to other conventional bulk devices. The radio frequency (RF) performance of FinFET is affected by gate-controlled parameters such as transconductance, output conductance, and total gate capacitance. In recent years, high-k spacer dielectric materials for manufacturing nanoscale devices are being widely explored because of their better electrostatic control and being less affected by short channel effects (SCEs). In this paper, we aim to explore the potential benefits of using different Dual-k spacers on source and drain, respectively: (AsymD-kk) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low-power operation at 14 nm gate length. It has been observed from the results that the AsymD-kk FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source and drain side, improving the transconductance (gm) and output conductance (gds) at the cost of an increase in Miller capacitance. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on a Dual-kk FinFET structure. It can be observed that the new asymmetric drain extension structures significantly improve the cutoff frequency (fT) and maximum oscillation frequency (fmax) given the significant reduction of inner fringe capacitance towards drain side due to the shifting of the drain extension’s doping concentration away from the gate edge. Therefore, the asymmetric drain extension Dual-kk trigate FinFET (AsymD-kkDE) is a new structure that combines different Dual-k spacers on the source and drain and asymmetric drain extension on a single silicon on insulator (SOI) platform to enhance the almost all analog/RF FOM. The proposed structure is verified by technology computer-aided design (TCAD) simulations with varying device physical parameters such as fin height, fin width, aspect ratio, spacer width, spacer material, etc. From comprehensive 3D device simulation, we have demonstrated that the proposed device is superior in performance to a conventional trigate FinFET and can be used to design low-power digital circuits.
... Due to the smaller size with the three-dimensional structure of FinFETs, it's very difficult to develop a compact model for its [17]. By increasing the height of the fins can moderate the Short channel Effect in FinFETs lead to significant DIBL and better subthreshold slope [18].With a combination of increasing the Fins Effect and along with channel length leads to better result in terms of reduction in the contact area that increase the contact resistance and leads to better device performance [20]. FinFETs can be designed in two types SOI and Bulk. ...
... In the proposed designed we used the SOI structure for designing the 14-nm FinFET and used the rectangular fins shape. All the Simulation carried on the Visual TCAD by Cogenda [20]. Table 1 represents the proposed design dimensions. ...
In today's microelectronics, FinFET played a leading role to reduce the device dimension at the nanometer scale. The ultra-thin fin on the FinFET device leads to suppression in short channel effect and leakage current that can make a different edge on the performance of the VLSI circuit. In this article, a comprehensive simulation and compact model of 14nm N-type FinFET presented. N-Type FinFET is simulated and analyzed the performance on the different parameters like power dissipation and on-off current ratio (I on /I off) concerning the different oxide material. Further, we analyzed the proposed device performance through the process variation by varying the parameter temperature from 200K to 350K and oxide thickness from 1 nm to 3nm.The high current ratio value of 10 10 observed in high-k oxide material in comparison to low-K oxide material that enhance the switching speed of the device in the proposed design along with analyzed the bandgap also. The power dissipation of the proposed design improved upto 38% in comparison to a low-k oxide material.
... 18 The multi-fin architecture with pitch distance on single substrate was first proposed by Mathew et al., Zhang et al. known as inverted 'T' (IT) FET. [17][18][19] The device experiences a better utilization of unwanted area among multi-fins. Further, Fahad et al. explore the optimization of ultrathin body (UTB) layer and renamed as Wavy FinFET. ...
... 21 The hybrid FinFET amalgamates two different technologies on the same SOI platform, i.e., 2-D UTB MOSFET 21,22 and 3-D FinFET. 19 The precise identification of UTB FinFET with gate oxide technology, spacers engineering, an asymmetric dual-k spacer (ADS) was discussed and came up with several advantages like high integration density, maximum area efficiency, and also a high performance with back biasing capability. 18,23,24 These topologies are constructed using inversion mode (IM) of conduction which are well-known devices for improving SCEs. ...
The work explores the performance estimation of Inverted 'T' (IT) architecture with JL topology i.e (ITJL-FinFET, the device utilizes unwanted area among multi-finswith bulk conductionmechanism) on SOI platform. For the first time, the crucial performancemetrics of ITJL FinFET are debated extensively by varying the geometry dimensions at 22-nm node. The gate length (LG), virtual underlap source (LUS) and drain (LUD), and workfunction (φM) are optimized at 20-nm, 4-nm, 4.6 eV respectively. The SS, DIBL and switching current ratio (ION/IOFF) are achieved 69 mV/decade, 27 mV/V and 105. The decrement in transconductance (gm) with increasing in length of LG, LUS, LUD and simultaniously, transconductance generation factor (TGF) tends to improve. Moreover, we have been examine the grid sensitivity of the device and considered the grid points where the independency of I-V characteristics achieved during simulation. The result ensures a systematic prefabrication analysis of ITJL FinFET found to be appropriate, which will overcome the challenges at the nanoscale regime.
... [7][8][9][10] However, the FinFET structure faces the problem of intrinsic fluctuations, which leads to performance mismatch between identically designed devices. 11,12 This statistical variability increases with the downscaling of device dimensions. The major sources of variability in underlap FinFETs are the line-edge roughness (LER), [13][14][15] random dopant fluctuation (RDF), 16,17 oxide thickness variation (OTV), 12,17,18 and metal gate work function variation (WFV). ...
... The fin thickness (T si ) and oxide layer thickness (t ox ) play an important role in controlling the carrier mobility as well as threshold voltage. As per Ref. 11, T si usually should be smaller than 0.7 × L G , where L G is the physical gate length, and the corresponding t ox should be smaller than 0.3 × T si to have sufficient suppression of the SCEs. In this work, T si and t ox are considered 8 and 1 nm, respectively. ...
In aggressively scaled devices, FinFET technology has become more prone to line-edge roughness (LER) induced threshold voltage variability. To explain this challenge, all possible LER-induced fin shape variabilities in spacer-defined patterning (i.e., correlated LER) and resist-defined patterning (i.e., uncorrelated LER) technology have been investigated for 14-nm underlap FinFET using 3-D numerical simulations. All LERinduced VTH variabilities are analyzed in the presence of other intrinsic variability sources, such as random dopant fluctuation (RDF), work function variation (WFV), and oxide thickness variation (OTV). This study reveals that the percentage threshold voltage (VTH) fluctuations of combined effects (RDF, WFV, and OTV) in spacerdefined and resist-defined FinFETs with respect to rectangular FinFET are 2.88% and 8.76%, respectively. © 2017 Society of Photo-Optical Instrumentation Engineers (SPIE).
... The VEA is increasing with a decrease in HFin/Lg ratio in the subthreshold region (VD= 50 mV), however, there is no such variations in the super-threshold region (VD= 0.35 V). fringing field density with HFin/Lg ratio. Sun et al. [26] have reported that HFin = 0.6xLg or 0.8xLg are good for better SCE immunity. So, we have varied HFin from 0.25xLg to 1.3xLg. ...
... So, in this work we have systematically explored the impact of WFin/Lg ratio on the analog/RF performance of the FinFET. [26] have reported that WFin=0.6xLg for FinFET and WFin=1.0xLg ...
Now a days FinFETs integrated into complex circuit applications can fulfill the demand of smartphones and tablets for better performance and make chips that can compute faster. This work studies the impact of HFin and WFin variations on various performance matrices including static as well dynamic figures of merit (FOMs). With the help of Aspect Ratio (WFin/HFin). The device is branched into three parts i.e., FinFET, Trigate, and Planar MOSFET. This unique report is a presentation of a detailed analysis about the impact of fin height (HFin) and width (WFin) on various performances including the DC as well as AC figures of merit (FOMs). The static or low frequency performances like threshold voltage (Vth), on current (Ion), off current (Ioff), power dissipation, transconductance (gm), output conductance (gd), transconductance generation factor (TGF=gm/ID), early voltage (VEA), gain (AV) and dynamic or high frequency performances as gate capacitance (Cgg), cutoff frequency (fT), output resistance (R0), intrinsic delay are systematically presented with the variation of device geometry parameters. The results presented in this report can be of great help to device engineers in designing 3-D devices as per their requirement
... When conducting single event effect studies of FinFET devices, the traditional research approach is based on TCAD simulation software. However, the traditional TCAD simulation process is tedious, and time-consuming, and requires researchers to fully understand FinFET devices and simulation software [18]- [20]. More importantly, the problem of nonconvergence during the simulation process has not been effectively solved yet. ...
The Single Event Effect (SEE) of FinFET devices has become one of the challenging issues affecting the reliability of modern electronic systems in space and terrestrial applications. However, the conventional FinFET device simulation steps are tedious and take a long time. This paper proposes a method based on a convolutional neural network (CNN) to predict the single event effect (SEE) of FinFET devices. By entering different particle incidence conditions, the SEE profiles, as well as the characteristic parameters, can be obtained quickly and accurately. The neural network model used in the experiments has a high prediction accuracy. The error of our trained network model in predicting the drain transient current pulse profile is only 0.012, The Mean Square Error(MSE) for predicting the peak drain transient current and total collected charge are only 0.00207 and 0.00084.The total time for training, validation and prediction of the neural network model in this study is 352 seconds, and the prediction time is much shorter, which is much lower than the simulation time of TCAD software. The minimum simulation time of the TCAD simulation software is 1901 seconds, and the simulation requires further modification of the resultant plots of the single event effect transient current curves.
... com/ artic le/ Gds2M esh). The subthreshold slope of FinFETs can be enhanced by reducing the short channel effect by increasing the height of the fins, which minimizes oxide layer degradation and boosts capacitive coupling between channel and gates DIBL [15][16][17]. ...
This work presents a new SOI 14 nm heterojunction FinFET with Si1-xGex fin for low-power digital logic circuits. The channel region of the proposed device consists of Si1-x Gex compound semiconductor material. The impact of the Ge-mole percentage (x) on several electrical characteristics has been calculated. In this paper, a single gate material single dielectric material (SGMSD) is used for designing the proposed heterojunction FinFET and its static characteristics are compared with conventional FinFET. For making the heterojunction between the channel region and source/drain region, SiGe is used as a channel (fin) material and silicon is used in drain/source regions. The proposed design shows the higher current ratio (4.51 × 1012) and minimum value of Ioff Current (1.38 × 10–18) with a minimum value of the subthreshold swing 58.67 mV/dec and minimum value DIBL 52.37 mV/V which is better than the conventional FinFET. In the proposed transistor design, the impact of fin material on the performance parameters of the device is analyzed. The result shows a significant improvement in short channel parameters, device ON/OFF current ratio, noise margin and delay. Also, a heterojunction p-channel FinFET is designed along with corresponding n-channel FinFET to evaluate the transistors for low power CMOS-based logic applications.
... This degradation is due to the short channel effects such as subthreshold current, drain-induced barrier lowering, channel width modulation, velocity saturation etc. [25,26]. Several semiconductor device structures such as silicon-on-insulator, double gate, trigate transistor, FinFET, multi-gate and GAA have already designed but gate-allaround (GAA) device structures have shown the advantage of strong gate control over channel by gate in contrast to multi-gate devices [27][28][29][30][31][32][33][34]. It has the highest conductivity and electrical properties [35][36][37][38]. ...
In today’s world, semiconductor nanowire GAA-MOSFET devices have stimulated a lot of scientific research interest in the field of semiconductor. It has been observed as one of the strong and gifted structure for future generation nano-scaled devices and integrated circuits (ICs). Basically, the term nanotechnology is the key powerhouse of semiconductor device engineering and technology to produce and operate the materials at nano-meter scale (10−9 m or 1 nm) either by top-down approach where the bulk materials are converted to a group of nano particles (atoms) or by bottom-up approach where the single groups of nano particles (atoms) are converted to the bulk materials. Nanowire GAA MOSFET is considered as work horse in semiconductor industry due to great electrostatic controllability over the channel and tight coupling. This review article investigates the different structural designs of nanowire devices using nanotechnology approaches for future device applications.
... A number of important approaches have been introduced for tackling the issue of short channel effects (SCE), including (1) multi-gate structures, (2) junctionless (JL) devices, (3) gate dielectric engineering, and (4) gate electrode work function engineering [1][2][3][4][5]. Several multi-gate structures, such as fin field-effect transistors (FinFETs), tri-gate FETs, gate-all-around FETs, and nanowire FETs, have already been explored in the literature [6][7][8][9][10]. In the advanced form of the multi-gate structures, the silicon nanotube field effect transistor (SiNT-FET) was introduced in 2012 [11,12]. ...
The silicon nanotube field effect transistor (FET) is a tubular structure and has an inner gate and outer gate to control the channel. In this paper, the performance of a junctionless silicon nanotube FET is optimized using inner and outer gate engi-neering through 3D numerical TCAD simulations. The performance of the optimized devices is enhanced in terms of ON current (ION), OFF current (IOFF), and IONIOFF ratio. Appropriate work function and gate dielectric choices are suggested for the inner and outer gates to obtain optimized devices. The lowest IOFF and highest IONIOFF ratio are obtained for devices with high inner and outer gate permittivity along with low inner and outer gate work function. Also, the highest ION is obtained for the device with the highest inner and outer gate dielectric permittivity with low outer and inner gate work function. The device optimized for ION (98.6% increase compared to reference device) with the corresponding IOFF better than the refer-ence device can be used for high-power applications.
... Two or three gates are wrapped around the channel to give high current driving capability and excellent immunity to short channel effects. For trigate FinFETs selective etching step is added to make the third gate on top of the channel [11]. This additional step leads to process complexity, but at the same time it advantages as reduces fringe capacitances. ...
Workfunction modulated dual material gate FinFET (WMDMG-FinFET) is proposed to improve the DC performance of the device. A dual metal gate FinFET with linear modulation in workfunction along the source side of gate electrode keeping drain side gate electrode workfunction to be constant is introduced. Its subthreshold performance (i.e., switching ratio and subthreshold swing) is enhanced by introducing spacers in the side-walls of gate, with underlap concept. SILVACO TCAD tool is used to carry out the simulation work. The simulation results are compared for different spacers and it is observed that TiO2 spacer with high-k dielectric gives the best switching ratio and lowest subthreshold swing. The WMDMG-FinFET with spacers in the underlapped region shows better subthreshold characteristics as compared to conventional DMG-FinFET.
... New architectures with enhanced gate-to-channel coupling i.e., multi-gate structures, were adapted to overcome this issue [4]. In particular, the advantages of multigate structures, improved subthreshold swing, reduced short-channel effects and, therefore, enhanced scalability [5][6][7]. In bioanalytics, the extensive integration of CMOS chips with exposed arrays of floating-gate pH-sensors are promising in applications such as DNA sequencing [8], and assure towards innovation in DNA quantification, depends on quantitative PCR [9,10]. ...
In this paper, a triple gate (TG) cavity based, polysilicon junctionless (JL) ion-sensitive field-effect transistor (ISFET) architecture has been proposed for the first time. The performance of the proposed device has been compared with conventionally doped ISFET. The effect of pH is investigated for different adhesion layers, device layer thickness (tsi), electrolyte thickness (te) and, channel lengths (L). Threshold voltage(\(\frac {\triangle {V_{th}}}{\triangle {pH}}\)) has been used as sensing metric for analysis and comparison. Besides, ION/IOFF ratio has also been measured for different pH. The average maximum threshold voltage sensitivity of the proposed device has been measured and found to be 72.5%, 49.5%, and 53.7% better than TG-conventional ISFET for different adhesion layers, device layer thickness, and channel lengths respectively. Furthermore, the effect of channel lenghth on threshold voltage sensitivity has also been studied. It is observed that the sensitivity increases with increase in channel length. The implementation and all the simulations have been performed by using the ATLAS device simulator.
... In this work we applied the step voltage of 1V across the Vgs and constant voltage of 1 V across the Vds. For calculating the driving force of electron and holes, quantum potential included in density gradient model of FinFETs [17,18]. Quantum corrections of the hole and electrons included in simulation as per below equations 1 [20]. ...
The introduction of Field Effect Transistor (FinFET) Technology played a leading contender in today microelectronics. FinFET structure allows to scale the device at sub-nanometer. Short channel effects can be suppressed by formation of ultra-thin fin in FinFET device. In this paper we compared the performance of the 20nm FinFET device by using different dielectric materials. We have considered only n-channel FinFET device. Simulation carried on the electron mobility, potential distribution, energy band of hole and electron, on-off current ratio (Ion/Ioff) and power dissipation of device with respect to the applied gate voltage. Mobility enhancement and higher current ratio (Ion/Ioff) is observed in proposed FinFET device having high k-dielectric material at lower voltage. This designed can be useful for low power applications due to low power dissipation. In high k-dielectric material, 1.41% improvement is observed in potential voltage with respect to low k- dielectric material when Vgs at low voltage and 0.98% improvement is observed when Vgs at high voltage. In high k- dielectric material 15% hike is observed in the energy conduction band as compared to low k-dielectric material when Vgs at low voltage and 14% hike is observed when Vgs at high voltage.
... FinFET with bottom spacer exploits shallower junction behaviour to reduce off sate leakage and simultaneously use of high doping in inactive fin contribute to the advantages of punchthrough stopper [10][11]. Reliability and process related issues still serious concern for FinFET structures [12][13][14] in terms of future scalability and performance parameters. Metal gate work function variability of pFinFET had been compared for Si and Ge interface to further optimized pFinFET performance [15]. ...
A steep subthershold slope novel usymmetrical FinFET is proposed for gate lenght 9nm with improved performance in terms of Ion/Ioff ratio in comparison to existing symmetrical structure. Proformance is furture optimised in terms of doping variations and under lap behaviour of FinFET. High-K dielectric material oxide and metal gate contact of high work function incorporated and performance compared. pFinFET and nFinFET both simulated togather to obtain ideal characteristics required to match in CMOS technology. 2D/3D Visual TCAD device simulator utilised in design of all FinFET structures.
... The technique discussed in the above sections holds true for the junction-based devices/the inversion mode Trigate FET. For this we took the device details from ref [25] which has a channel length of 20 nm and a gate workfunction of 4.37 eV and the corresponding cur- rents of the calibrated device are given in Table 5. All the studies ta- bulated in Table 3 Table 5. ...
... Here Pie-gate structure is basically represented by misalign ment(ΔX j =-ive) between the S/D junctions and the bottom of the gate electrode. Since the change of performance due to process variation can be very undesirable for some analog or dig ital CMOS circuits, the designer wants that the device performance should be independent of process variation [12]. The observed random distribution of identically drawn devices can be caused by impurity concentration densities. ...
FinFETs are multigate MOSFETs conventionally fabricated on SOI wafer. Alternatively, use of Si-bulk wafers for FinFET has gained significant interest for the low cost of wafers and more importantly for the compatib ility with bulk CMOS technology. This paper describes the design of Bulk Fin FET with improved performance using different bulk structures. In initial part of work, we have used the Pie-gate structure and heavy body doping structure i.e. Punchthrough stopper. Both the structures are comb ined in a novel Pie-gate bulk FinFET structure with punchthrough stopper. It has been observed that the novel structure shows better results compared to previous structures but it is difficult to fabricate. So, the Performance of bulk FinFET with bottom spacer is studied including the detailed discussion of process variation effect which shows that such bulk structure is supposed to have less fabrication co mplexity to achieve and optimize a desired doping profile. Finally, It is observed that the bulk Fin FET with bottom spacer can be optimized to obtain superior performance than all other FinFETs making it independent of doping related process variations.
... Multigate devices provided the answer to variability-induced problems in planar submicrometer transistors [40], [41] and were mainly introduced by manufacturers at 22-nm nodes and beyond. The FinFET has been established as the workhorse of the semiconductor industry for high performance down to 10-nm nodes [12]. ...
From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory.
... As the paper explores FinFET architecture, various dielectric materials are considered to optimize the analysis of spacer. The Table 1 replicates the parameters used to concrete the Wavy-JL FinFET estimated for device simulation [29][30][31]. ...
In this work, an attempt has been made to investigate the performance of a new device, Wavy Junctionless FinFET at 22 nm node using low to high permittivity spacer for underlap regions. An alternative VTH extraction method has been demonstrated, which signifies the importance of cannel length at the nanoscale regime. The device layer Silicon film possesses uniform doping profile, where the current is controlled by channel doping and the mobility of charge carriers which account the bulk conduction instead of surface conduction. Due to the scalability of device dimensions, underlap regions are preferred to differentiate the control and the location of dopant atoms along the conduction region and hence this enhances the device performances. The simulation results enlighten the effectiveness of high permittivity of spacer region through performance evaluation. The simulated results exhibit an SS of 64 mV/decade, DIBL of 26 mV/V and ION/IOFF ratio of 10⁷.
... The paper explores the optimal structure of Si based FinFET, various dielectric materials are considered to optimize the analysis of spacers. The Table 2 replicates the parameters used to concrete the inverted 'T' JL FinFET estimated for device simulation [26]- [28]. The physics behind the JLT is different from that of IMT, the depletion of heavily doped device layer appears at VGS=VDD=0V which makes the channel fully depleted with respect to VGS (VGS>VTH) and a high electric field (E field) is perpendicular to the device layer. ...
... 2(b) i.e. Thin FinFET have slighlty better electrostatic conrol of the channel because gate region is thin at middle of the Fin and for thinner channel the electric field will be more strong [16]. Hence the potential distribution is different which shows that it effects threshold voltage directly. ...
In todays advanced nanoscale regime, use of metal gate stacks have a different impact on the intrinsic parameter variability. The metal gates have a natural granular structure, where work function of each grain depends upon its orientation. Circuit and device designing are limited by the threshold voltage variability. In this study, threshold voltage variability induced by work function fluctuations of metal for different grain sizes (10, 7 and 5 nm) in a 14 nm gate length FinFETs device is analyzed using 3-D drift-diffusion device simulator. It is observed that with a reduction in grain size threshold voltage variability reduces linearly. It is seen that the different Fin shapes have approximately ~6% shift in the threshold voltage where as there is approximately ~16% improvement in the standard deviation of the threshold voltage. Further, on reducing the average grain size from 10 nm down to 5 nm results in an approximately ~45% reduction in variability induced by work function.
... It was further investigated that off state leakage current in SOI FinFET was 25 times less than that of bulk MOSFET. This may be due to better control of three gates over channel in case of SOI FinFET and its ultra thin body structure [13,14] which might have reduced the leakage current in SOI FinFET and further controlled the short channel effects whereas bulk MOSFET relies on channel doping to control short channel effects [15]. It was also observed that increase in drain voltage increased the off current in both devices, which happened because of DIBL. ...
The need to control the short channel effects in transistor that occurs in nanometer regime has caused the invention of multi gate transistors over planar bulk transistors in order to improve the performance. In this research paper the 3D model of SOI FinFET and Bulk MOSFET at 20nm node technology is designed and their transfer characteristics, drain characteristics and short channel effects are reported. The OFF state leakage current, DIBL, and threshold voltage of SOI FinFET and bulk MOSFET has been calculated. The simulation is performed using TCAD simulator. The simulation results has shown that the OFF state leakage current is less in FinFET as compared to bulk MOSFET and the Ion in SOI FinFET is higher than that of bulk MOSFET. The DIBL of bulk MOSFET is found to be 2.57 times more than that of SOI FINFET, so SOI FinFET has shown reduction in short channel effects as compared to bulk MOSFET at 20nm gate length. GIDL is also examined in both devices. The drain current of SOI FinFET at Vgs= 0.1V is observed higher than that of bulk MOSFET.
... Structures with improved gate-to-channel coupling, indicated as multi-gate devices, were conceived for traditional solid-state systems to overcome this issue [1]. In particular, the feature of these devices, enhanced subthreshold swing, reduced short-channel effects such as drain-induced barrier lowering (DIBL) and, consequently, resulted in an improved scalability [2][3][4]. As a matter of fact, the introduction of multi-gate device architectures has so far effectively sustained Moore's law and kept up the pace of technological advancement in the electronics industry. ...
The signal-to-noise ratio of planar ISFET pH sensors deteriorates when reducing the area occupied by the device, thus hampering the scalability of on-chip analytical systems which detect the DNA polymerase through pH measurements. Top-down nano-sized tri-gate transistors, such as silicon nanowires, are designed for high performance solid-state circuits thanks to their superior properties of voltage-to-current transduction, which can be advantageously exploited for pH sensing. A systematic study is carried out on rectangular-shaped nanowires developed in a complementary metal-oxide-semiconductor (CMOS)-compatible technology, showing that reducing the width of the devices below a few hundreds of nanometers leads to higher charge sensitivity. Moreover, devices composed of several wires in parallel further increase the exposed surface per unit footprint area, thus maximizing the signal-to-noise ratio. This technology allows a sub milli-pH unit resolution with a sensor footprint of about 1 µm², exceeding the performance of previously reported studies on silicon nanowires by two orders of magnitude.
This manuscript for the first time presents the digital and analog/RF performance analysis for novel Tree-shaped Junctionless Nanosheet (NS) FET. An additional inter-bridge (IB) channel is added to the vertically stacked JL-NSFET to form a Tree-shaped structure. The Tree-shaped JL-NSFET is compared with the conventional JL-NSFET for
${L}_{g}$
= 16 nm,
${T}_{\text {NS}}$
= 5 nm,
${W}_{\text {NS}}$
= 18 nm,
${W}_{\text {IB}}$
= 2 nm, and
${H}_{\text {IB}}$
= 6 nm. It is observed that ON-current (
${I}_{ \mathrm{\scriptscriptstyle ON}}$
) has been improved for Tree-shaped JL-NSFET by an amount of ~15.3% with a decent subthreshold swing of 61.5 mV/dec. The analog/RF performance of the Tree-shaped JL-NSFET has been improved satisfactorily as compared to the conventional JL-NSFET. Further to enhance the digital/analog RF performance the
${W}_{\text {IB}}$
is varied between 2–4 nm. The
${I}_{ \mathrm{\scriptscriptstyle ON}}$
is increased by an amount of ~23.56% with the increase in
${W}_{\text {IB}}$
due to the increase in effective width. However, the same resulted in the degradation of
${A}_{V}$
, GFP,
${f}_{T}$
, and
${f}_{\text {MAX}}$
by an amount of ~1.72%, ~3.39%, ~4.46%, and ~8.39%, respectively, at 1-nA normalized drain current. Hence lower
${W}_{\text {IB}}$
must be chosen for the improvement of analog/RF parameters. Furthermore, the effect of temperature (100–400 K) on Tree-shaped JL-NSFET is also investigated and the performance is best recorded at lower temperatures. At 1-nA normalized drain current,
${g}_{m}$
,
${A}_{V}$
,
${f}_{T}$
,
${f}_{\text {MAX}}$
, and GFP are noticeably improved by an amount of ~68.6%, ~5.84%, ~65.02%, ~34.14%, and ~56.02%, respectively. Moreover, the effect of IB height (
${H}_{\text {IB}}$
) is explored (6–14 nm) and it is inferred that
${H}_{\text {IB}}$
should be optimized to get better digital and analog/RF performances according to the application areas.
With the down scaling of device dimensions, FinFET structure faces the problem of the increasing process variability which results to the device performance mismatch. By technology computer-aided design (TCAD) numerical simulation, a high-k/metal gate silicon-on-insulator (SOI) FinFET at 14 nm technology node is presented, which is calibrated by the experiment data. The influences of the work function and the oxide thickness variation on single event transient (SET) characteristic are systematically studied and analyzed. The statistical analysis of the effects of three profile oxide thickness mismatch and variation on SET is also performed. The results show that as the equivalent oxide thickness varies from 0.41 nm to 0.61 nm, SET current peak increases from 377.92 μA to 392.08 μA and the collected charge increases from 1.265fC to 1.271fC due to the increased threshold voltage, respectively. Due to the combination electron concentration and recombination rate, when the work function varies from 4.36 eV to 4.6 eV, the transient current peak decreases from 387.23 μA to 363.61 μA and the collected charge reduces from 1.269fC to 1.258fC, respectively. Compared with the profile with shorter gate width, the effect of the oxide thickness variation with the longer gate width on SET is more significant. The standard deviation and normalized deviation of SET current peak and collected charge are 7.35 μA and 0.03fC, 1.89% and 2.57%, respectively.
This work presents a new junctionless device called Workfunction Modulated Dual Metal Gate Junctionless FinFET (WFMDMG-Junctionless FinFET) to minimize the short channel effects, and to achieve improved dc performance. The result is analyzed by dividing the workfunction of the gate metal electrode in two equal halves and further dividing the source end of the electrode in five equal parts with linear variation in workfunction, keeping the drain end at constant workfunction. The 3-D TCAD simulations are carried out by SILVACO TCAD tool. And the results are compared with the Single Metal Gate (SMG)-junctionless FinFET, and Dual Metal Gate (DMG)-junctionless FinFET. The new proposed junctionless device shows improved subthreshold characteristics, i.e., minimum subthreshold swing (SS) of 60.1 mV/decade, and high ION/IOFF current ratio of 1.48e13.
This work investigates the reliability assessment of high-k spacer and the effect of temperature on the device analog/RF performance for Inverted ‘T' (IT) Junctionless (JL) FinFET. A systematic analysis is performed for different high-k spacer materials, like, SiO2, Si3N4, and HfO2 to improve the analog/RF performances. This work also represents the effect of oxide stacking i.e., low-k on high-k materials as a spacer to ensure device reliability for analog/RF performance. Various performances as subthreshold swing (SS), current switching ratio (ION/IOFF ratio), drain induced barrier lowering (DIBL), transconductance (gm), early voltage (VEA), gain (AV), higher order derivatives of current (gm1, gm2, gm3), Capacitance (CGS, CGD, CGG), cut-off frequency (fT), 2nd and 3rd order voltage intercept point (VIP2, VIP3), 3rd order intermodulation input intercept point (IIP3) are analyzed for the device. The obtained results are achieved with uniform high doping concentration under bulk conduction mechanism which downsizes the short channel effects and thereby enhances the linearity FoMs for analog/RF circuit applications. At 300 K, the acquire SCEs for high-k spacers, for example, SS, ION/IOFF ratio, DIBL accomplish to be 64 mV/decade, 107, 26 mV/V respectively. In contrast with distinctive temperature variation from 200 K to 400 K, the SCEs at 300 K are same to that of the high-k spacers.
In this work, the influence of proton-irradiation in the voltage gain of two-stage operational transconductance amplifier (OTA) designed with silicon-on-insulator (SOI) fin field effect transistors (FinFETs) is studied. The OTA simulations were performed using Verilog-A approach based on experimental data extracted from the SOI FinFET electrical characterization, before and after proton-irradiation. The OTA is designed with SOI FinFETs of fin widths ( W fin ) of 20 nm, 120 nm, and 870 nm, all in the same predefined inversion region ( g m / I D = 8 V ⁻¹ ). All evaluated OTA circuits exposed to proton-irradiation presented a voltage gain increase (compared with pre-irradiation circuits), of 0.87 dB, 1.19 dB, and 6.16 dB for fin widths of 20 nm, 120 nm, and 870 nm, respectively. The results show that despite the typical radiation effect of degradation of the individual transistors (it being more severe for larger fin width SOI FinFET), these effects combined in OTA circuits result in an unexpected improvement in DC voltage gain, especially for wider fins. Focusing on the fin width impact on the OTA voltage gain, before and after proton-irradiation, it is much greater for narrow fin width SOI FinFET thanks to the better Early voltage.
In current CMOS technology, parameter variations are playing a vital role in limiting the benefits of downscaling, especially in the nanodomain. This work presents the investigation of random dopant fluctuation (RDF) in several possible line-edge roughness (LER)-induced fin shapes of spacer- (i.e., correlated LER) and resist- (i.e., uncorrelated LER) defined patterning techniques for a 14-nm FinFET structure. The three-dimensional (3-D) technology computer-aided design simulation on a large statistical ensemble has been carried out to analyze the impact of the RDF on various device parameters such as threshold voltage, drive current, off current, and drain-induced barrier lowering. It is observed that the impact of RDF on electrical parameters mainly depends on the fin shape and is dominant in all resist-defined FinFET structures. It is also found that the impact of RDF can diminish significantly using the spacer-defined patterning technique. Further, the impact of RDF in spacer- and resist-defined FinFET structures has been investigated for noise margins of 6-T static random access memories (SRAM). It is concluded that random dopant variations in SRAM performance offer better immunity in the case of spacer-defined FinFETs compared with resist-defined FinFETs. © 2018 Society of Photo-Optical Instrumentation Engineers (SPIE).
Nowadays FinFETs integrated into complex applications can fulfill the demand of new technology and make chips that can compute faster. Simultaneously various novel FinFETs structures come up constantly. In this brief, the impact of significant geometry parameters variations to device performance has been studied, such as fin height (Hfin), fin width (Wfin), fin spacing (Sfin), aspect ratio (Wfin/Hfin), and so on. In the result, we are able to determine the optimum device parameters for Multi-fin FinFETs. Meanwhile we analyze the parasitic gate capacitance and resistance of the multi-fin FinFETs using a conformal mapping method. To minimize the number of model fitting parameters, nondimensionalization technique is used. An effective lumped resistance model derived from distributed RC network is in use. Also, an analytical parasitic gate capacitance model is proposed, combined with parasitic capacitive couplings between source/drain fins and gates. Those analytical model can be applied for accurate circuit simulations of multi-fin FinFETs devices. The results presented in this paper can be of great help to device designers in designing 3-D devices as per their requirement.
In sub-20 nm CMOS technology nodes, the parameter variability has become a main hurdle during the scaling of devices. Recently, the use of metal gate stacks in nano-scale FinFET structure has a significant impact on the intrinsic parameter fluctuations due to the granular nature of metals. A 14 nm FinFET structure has been considered to study the impact of metal-gate work-function variability by using the 3-D device and mixed mode circuit simulation. The present work investigates the impact of work function variability (WFV) on electrical characteristics of various possible FinFET architectures followed by the regression model. Further, the investigation has been extended to study the stability performance of 6-T SRAM cell under the influence of WFV. It is observed that work function variation may result in considerable performance degradation in device as well as SRAM operation in nano domain.
In aggressively scaled devices, the FinFET technology has become more prone to line edge roughness (LER) induced threshold voltage variability. As a result, nano scale FinFET structures face the problem of intrinsic statistical fluctuations in the threshold voltage. This paper describes the all LER induced variability of threshold voltage for 14 nm underlap FinFET using 3-D numerical simulations. It is concluded that percentage threshold voltage (VTH) fluctuations referenced with respect to rectangular FinFET can go up to 8.76%. This work has also investigated the impact of other sources of variability such as random dopant fluctuation, work function variation and oxide thickness variation on threshold voltage.
In this paper, analog/RF performance of source side only dual-k spacer (Dual-kS) trigate junctionless transistor (JLT) is investigated with respect to the parametric variations. It is observed that the Dual-kS JLT improves analog/RF figure of merits (FOMs) and shows its lower dependence to the parametric variations compared with the conventional (low-k spacer) JLT. This study reveals that the design of Dual-kS JLT with lower aspect ratio (1 to 3) improves the analog FOMs with moderate frequency of operations at fin-width of 10 nm with gate length being 20 nm. Moreover, the frequency of operation can be increased further by increasing the aspect ratio (4 to 6) without sacrificing the analog FOMs such as transconductance (gm), output conductance (gds) and intrinsic voltage gain (AV0). It is also reported that gds of Dual-kS JLT is least sensitive to the variation in fin-width, doping concentration and oxide thickness, which proves the potential of Dual-kS device to act as a constant current source. Moreover, Dual-kS device is found to be robust against the variation in doping concentration and oxide thickness, which further improves the merit of Dual-kS JLT for low-voltage/low-power analog/RF applications.
Process variation is become future design challenge in ultra scaled identically designed Static Random Access Memory (SRAM), hence amendment in SRAM is needed. In this paper, we propose a novel low-power sensitivity-driven and inter-die process variation aware 10T SRAM cell via selective back-gate (SBG) biasing technique with independent-double-gate FinFET. As driver and load are the latching transistor in SRAM cell, where stability of cell depends on them, therefore SBG is applied on these transistors. SBG improves design yield and reduces parametric failures of proposed 10T cell by exploiting controlled conductivity of these transistors using back-gate biasing. Simulation results show that proposed SRAM cell improves write margin, static noise margin and read noise margins by 76%, 30% and 22%, respectively along with improved performance.
The endless miniaturization of Si based MOSFETs has the key for driving the electronic revolution. However, scaling of the channel length is the enormous challenge to preserve the performance in terms of speed, power and electrostatic integrity at each technology nodes. Subsequently all researchers have been analyzing new device materials and architectures to fix this challenge. After continuous development in the areas of devices and materials have lastly conveyed III-V MOSFETs with high channel mobility. This paper is a discussion about the impact of fin height (HFin) and fin width (WFin) of a GaAs-FinFET, which affect the reliability of the device in view of various performance measures. A detailed analysis about the impact of geometry parameters like (HFin) and (WFin) on the static or low frequency performances like threshold voltage (Vth), on-off ratio (Ion/Ioff), power dissipation, subthreshold slope (SS), transconductance (gm), early voltage (VEA), gain (AV) and dynamic or high frequency performances as gate capacitance (Cgg), cut-off frequency (fT), delay (CV/I), energy (CV2), energy delay product (EDP) are systematically presented.
From the commencement of CMOS scaling, the simple MOSFETs are not up to the performance due to the increased SCEs and leakage current. To slacken the SCEs and leakage currents, different types of structures i.e. Multi-Gate MOSFETs like DG, TG, FinFETs are introduced. Currently the Integrated Device Manufacturer (IDM), foundries and electronic design automation (EDA) companies grant more investments and emphasis on most promising Multi-Gate technology. In this, sensitivity of underlap length on DC and AC parameters like drain current, SS, transition frequency, delay, EDP etc. is studied for both the chosen devices i.e. DG MOSFET and FinFET. From our reported results, DG MOSFET is a good candidate for high current drivability whereas FinFET provides better immunity to leakage currents and hence improved delay, EDP over DG MOSFET. Furthermore, FinFET provides high value of transition frequency which indicates that it is faster than DG MOSFET.
A physically based variability model is developed to explain threshold voltage (V
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) and drain-induced barrier lowering (DIBL) variations, and their correlations for static RAMs (SRAMs) and analog devices fabricated in a 32-nm high-K metal-gate technology. Inputs to the model rely on forward (F) and reverse (R) measurement of transistor pair mismatch. The modeling results are validated on SRAMs and analog devices. Asymmetric and symmetric variation components of V
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and DIBL variability are extracted by the model. Asymmetric variation is a major component responsible for the higher σ V
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mismatch in saturation region compared with linear region, and higher DIBL variability.
On scaling the conventional MOSFET in sub-micrometer regime, the short channel effects (SCEs) deteriorates the device performance. Owing to a new device structure (FinFET) has been introduced. This paper presents the effect of variation in different parameters of FinFET such as structure, dimension, doping and oxide material used for various electrical characteristics (on-state current (Ion), Subthreshold Swing (SS), off-current (Ioff) and threshold voltage (Vt)). As we increase the no. of gates in FinFET device, much better control of channel is obtained than the conventional MOSFET and SCEs are reduced to a great extent while scaling the device beyond 32 nm regime. The comparison has been drawn on 3-D SILVACO ATLAS simulations for different FinFET structures, based on simulation results Cylindrical-Gate All Around (Cy-GAA) FinFET exhibits the higher Ion current, smaller Ioff current, and high Ion/Ioff ratio due to its symmetrical structure and removal of corner effects.
This paper presents a 2-D temperature-dependent analytical drain current model, which is valid for six different device architectures (by slightly modifying the used parameters), i.e., dual material gate dielectric pocket silicon-on-void, dual material gate silicon-on-void, dual material gate silicon-on-insulator, dielectric pocket silicon-on-void, silicon-on-void, and silicon-on-insulator MOSFETs. The results thus obtained, i.e., drain current, transconductance, $g_{m}$/$I_{rm ds}$ ratio, threshold voltage, subthreshold slope, and $I_{rm on}$ /$I_{rm off}$ ratio have been verified with the simulated results obtained using ATLAS 3-D device simulator for channel length down to 30 nm. The analytical model is also used to investigate the impact of temperature variation on the characteristics of N-MOS inverter based on different architectures. In addition, impact of process and parameters variation (i.e., variation in shallow extension depth $(X_{e})$, side pillar thickness $(T_{rm st})$, thickness of buried oxide layer $(t_{3})$ along with the variation in temperature) on the subthreshold performance of different devices has also been studied through exhaustive device simulation.
The velocity of an electron traveling from the source to drain of a field effect transistor can be much degraded by scattering effects. The scattering effects eventually become dominant as the devices are scaled down to the nanometer regime. In this paper, we propose a current-voltage (I-V) model for a two-dimensional Silicon Nanowire FinFET (SNWFinFET) which considers the scattering mechanism effects as well. Based on our simulated model, a notable scattering effect is observed and the I-V characteristics are in good agreement with experimental data. To evaluate the model, three parameters, temperature, channel length and drain voltage, were varied; the variation of each parameter has a significant effect on the I-V characteristics. These simulation results provide insights helpful for implementing SNWFinFETs as future devices, especially for high speed applications.
The impact of systematic variations on transistor performance is shown for the trigate Bulk MOSFET and Double Gate SOI FinFET. This paper compares the variations in threshold voltage, subthreshold swing and drain induced barrier lowering (DIBL) by varying physical dimensions (gate oxide thickness, channel width and channel length) of the devices mentioned above. It also compares the temperature profile of the devices along the channel length. The electrical characteristics and temperature profile of the devices were simulated with the help of Sentaurus TCAD. The results obtained from the simulation reveal that trigate bulk MOSFET is more scalable than double gate SOI FinFET and can be used for better yield and reliability.
In this paper, the impact of interface charges on the performance of a short-channel symmetric dielectric pocket double-gate (DP-DG) MOSFET has been investigated. An analytical drain current model for DP-DG MOSFET has been developed, which is also useful for investigating the impact of dual-material gate on DP-DG architecture. The proposed model is verified using ATLAS 3-D simulator. In addition, exhaustive simulation has been carried out to address the impact of interface charges on the reliability issues of various devices, i.e., DP-DG, double-gate, and dielectric pocket architectures in terms of gate leakage current, electron temperature, and impact of interface charges on the threshold voltage lowering. Analog and digital performances have also been investigated and compared with the other devices.
A tri-gate bulk MOSFET design utilizing a low-aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations indicate that this design offers the advantages of a multi-gate FET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).
We derive a new scale length for two-dimensional (2-D) effects in MOSFETs and discuss its significance. This derivation properly takes into account the difference in permittivity between the Si channel and the gate insulator, and thus permits an accurate understanding of the effects of using insufficiently scaled oxide or thicker higher permittivity gate insulators. The theory shows that the utility of higher dielectric constant insulators decreases for /spl epsiv///spl epsiv//sub 0/>-20, and that in no event should the insulator be thicker than the Si depletion depth. The approach is also applied to double-gated FET structures, resulting in a new more general scale length formula for them, too.
Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed.
The scale length for trigate and planar ground-plane bulk MOSFETs is derived, and its sensitivity to device design parameters is investigated. The results indicate that the trigate bulk MOSFET is a more scalable design as compared with the planar ground-plane bulk MOSFET and the double-gate SOI MOSFET.
Variations in highly scaled ( L <sub>G</sub> = 9 nm), undoped-channel FinFET performance, caused by statistical dopant fluctuations (SDFs) in the source/drain (S/D) gradient regions, are systematically investigated using 3-D atomistic device simulations. The impact of SDF on device design optimization is examined and simple design strategies are identified. Variation-tolerant design imposes stringent specifications for S/D lateral abruptness and gate-sidewall spacer thickness, and it poses a tradeoff between performance and variability for body thickness.
This paper describes a previously unreported phenomenon wherein
NMOS transistors of identical gate length exhibit a significant
sensitivity to layout. Drive current may be reduced up to 13%, depending
on diffusion overlap of gate. Mobility reduction, induced by stress from
the trench isolation edge, is the root cause of the performance
degradation. PMOS devices are not affected. Simulation results show that
stress varies strongly with distance from the trench edge, and with
overall diffusion size. Stress is also a major component of narrow-width
effects, and explains why Idsat scaling with W differs for NMOS and PMOS
devices
Si:C layers under non-doped-Si epitaxial channel (Epi-channel) produces steep channel profile for 25 nm-L<sub>G</sub> nMOSFET. Si:C layers work as the dopant-diffusion-barriers from the boron doped regions. Moreover, retrograde Halo profiles are also realized in this structure. Steep channel profiles at scaled device are confirmed, and the benefits of its profile at L<sub>G</sub> of 25 nm are discussed.
In sub-100-nm processes, many physical phenomena have become critical issues in the development of processes, devices, and circuits. To achieve reasonable compromise in ASIC design, device-and process-level characterization of physical designs is a fundamental requirement. In this paper, we address topics regarding "design for variability", which are increasingly important in the 65- to 90-nm technology era. We have developed a new test-structure to precisely measure the on-chip variation of key LSI components (MOST, R, C, and circuit-delay). Statistical analysis of the experimental results revealed that the 3σ variation of MOS drive-current within a chip was 30%, which led to equal variation in the circuit propagation delay (Tpd). We found that variation can be suppressed due to its randomness features in multi-stage circuitry and high-performance, large-gate-area driver CMOS devices.
A scaling theory for double-gate SOI MOSFETs, which gives guidance
for device design (silicon thickness t<sub>si</sub>; gate oxide
thickness t<sub>ox</sub>) that maintains a subthreshold factor for a
given gate length is discussed. According to the theory, a device can be
designed with a gate length of less than 0.1 μm while maintaining the
ideal subthreshold factor. This is verified numerically with a
two-dimensional device simulator
Scaling the Si MOSFET is reconsidered. Requirements on
subthreshold leakage control force conventional scaling to use high
doping as the device dimension penetrates into the deep-submicrometer
regime, leading to an undesirably large junction capacitance and
degraded mobility. By studying the scaling of fully depleted SOI
devices, the important concept of controlling horizontal leakage through
vertical structures is highlighted. Several structural variations of
conventional SOI structures are discussed in terms of a natural length
scale to guide the design. The concept of vertical doping engineering
can also be realized in bulk Si to obtain good subthreshold
characteristics without large junction capacitance or heavy channel
doping
Mountain View, CA, Sentaurus User's Manual
- Inc Synopsys
Synopsys, Inc., Mountain View, CA, Sentaurus User's Manual, 2009.06,
2009.
Multigate FET design for tolerance to statistical dopant fluctuations
- V Varadarajan
- L Smith
- S Balasubramanian
- T.-J. King Liu
V. Varadarajan, L. Smith, S. Balasubramanian, and T.-J. King Liu, "Multigate FET design for tolerance to statistical dopant fluctuations," in
Proc. IEEE Silicon Nanoelectron. Workshop, 2006, pp. 137-138.