Rohit Lorenzo

VIT University | VIT · School of Electronics Engineering (SENSE)

There is an intensive demand for energy-efficient computing gadgets. To optimize the arithmetic unit of these devices, this paper presents a 1-bit full adder cell designed using a hybrid logic scheme. The reported cell employs 18-transistors and performs better than existing hybrid full adder cells, while maintaining full swing output and minimum c...

This paper analyses the performance of 5 nm gate length gate engineered oxide stack silicon on insulator (SOI) fin field-effect transistor (OS-Fin-FET) for the first time. The high dielectric (High-K) value of the material-based gate oxide stack structure increases both the analog and the radio frequency (RF) performance of the Fin-FET device when...

Over the past four decades, single event upset (SEU) and single event multiple node upset (SEMNU) have become the major issues in the memory area. Moreover, these upsets are prone to reliability issues in space, terrestrial, military, and medical applications. This article concisely reviews different researchers and academicians who proposed resili...

This work presents a robust and low leakage new 8T static random access memory (SRAM) cell without any half‐selection disturbance. The proposed cell removes write disturbance by eliminating the trail from supply and ground. Furthermore, it removes the read disturbance by separating the read trail from the storage node. The proposed cell addresses t...

In present days, the improved performance in nanoscale dimensions is of enormous need than conventional CMOS devices. This paper presents an insight into Trigate FinFET in 5 nm technology using ATLAS 2D simulator. The drain current model based on surface potential calculation is shown to study the performance of tri gate FinFET. The 2D Poisson’s eq...

This study aims for a new 11T static random access memory (SRAM) cell that uses power gating transistors and transmission gate for low leakage and reliable write operation. The proposed cell has a separate read and write path which successfully improves read and write abilities. Furthermore, it solves the row half select disturbance and utilises a...

Leakage power dissipation is the dominant contributor of total power dissipation in nanoscale complementary metal oxide semiconductor (CMOS) integrated circuits. CMOS technology scaling demands for a reduced power supply, low threshold voltage, high transistor density and reduced oxide thickness, which has led to significant increase in leakage pow...

A novel 9T-SRAM architecture is proposed in this paper. It smartly integrates the source biasing and body-bias control schemes in designing an SRAM cell. The proposed cell consists of nine transistors with separate read/write ports. It uses a read word-line based body bias controller and two tail transistors in pull-down path to improve the design...

A dynamic threshold voltage control strategy is presented in this paper to minimize leakage power while enhancing the speed and stability. The threshold voltage of driver and access transistor are tuned dynamically through a novel body-bias controller circuit. The word line signal level controls the action of the proposed body-bias controller. In o...

Ever increasing demand for portable and battery-operated systems has lead to aggressive scaling. While technology scaling facilitates faster and high performance devices, at the same time it causes excessive power dissipation. Leakage power dissipation is now a dominating component of total power consumption in such portable devices. So there is...

The stability, leakage power and speed of Static random access memory (SRAM) have become an important issue with CMOS technology scaling. In this paper, a controller circuit is introduced which is separately controlling the load, driver and access transistors of SRAM cell. Based on word line signal value, optimal body bias voltage is generated thro...

In this paper a body bias technique is proposed for leakage minimization in CMOS VLSI circuits. A gate level body bias controller circuit is designed which dynamically change the threshold voltage of NMOS transistors. When the NMOS transistor is in OFF state, the threshold voltage of transistor is raised by applying reverse body bias through the co...

In this paper, a comparison between Single Gate Fully Depleted SOI (SGSOI) and Double Gate Fully Depleted SOI (DGSOI) MOSFET with Si3N4 Spacer (insulator) around the Gate electrode at various different technology nodes are investigated. Simulations are done in ATLAS package of SIVACO tool. Further in this work, study of SON Devices (structure with...

This paper presents a novel design to reduce sub threshold leakage current. The leakage controlled transistors are utilized to change dynamically the ground voltage level which is based on output voltage level of logic gate. The leakage controlled transistors (LCT's) are utilized to reduce the leakage power and static energy consumption (static pow...

In this paper a new SRAM cell is designed with a body bias controller to control leakage, speed and stability. A novel controller circuit is proposed to control the value of threshold voltage. Operation of the proposed controller is based on word line signal levels. In order to reduce sub threshold leakage current, the NMOS access and driver transi...

This paper presents a comprehensive survey and analysis of various subthreshold leakage power reduction techniques. Moreover, a new technique for low leakage and high speed is also proposed here. As the technology scales down to deep sub micron level, leakage power dissipation increases very rapidly due to the high transistor density, low threshold...

Leakage power dissipation has become a dominating proportion of the total power dissipation. According to international technology roadmap semiconductor (ITRS), this directly affects the portable battery operated device like mobile phones. A detailed analysis of leakage reduction data retention leakage feedback approaches are discussed in this pape...

Leakage power consumption has become serious concern for circuit designers. It is expected that leakage power will dominate the total power dissipation in future VLSI circuits. We here propose a new design named “NMOS leakage feedback” which reduces leakage current while saving exact logic state. The circuit technique includes addition of NMOS help...

In this paper we propose a new structure for NMOS based leakage feedback approach. The new proposed circuit technique includes NMOS only sleep transistors in parallel to both pull-up and pull-down paths which will reduce subthreshold current while saving the exact logic state. Based on 45nm Berkeley predictive technology model (BSIM 4), post layout...

Now a day's low power Design is a essential requirement for This electronic document is a “live” template. The various components of your paper [title, text, heads, etc.] are already defined on the style hardware implementation. Technology moving into deep submicron region causes increase in leakage power. MTCMOS is promising technique for reducing...