Manisha Pattanaik

ABV-Indian Institute of Information Technology and Management Gwalior | IIITM · PhD Program in IT Strategy

The von Neumann computing architecture faces considerable challenges (e.g., high throughput and improving energy efficiency) in developing artificial intelligence (AI) edge devices. In-memory computation (IMC) is a new computing paradigm to improve the energy efficiency and the throughput of dot product operations for AI edge devices. In this paper...

p>Hardware Trojan (HT) is the most critical threat due to outsourcing of Integrated circuit designing phases. Therefore, a new technique is proposed that utilizes structural and SCOAP features to detect HT from the gate-level netlist using Light Gradient Boosting (Light GBM). Further, a model agnostic Shapley additive explanations (SHAP) is employe...

p>Hardware Trojan (HT) is the most critical threat due to outsourcing of Integrated circuit designing phases. Therefore, a new technique is proposed that utilizes structural and SCOAP features to detect HT from the gate-level netlist using Light Gradient Boosting (Light GBM). Further, a model agnostic Shapley additive explanations (SHAP) is employe...

Hardware Trojan (HT) intrusion at different integrated circuit (IC) phases is the most important concern for the semiconductor industries. Recently, machine learning (ML) models have been used to detect HT from the pre-silicon IC phase, which utilizes either structural or SCOAP gate level netlist features. However, the main concern is that an adver...

The In-Memory Computing (IMC) architecture based on Conventional 6T, 8T, and 10T SRAM suffers from compute disturbance, compute-failure, and half-select issues, which affect the reliability of In-Memory Boolean Computation (IMBC) operations. To overcome these problems, local bit-line Shared pass-gate Dual-Port 8T (SDP8T) SRAM-based IMC architecture...

The main focus of approximate dividers has been on ASIC-based designs. However, for emerging applications, there is a need to design approximate arithmetic units compatible with FPGA applications due to their inherent capabilities. A separate approximate design concept for ASIC and FPGA systems diminish the benefits of approximate computing techniq...

The current computing systems are facing von Neumann bottleneck (VNB) in modern times due to the high prominence on big-data applications such as artificial intelligence and neuromorphic computing. In-memory computation is one of the emerging computing paradigms to mitigate this VNB. In this paper, a memristor-based robust 7T2M Nonvolatile-SRAM (Nv...

This paper examines the performance of the proposed low DIBL Gate all around FET (GAAFET) based 6 T and 7 T SRAM cells on enhancing stability for low power applications. GAAFETs are used in cross-coupled inverter circuitry to increase the stability of proposed 6 T and 7 T SRAM cells as these cross-coupled inverters provide the closest ideal voltage...

This work presents a power-efficient and noise-efficient amplifier for ECG recordings. To improve power efficiency, all the transistors in the proposed amplifier is designed in sub-threshold region which gives high g\(_m\)/I\(_D\) ratio. To improve noise efficiency, inverter-based differential input stage is used in this proposed operational transc...

Approximate computing is an emerging computing technique for designing energy- and resource-efficient arithmetic circuits for error-resilient applications. Square root (SQR) computation is a fundamental and complex operation in various signal/image processing tasks. It demands high resource and energy consumption, making the square-rooter a crucial...

Static Random-Access Memory (SRAM) is widely considered to be the most important building block of microprocessor and “System on Chip” (SoC). Low stability, high-power, and low process tolerance have become critical issues in the traditional 6T cell. This paper introduces a new read/write decouple single-ended 9T SRAM cell with high stability, low...

It deals with small dataset and class imbalance problem arises in hardware Trojan detection

Gate all around FET (GAAFET) is a widely used device structure for designing analog and digital circuits. In this research paper, a common source amplifier is designed using a dual-metal nitride oxide gate all around FET (DM-NO GAAFET), and performance is investigated for gain, bandwidth, leakage power, and average power. Moreover, analytical expre...

In the research paper, the semi-analytical modelling is done for low drain-induced barrier lowering (DIBL) dual-metal gate all around FET (DM GAAFET). Vacuum and silicon nitride are considered in the act of the gate oxide material near drain region for dual-metal vacuum oxide gate all around FET (DM-VO GAAFET) and dual-metal nitride oxide gate all...

The involvement of external vendors in semiconductor industries increases the chance of hardware Trojan (HT) insertion in different phases of the integrated circuit (IC) design. Recently, several partial reverse engineering (RE) based HT detection techniques are reported, which attempt to reduce the time and complexity involved in the full RE proce...

Radiation environment generates high soft error rates in conventional SRAM. To overcome this issue, several radiation hardened by design SRAM circuits (12TRHBD, 13TRHBD, DICE, etc.) have been developed. Although many of the radiation hardened SRAM cells are there, all the circuits mainly concern a single node upset only. In this chapter, 16T radiat...

Energy efficiency has emerged as one of the most essential design parameter in contemporary computing system design. Approximate computing is a new computing paradigm to achieve energy efficiency by trading-off energy/area/latency improvements with accuracy for error-resilient applications. This paper proposes Reconfigurable Energy-efficient Approx...

Approximate computing has received significant recognition for enhancing energy-efficiency in error-resilient applications. This paper proposes bit significance based reconfigurable approximate restoring dividers and square rooters for improved energy-efficiency. Configurable subtractor cells (CSCs) which can function both accurately and approximat...

In this research work, a dual‐metal hetero‐dielectric with nitride gate all around field effect transistor (DM‐HD‐NA GAAFET) has been proposed to address and mitigate an essential issue of drain induced barrier lowering and tunnelling leakage current. This device also provides better transconductance, output conductance, early voltage, and transfor...

In real-life applications, certain images utilized are corrupted in which the image pixels are damaged or missing, which increases the complexity of computer vision tasks. In this paper, a deep learning architecture is proposed to deal with image completion and enhancement. Generative Adversarial Networks (GAN), has been turned out to be helpful in...

In order to support real-time HD video requirements for mobile and real time applications, energy-efficient design is the need of the hour for such low-cost devices. HEVC is the latest video compression standard that achieves high compression ratio and high bit-rate over existing architecture(H.264) but at the cost of higher computational complexit...

In this work, we have designed and simulated a Gate All Around TFET (GAATFET) based 3 stage ring oscillator circuit and compared its performance with the CMOS based counterpart. The results of SPICE simulations indicate that GAATFET based ring oscillator circuit consumes 3.5 times lower power consumption in active mode than CMOS based ring oscillat...

In this work, we have designed and simulated a Gate All Around TFET (GAATFET) based 3 stage ring oscillator circuit and compared its performance with the CMOS based counterpart. The results of SPICE simulations indicate that GAATFET based ring oscillator circuit consumes 3.5 times lower power consumption in active mode than CMOS based ring oscillat...

Tunnel FETs (TFETs) possess all required characteristics for replacing MOSFET device in circuits with stringent requirements particularly for Internet of Things (IoT) and Biomedical applications. In particular Gate-All-Around (GAA) TFET device configuration exhibits higher ION/IOFF ratio and strong control of the gate terminal over the channel. The...

Tunnel FETs (TFETs) possess all required characteristics for replacing MOSFET device in circuits with stringent requirements particularly for Internet of Things (IoT) and Biomedical applications. In particular Gate-All-Around (GAA) TFET device configuration exhibits higher ION/IOFF ratio and strong control of the gate terminal over the channel. The...

Low read stability and high leakage current are two major problems in Static Random Access Memory (SRAM) at the scaled CMOS technology node. This paper provides stability, leakage and process variation analysis of a Schmitt Trigger and read buffer based differential 10T (hereafter called ST3) SRAM cell. The ST3 cell provides improve read stability,...

This paper presents a low leakage noise tolerant (LL10T) SRAM cell. The proposed SRAM cell has high read static noise margin and low leakage power in contrast to the conventional 6T (C6T) SRAM cell. LL10T isolates the read circuitry through read decoupling technique to improve the read static noise margin by reducing the disturbance in read operati...

In deep submicrometer technology (below 65 nm), SRAM designs suffer from high leakage and low stability issues. This paper presents a low leakage highly stable SRAM cell with read-write enhanced circuitry. The proposed SRAM performs read-write operation through single bitline and have separate read-write circuitry. It consists of a sleep transistor...

Tunneling Field Effect Transistor (TFET) has emerged as an alternative device to MOSFET for designing low power analog and digital integrated circuits. This paper investigates the performance of a common source amplifier circuit designed using Gate-All-Around Hetero Dielectric Tri Material Gate TFET device. HD-TMGTFET device is designed on Visual T...

This paper investigates the performance of tri material gate tunnel field effect transistor (TMGTFET) device designed in gate all around (GAA) configuration. The device performance is analyzed by varying various device related parameters like: drain doping, oxide thickness and radius of silicon core. Simulations are performed using technology compu...

Development of novel electronic devices is an area of active research which reveals the potential of organic nano-materials towards efficient nano-devices application. In this letter, we have investigated the electronic transport properties of nitrogen (N) doped disconnected zigzag graphene nanoribbons (ZGNR). Six different configurations viz. N1,...

In this work we have analyzed the impact of charge carrier's injection mechanism on analog performance of amplifier. The present study is based on comparative analysis of two different FET based amplifiers i.e. Metal Oxide Semiconductor FET (MOSFET) amplifier and Sandwich Tunnel Barrier FET (STBFET) amplifier. The performance parameters for both th...

Estimation of static noise margin (SNM) is believed to be most important step of static random access memory (SRAM) bitcell design. Moreover, the measurement of bitcell stability is a critical issue with scaling of complementary metal-oxide semiconductor (CMOS) technology. Available techniques to find SNM are time consuming and difficult to impleme...

With continued scaling of VLSI circuits, reliability has emerged out as one of the major circuit design challenges. Systematic die-to-die, random on-die as well as temperature and supply voltage variations are major sources of performance degradation which leads to unreliable circuits. Further, with reduced short channel effects at highly scaled no...

As the VLSI technology is heading toward deep subnanometer range, the NBTI effect has emerged as a major reliability issue for the state-of-the-art CMOS as well as FinFET-based circuits. NBTI causes an incremental deviation in the threshold voltage of PMOS and hence causes variation in timing of digital circuits. Further, NBTI may increase the dela...

The conventional NOR-based decoders are one ofthe fastest dynamic decoder circuits employed in microprocessors. However, they suffer from a huge amount of power dissipationresulting from the presence of short circuit paths betweenthe supply and the ground through pull-down network. Twodecoder designs with a novel selective precharge circuit have be...

To make portable battery operated devices moreefficient with low leakage current is a major challenge with the technology scaling. The power dissipation is expected to increase further in next generation technologies because of the exponential increase in leakage currents with technology scaling. FinFET device was introduced as a suitable replaceme...

Efficient and process variation tolerant memory isthe current market demand especially for Portable devices. Inscaled down devices leakage current becomes comparable to theOn-State current. SRAM Cell remains in stand-by mode for mostof the time and accounts for maximum average power dissipation. This research work explores the existing built-in fee...

A design of an area efficient and low power 16 bit Multiply and Accumulate (MAC) unit is implemented in this paper. MAC unit performs various Digital Signal Processing applications generally contain number of repetitive methods having multiplications and additions. The MAC unit is designed by Modified Wallace Multiplier (MWM) using compressor with...

In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS digital standard cell library is developed. The developed standard cell library contains basic cells such as inverter, NAND, NOR, AND, OR and buffer logic cells and characterized at 32 nm bulk CMOS process technology. All cells are designed, at 32 nm technology node...

The previous few chapters focused on the variability issues of the nanoscale integrated circuits (ICs) for diverse applications including analog, radio frequency (RF), digital and memory ICs. The designs of such ICs are based on nanoscale bulk MOSFET and FinFET devices. The current chapter presents the leakage power dissipation which is an importan...

This chapter describes nanoscale FinFET devices and their application in SRAM design. It also discusses variability of nanoscale integrated circuits (ICs) and introduces variability-aware memory design. In the previous two chapters, process variations were discussed for analog and digital ICs. However, this chapter focuses on futuristic memory desi...

A double gated structure of Gate-Stack Doping-Less Tunnel Field Effect Transistor (GS-DLTFET) is proposed in this paper. Source and Drain regions of the FET are not doped using the charge plasma concept, which makes the device free from the random dopant fluctuation issue. A multi-layer structure is formed on the gate by imposing the layers of diel...

Leakage power dissipation, timing delay and high noise immunity in advanced embedded static random access memories cells are main critical issues in low power battery operated devices. The newly proposed FinFET based highly noise immune Power gated 6T SRAM design is targeting these areas and successfully suppress leakage power dissipation with main...

In this paper we have done performance comparison of double gate tunnel FET (DGTFET) and sandwich tunnel barrier FET (STBFET i.e., line tunnel FET) with temperature variation. It is noticed that the OFF state current of STBFET shows more variations with increased temperature than DGTFET counterparts. The impact of temperature variations at transcon...

In this paper we have investigated the impact of parameter variations on the performance of Sandwich tunnel barrier FET (STBFET) through numerical simulation. It is reported that variability in the parameters such as oxide thickness, gate alignment, dielectric constant, work function, epi-layer thickness have a significant impact on the performance...

This paper presents a high performance, energy efficient implicit pulsed triggered flip flop based on direct coupled pass transistor (DCPT) approach. This approach directly couple input D to output Q of the flip flop to alleviate the worst case delay. It reduces input to output travelled path hence reduces D-to-Q delay and power consumption. It als...

Technology enhancement has increased sensitivity of process variations of scaled SRAM on the verge of instability. This demands a process variation (PV) aware stability model for the modern SRAM. This paper first analyzes PV severity on readability, writability and static leakage current and provides a statistical model. The paper further improves...

Wide fan-in dynamic logic OR gate has always been an integral part of high speed microprocessors. However, low noise immunity of wide fan-in dynamic logic gate is always an issue of concern. For maintaining high noise immunity, various large sized PMOS keeper-based dynamic OR gates are proposed in the literature. These designs allow large leakage t...

To draw an accurate relationship between power dissipation and speed is a challenging problem in operational Amplifier with switch capacitance. However, transformation of current steer circuit into charge steer is an efficient technique to reduce power dissipation even at higher speed. In this paper, an efficient model is proposed to estimate the 1...

Near threshold operation of device and circuit is still a challenging area with conventional MOSFET topologies. This paper presents the performance comparison of Ge/Si double gate tunnel FET (DGTFET) and pocket DGTFET in terms of ON state and OFF state current. The Ge DGTFET has higher ON current than Si DGTFET and less ON current than pocket DGTFE...

A new 1-bit full adder cell has been introduced in this paper. According to this approach body-biasing and semi domino logic both are used in a single full adder. Body-biasing technique is used to vary the threshold voltage to operate this adder at higher speed by allowing the faster gate switching. The important thing in this approach is that ther...

In this paper, programming characteristics of two- bit SONOS (silicon-oxide-nitride-oxide-silicon) with high-k dielectric material is analysed. Two bit is used for increment of storage density instead of a single cell. Hafnium Oxide has good programming characteristics, so in this design Hafnium Oxide as high-k material is used. This material is re...

As the technology is moving towards nanoscaled device dimensions, the Process, Voltage and Temperature (PVT) variations have become dominant parameters of increased SRAM failure probability and loss of manufacturing yield. In this paper, we proposed three Independently controlled double-Gate FinFET (IDG-FinFET) based SRAM topologies for PVT toleran...

This paper presents a two stage process for image de-noising and edge enhancement by applying singular value decomposition technique on anisotropic diffused images. The two diffused versions of the input noisy image are generated in the first stage by anisotropic diffusion. The first diffused image is a well smoothed image and the second diffused i...

With rapid scaling in Deep Sub-micron (DSM) technologies, the difference between supply and threshold voltage is decreasing rapidly. This makes delay of the circuit highly sensitive to gate overdrive voltage with temperature fluctuations. In sub-100nm technologies, the delay of the circuit decreases with increase in temperature, known as Inverted T...

Process variation is become future design challenge in ultra scaled identically designed Static Random Access Memory (SRAM), hence amendment in SRAM is needed. In this paper, we propose a novel low-power sensitivity-driven and inter-die process variation aware 10T SRAM cell via selective back-gate (SBG) biasing technique with independent-double-gat...

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is...

Abstract: A 3-stage voltage controlled variable gain amplifier (VGA) for GHz range of application has been designed by using charge steering technique and simulated in a 65nm CMOS technology. The proposed voltage controlled VGA is characterized by wide range of gain variation, less temperature dependence gain characteristic, ultra-low power dissipa...

The development of the large scale multi-electrode neural-recording systems has accelerated the process of brain monitoring. Neural amplifier is the most important development in this field. A fully integrated low-noise tunable neural amplifier is presented in this paper. The proposed neural amplifier not only provides low signal distortion and hig...

This paper provides a robust scheme for random valued impulsive noise reduction along with edge preservation by anisotropic diffusion with improved diffusivity. The defective impulse noisy pixels are detected by Laplacian based second order pixel difference operation where these defective pixels are replaced by appropriate values with regard of the...

On the basis of ab-initio calculations, we predict the effect of conformation and molecule-electrode distance on transport properties of asymmetric molecular junctions for different electrode materials M (M = Au, Ag, Cu, and Pt). The asymmetry in these junctions is created by connecting one end of the biphenyl molecule to conjugated double thiol (m...

In this work, we discuss the origin and temperature dependence of various mechanisms behind the flow of leakage current in two topologies of TFET – basic TFET and pocket doped TFET. It is shown that the leakage current of pocket doped TFET shows relatively less variations with change in temperature when compared with MOSFET and basic TFET, and henc...

The demand of low power high density integrated circuits is increasing in modern battery operated portable systems. Sub-threshold region of MOS transistors is the most desirable region for energy efficient circuit design. The operating ultra-low power supply voltage is the key design constraint with accurate output performance in sub-threshold regi...

We analyze the effect of electrode materials Y (Y=Ag, Cu, and Pt) on electronic transport properties of asymmetric biphenyl molecular junctions using first-principles calculations. To introduce coupling asymmetry in these junctions, one end of the biphenyl molecule is terminated by conjugated double thiol (model A) and single thiol (model B) anchor...

Aggressively scaled SRAM is highly vulnerable to short channel and process variation effects. FinFET technology emerges as a device level solution to overcome these scaling limitations while assist techniques aid super-scaled SRAM to achieve better performance and stability. In this paper, we propose two operation-aware assist circuits, namely, Spl...