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The layout of an 8-bit pipelined ADC

The layout of an 8-bit pipelined ADC

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Figure 3. The layout of an 8-bit pipelined ADC
Research of Design Technologies for 8-bit High Speed Low Power Pipelined ADC
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  • Dec 2018
8-bit, 80MS/s low power ADC is presented in this paper by using seven stage Pipelined architecture. To reduce the chip size and power of total ADC, and improve the harmonic distortion and noise property, MDAC in first sub-ADC is considered focused, The whole ADC was designed in 0.18μm CMOS process, the SNR of the ADC is 53dB, ENOB is 7.98bits. The...
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... on the above design idea, the design of the entire ADC is completed. Figure 3 is the layout of the entire 8 bit Pipelined ADC. The above ADC is designed based on 0.18μm process platform. ...

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