Yasuaki Nishitani's research while affiliated with Iwate University and other places

In this paper, we propose a design of reversible adder/subtractor blocks and arithmetic logic units (ALUs). The main concept of our approach is different from that of the existing related studies; we emphasize the function design. Our approach of investigating the reversible functions includes (a) the embedding of irreversible functions into incompletely-specified reversible functions, (b) the operation assignment, and (c) the permutation of function outputs. We give some extensions of these techniques for further improvements in the design of reversible functions. The resulting reversible circuits are smaller than that of the existing design in terms of the number of multiple-control Toffoli gates. To evaluate the quantum cost of the obtained circuits, we convert the circuits to reduced quantum circuits for experiments. The results also show the superiority of our realization of adder/subtractor blocks and ALUs in quantum cost.

We present a new lower bound on the number of gates in reversible logic circuits that represent a given reversible logic function, in which the circuits are assumed to consist of general Toffoli gates and have no redundant input/output lines. We make a theoretical comparison of lower bounds, and prove that the proposed bound is better than the previous one. Moreover, experimental results for lower bounds on randomly-generated reversible logic functions and reversible benchmarks are given. The results also demonstrate that the proposed lower bound is better than the former one.

We propose a testable decimal multiplication circuit under the single cell fault model. The multiplier consists of iterative logic arrays of partial product generators and adders. We also give a set of test patterns to detect single faults in the circuit. The number of test patterns is proportional to that of the input digits of the multiplier, which is significantly smaller than the exponential number of test patterns required in non-testable circuits. This efficient testability is achieved only by as light change of the function in the partial product generators and an insertion of some testing inputs in the adders. No additional hardware modules are required in the proposed realization.

We propose faster-computing methods for the minimization algorithm of AND–EXOR expressions, or exclusive-or sum-of-products expressions (ESOPs), and obtain the exact minimum ESOPs of benchmark functions. These methods improve the search procedure for ESOPs, which is the most time-consuming part of the original algorithm. For faster computation, the search space for ESOPs is reduced by checking the upper and lower bounds on the size of ESOPs. Experimental results to demonstrate the effectiveness of these methods are presented. The exact minimum ESOPs of many practical benchmark functions have been revealed by this improved algorithm.

Exclusive-or sum-of-products expressions (ESOPs) are the most general AND-EXOR expressions. This paper presents a new data structure called a function product (FP) and an algorithm for obtaining simplified ESOPs through transformation of FPs. The algorithm takes the following steps: converting an initial ESOP into an EXOR of FPs (EX-FP), simplifying the EX-FP by repeating the transformation of FPs, and reconverting the resulting EX-FP into the simplified ESOP. The authors give experimental results on benchmarks to demonstrate the superiority of the method in reduction of literals

We propose three search methods for obtaining exact minimum AND-EXOR expressions: the depth-first, the breadth-first, and the depth-first-when-optimum searches. They minimize up to 7-variable functions in a practical computation time. Experimental results to compare the efficiency of these methods are presented. The depth-first search, which saves the memory consumption, minimizes the 16-variable benchmark function t481 without memory exhaustion. This search method is the fastest among these three methods on the average computation time for randomly-generated single-output functions. The depth-first-when-optimum search is the fastest on the computation time for the most of benchmark functions. For some benchmark functions, however, the breadth-first search is the fastest

We propose a faster algorithm of minimizing AND-EXOR expressions. While it has been considered difficult to obtain the minimum AND-EXOR expression of a given function with six variables in a practical computing time, our algorithm can compute the minimum AND-EXOR expressions of any six-variable and some seven-variable functions practically. In this paper, we first present a naive algorithm that searches the space of expansions of a given n-variable function f for a minimum expression of f. The space of expansions are generated by using all combinations of (n-1)-variable product terms. Then, how to prune the branches in the search process and how to restrict the search space to obtain the minimum solutions are discussed as the key point of reduction of the computing time. Finally, a faster algorithm is constructed by using the methods discussed. Experimental results to demonstrate the effectiveness of these methods are also presented.