Raymond Lo's research while affiliated with Mountain View College and other places
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Publications (8)
We present techniques that allow strength reduction to be performed concurrently with partial redundancy elimination in the SSAPRE framework. By sharing the characteristics inherent to SSAPRE, the resulting strength reduction algorithm exhibits many interesting attributes. We compare various aspects of the new strength reduction algorithm with prev...
. This paper addresses the problems of representing aliases and indirect memory operations in SSA form. We propose a method that prevents explosion in the number of SSA variable versions in the presence of aliases. We also present a technique that allows indirect memory operations to be globally commonized. The result is a precise and compact SSA r...
The SSAPRE algorithm for performing partial redundancy elimination based entirely on SSA form is presented. The algorithm is formulated based on a new conceptual framework, the factored redundancy graph, for analyzing redundancy, and represents the first sparse approach to the classical problem of partial redundancy elimination. At the same time, i...
An algorithm for register promotion is presented based on the observation that the circumstances for promoting a memory location's value to register coincide with situations where the program exhibits partial redundancy between accesses to the memory location. The recent SSAPRE algorithm for eliminating partial redundancy using a sparse SSA represe...
A new algorithm, SSAPRE, for performing partial redundancy elimination based entirely on SSA form is presented. It achieves optimal code motion similar to lazy code motion [KRS94a, DS93], but is formulated independently and does not involve iterative data flow analysis and bit vectors in its solution. It not only exhibits the characteristics common...
Loop induction variable canonicalization transforms a loop to use a single primary induction variable that is incremented by one at the end of each iteration. In this process, other induction variables in the loop, called secondary induction variables, are removed from the loop, with their original references expressed in terms of the primary induc...
The paper presents a technique called Global Instruction Distribution that globally fine-tunes the code produced for a superscalar processor. The fine-tuning is effected by distributing instructions from one block to other blocks according to the control flow graph of the program. The method does not involve instruction scheduling, but models resou...
Citations
... In memory-oriented scientific approaches, there are studies on reducing program code size and saving memory by using compiler optimization flags [18][19][20][21]. In addition, there are some studies in the literature on saving memory through methods, such as reducing code size by memory optimization, eliminating sub-expressions, and cleaning up dead code [22,23]. ...
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... De forma análoga ao grafo de fluxo de controle apresentado na Seção anterior, o grafo de fluxo de dados (DFG, Data Flow Graph em Inglês) modela as interdependências entre instruções em função de seus operandos. Devido à maior complexidade quando comparado ao CFG, é comum que um DFG seja computado apenas dentro dos blocos básicos que o analisador considerar relevantes [21]. ...
... LLVM implements a variation of the technique proposed by Pop [22]. In this paper, it is primarily useful to support induction variable canonicalization [16], and to generate code for address generators [8,15]. ...
... Domagala et al. [10] focus their research on the optimization of RA for the loops of the program. ey presented and implemented in the Open64 compiler an approach to register allocation and register promotion [28] that considers the impacts of IS and loop unrolling. e tests indicated a substantial improvement in the number of spills for many loops with high register pressure. ...
... Saabas and Uustalu use type-systems framework to approach this problem [4]. Some Optimizations have been added to PRE such as strength reduction [5] and global value numbering [6]. All methods mentioned above are established to operate on sequential programs. ...
... strong updates in the same way as tracking scalar value-flows. It is similar to the idea proposed by Chow et al. [6] and Memo-rySSA [24]. In contrast to previous works, dfi.store adopts a lightweight design and excludes weak updates on addresstaken variables (i.e. ...
... Graal IR is a structured, directed graph consisting of nodes that represent the control flow and the data flow of a method. The IR is in static single assignment form [19,25,59,60,84], with φ nodes representing values that depend on the current path (e.g., a φ node captures an assignment whose value is branch-dependent, a loop φ represents values modified in a loop). To enable traversal of the IR during compilation, Graal IR nodes are typically scheduled within basic blocks [20,70]. ...
