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Mechanically Flexible Optically Transparent Silicon Fabric with High Thermal Budget Devices from Bulk Silicon (100)
Abstract
Today’s information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor – heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon – industry’s darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 m thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).
... technology achieves both flexibility and good functionality by combining an ultrathin chip (UTC) consisting of single-crystal silicon and printed electronics. When a silicon-based electronic device is thinned to a thickness of less than 20 µm by chemical mechanical polishing (CMP), dry etching, and MEMS processing, (14)(15)(16)(17)(18) it becomes flexible. Vanfleteren's group fabricated an ultrathin microcontroller unit (MCU) with flexibility and good performance, (19,20) and demonstrated that an MCU with a thickness of 20 µm can operate when its radius of curvature is 3.3 mm. ...
Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered.
— A scalable manufacturing process for fabricating active-matrix backplanes on low-cost flexible substrates, a key enabler for electronic-paper displays, is presented. This process is based on solution processing, ink-jet printing, and laser patterning. A multilayer architecture is employed to enable high aperture ratio and array performance. These backplanes were combined with E Ink electrophoretic media to create high-performance displays that have high contrast, are bistable, and can be flexed repeatedly to a radius of curvature of 5 mm.
This letter introduces a type of thin-film transistor that uses aligned arrays of thin (submicron) ribbons of single-crystal silicon created by lithographic patterning and anisotropic etching of bulk silicon (111) wafers. Devices that incorporate such ribbons printed onto thin plastic substrates show good electrical properties and mechanical flexibility. Effective device mobilities, as evaluated in the linear regime, were as high as 360 cm2 V−1 s−1, and on/off ratios were >103. These results may represent important steps toward a low-cost approach to large-area, high-performance, mechanically flexible electronic systems for structural health monitors, sensors, displays, and other applications.
Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to producing thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).
Decade long research in 1D nanowire field effect transistors (FET) shows although it has ultra-low off-state leakage current and a single device uses a very small area, its drive current generation per device is extremely low. Thus it requires arrays of nanowires to be integrated together to achieve appreciable amount of current necessary for high performance computation causing an area penalty and compromised functionality. Here we show that a FET with a nanotube architecture and core-shell gate stacks is capable of achieving the desirable leakage characteristics of the nanowire FET while generating a much larger drive current with area efficiency. The core-shell gate stacks of silicon nanotube FETs tighten the electrostatic control and enable volume inversion mode operation leading to improved short channel behavior and enhanced performance. Our comparative study is based on semi-classical transport models with quantum confinement effects which offers new opportunity for future generation high performance computation.
Gate-first integration of tunable work function metal gates of different thicknesses (3-20 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (V<sub>Th</sub>) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ~40 mV/V), nearly symmetric V<sub>Th</sub>, low T<sub>inv</sub> (~1.4 nm), and high I<sub>on</sub> (~780 ¿A/¿m) for N/PMOS without any intentional strain enhancement.
A single-crystal silicon, high aspect ratio, low-temperature process sequence for the fabrication of suspended microelectromechanical structures (MEMS) using a single lithography step and reactive ion etching (RIE) is presented. The process is called SCREAM I (single-crystal reactive etching and metallization). SCREAM I is a bulk micromachining process that uses RIE of a silicon substrate to fabricate suspended movable single-crystal silicon (SCS) beam structures. Beam elements with aspect ratios of 10 to 1 and widths ranging from 0.5 to 4.0 μm have been fabricated. All process steps are low temperature (<300 °C), and only conventional silicon fabrication tools are used: photolithography, RIE, MIE, plasma-enhanced chemical-vapor deposition (PECVD) and sputter deposition. SCREAM I is a self-aligned process and uses a single lithography step to define beams and structures simultaneously as well as all necessary contact pads, electrical interconnects and lateral capacitors. SCREAM I has been specifically designed for integration with standard integrated circuit (IC) processes, so MEM devices can be fabricated adjacent to prefabricated analog and digital circuitry. In this paper we present process parameters for the fabrication of discrete SCREAM I devices. We also discuss mask design rules and show micrographs of fabricated devices.
We report classes of electronic systems that achieve thicknesses, effective elastic moduli, bending stiffnesses, and areal
mass densities matched to the epidermis. Unlike traditional wafer-based technologies, laminating such devices onto the skin
leads to conformal contact and adequate adhesion based on van der Waals interactions alone, in a manner that is mechanically
invisible to the user. We describe systems incorporating electrophysiological, temperature, and strain sensors, as well as
transistors, light-emitting diodes, photodetectors, radio frequency inductors, capacitors, oscillators, and rectifying diodes.
Solar cells and wireless coils provide options for power supply. We used this type of technology to measure electrical activity
produced by the heart, brain, and skeletal muscles and show that the resulting data contain sufficient information for an
unusual type of computer game controller.
The development of optically transparent and mechanically flexible electronic circuitry is an essential step in the effort to develop next-generation display technologies, including 'see-through' and conformable products. Nanowire transistors (NWTs) are of particular interest for future display devices because of their high carrier mobilities compared with bulk or thin-film transistors made from the same materials, the prospect of processing at low temperatures compatible with plastic substrates, as well as their optical transparency and inherent mechanical flexibility. Here we report fully transparent In(2)O(3) and ZnO NWTs fabricated on both glass and flexible plastic substrates, exhibiting high-performance n-type transistor characteristics with approximately 82% optical transparency. These NWTs should be attractive as pixel-switching and driving transistors in active-matrix organic light-emitting diode (AMOLED) displays. The transparency of the entire pixel area should significantly enhance aperture ratio efficiency in active-matrix arrays and thus substantially decrease power consumption.
Inorganic light-emitting diodes and photodetectors represent important, established technologies for solid-state lighting, digital imaging and many other applications. Eliminating mechanical and geometrical design constraints imposed by the supporting semiconductor wafers can enable alternative uses in areas such as biomedicine and robotics. Here we describe systems that consist of arrays of interconnected, ultrathin inorganic light-emitting diodes and photodetectors configured in mechanically optimized layouts on unusual substrates. Light-emitting sutures, implantable sheets and illuminated plasmonic crystals that are compatible with complete immersion in biofluids illustrate the suitability of these technologies for use in biomedicine. Waterproof optical-proximity-sensor tapes capable of conformal integration on curved surfaces of gloves and thin, refractive-index monitors wrapped on tubing for intravenous delivery systems demonstrate possibilities in robotics and clinical medicine. These and related systems may create important, unconventional opportunities for optoelectronic devices.
Compound semiconductors like gallium arsenide (GaAs) provide advantages over silicon for many applications, owing to their direct bandgaps and high electron mobilities. Examples range from efficient photovoltaic devices to radio-frequency electronics and most forms of optoelectronics. However, growing large, high quality wafers of these materials, and intimately integrating them on silicon or amorphous substrates (such as glass or plastic) is expensive, which restricts their use. Here we describe materials and fabrication concepts that address many of these challenges, through the use of films of GaAs or AlGaAs grown in thick, multilayer epitaxial assemblies, then separated from each other and distributed on foreign substrates by printing. This method yields large quantities of high quality semiconductor material capable of device integration in large area formats, in a manner that also allows the wafer to be reused for additional growths. We demonstrate some capabilities of this approach with three different applications: GaAs-based metal semiconductor field effect transistors and logic gates on plates of glass, near-infrared imaging devices on wafers of silicon, and photovoltaic modules on sheets of plastic. These results illustrate the implementation of compound semiconductors such as GaAs in applications whose cost structures, formats, area coverages or modes of use are incompatible with conventional growth or integration strategies.
At present, flexible displays are an important focus of research. Further development of large, flexible displays requires a cost-effective manufacturing process for the active-matrix backplane, which contains one transistor per pixel. One way to further reduce costs is to integrate (part of) the display drive circuitry, such as row shift registers, directly on the display substrate. Here, we demonstrate flexible active-matrix monochrome electrophoretic displays based on solution-processed organic transistors on 25-microm-thick polyimide substrates. The displays can be bent to a radius of 1 cm without significant loss in performance. Using the same process flow we prepared row shift registers. With 1,888 transistors, these are the largest organic integrated circuits reported to date. More importantly, the operating frequency of 5 kHz is sufficiently high to allow integration with the display operating at video speed. This work therefore represents a major step towards 'system-on-plastic'.
Skin-like sensitivity, or the capability to recognize tactile information, will be an essential feature of future generations of robots, enabling them to operate in unstructured environments. Recently developed large-area pressure sensors made with organic transistors have been proposed for electronic artificial skin (E-skin) applications. These sensors are bendable down to a 2-mm radius, a size that is sufficiently small for the fabrication of human-sized robot fingers. Natural human skin, however, is far more complex than the transistor-based imitations demonstrated so far. It performs other functions, including thermal sensing. Furthermore, without conformability, the application of E-skin on three-dimensional surfaces is impossible. In this work, we have successfully developed conformable, flexible, large-area networks of thermal and pressure sensors based on an organic semiconductor. A plastic film with organic transistor-based electronic circuits is processed to form a net-shaped structure, which allows the E-skin films to be extended by 25%. The net-shaped pressure sensor matrix was attached to the surface of an egg, and pressure images were successfully obtained in this configuration. Then, a similar network of thermal sensors was developed with organic semiconductors. Next, the possible implementation of both pressure and thermal sensors on the surfaces is presented, and, by means of laminated sensor networks, the distributions of pressure and temperature are simultaneously obtained.
Strain plays a critical role in the properties of materials. In silicon and silicon-germanium, strain provides a mechanism for control of both carrier mobility and band offsets. In materials integration, strain is typically tuned through the use of dislocations and elemental composition. We demonstrate a versatile method to control strain by fabricating membranes in which the final strain state is controlled by elastic strain sharing, that is, without the formation of defects. We grow Si/SiGe layers on a substrate from which they can be released, forming nanomembranes. X-ray-diffraction measurements confirm a final strain predicted by elasticity theory. The effectiveness of elastic strain to alter electronic properties is demonstrated by low-temperature longitudinal Hall-effect measurements on a strained-silicon quantum well before and after release. Elastic strain sharing and film transfer offer an intriguing path towards complex, multiple-layer structures in which each layer's properties are controlled elastically, without the introduction of undesirable defects.
Commercial ultrafiltration and dialysis membranes have broad pore size distributions and are over 1,000 times thicker than the molecules they are designed to separate, leading to poor size cut-off properties, filtrate loss within the membranes, and low transport rates. Nanofabricated membranes have great potential in molecular separation applications by offering more precise structural control, yet transport is also limited by micrometre-scale thicknesses. This limitation can be addressed by a new class of ultrathin nanostructured membranes where the membrane is roughly as thick (approximately 10 nm) as the molecules being separated, but membrane fragility and complex fabrication have prevented the use of ultrathin membranes for molecular separations. Here we report the development of an ultrathin porous nanocrystalline silicon (pnc-Si) membrane using straightforward silicon fabrication techniques that provide control over average pore sizes from approximately 5 nm to 25 nm. Our pnc-Si membranes can retain proteins while permitting the transport of small molecules at rates an order of magnitude faster than existing materials, separate differently sized proteins under physiological conditions, and separate similarly sized molecules carrying different charges. Despite being only 15 nm thick, pnc-Si membranes that are free-standing over 40,000 microm2 can support a full atmosphere of differential pressure without plastic deformation or fracture. By providing efficient, low-loss macromolecule separations, pnc-Si membranes are expected to enable a variety of new devices, including membrane-based chromatography systems and both analytical and preparative microfluidic systems that require highly efficient separations.
We introduce a method to fabricate high-performance field-effect transistors on the surface of freestanding organic single crystals. The transistors are constructed by laminating a monolithic elastomeric transistor stamp against the surface of a crystal. This method, which eliminates exposure of the fragile organic surface to the hazards of conventional processing, enables fabrication of rubrene transistors with charge carrier mobilities as high as approximately 15 cm2/V.s and subthreshold slopes as low as 2nF.V/decade.cm2. Multiple relamination of the transistor stamp against the same crystal does not affect the transistor characteristics; we exploit this reversibility to reveal anisotropic charge transport at the basal plane of rubrene.
A new method for the fabrication of micro structures for fluidic
applications, such as channels, cavities, and connector holes in the
bulk of silicon wafers, called buried channel technology (BCT), is
presented in this paper. The micro structures are constructed by trench
etching, coating of the sidewalls of the trench, removal of the coating
at the bottom of the trench, and etching into the bulk of the silicon
substrate. The structures can be sealed by deposition of a suitable
layer that closes the trench. BCT is a process that can be used to
fabricate complete micro channels in a single wafer with only one
lithographic mask and processing on one side of the wafer, without the
need for assembly and bonding. The process leaves a substrate surface
with little topography, which easily allows further processing, such as
the integration of electronic circuits or solid-state sensors. The
essential features of the technology, as well as design rules and
feasible process schemes, will be demonstrated on examples from the
field of μ-fluidics
Longitudinal piezoresistance (pi) coefficients for n- and p-type double-gate (DG) FinFETs with sidewall channels along (110) surface and (110) channel direction are measured via wafer-bending experiments (51.4 and -37 X 10 <sup>-11</sup> Pa<sup>-1</sup> for n- and p-FinFETs, respectively) and are found to differ from bulk Si (110) (31.2 and -71.8 X 10 <sup>-11</sup> Pa<sup>-1</sup> for n- and p-Si, respectively). Compressive and tensile contact-etch-stop liners (CESLs) are fabricated on DG FinFETs and are found to induce higher channel stress than in planar MOSFETs, with 30% enhancement in the saturation current for the shortest channel-length devices in both n- and p-MOSFETs, whereas the long devices show little or no enhancement. The channel-length dependence of the enhancement suggests that stress coupling into the FinFET channels from the CESL occurs via the fin extensions and not through the gate.
After the demonstration of the first organic FET in 1986, a new era in the field of electronic began: the era of organic electronics. Although the reported performance of organic transistors is still considerably lower compared to that of silicon transistors, a new market is open for organic devices, where the excellent performance of silicon technology is not required. Several commercial applications for organic electronics have been suggested: organic RFID tags, electronic papers, imagers, sensors, organic LED drivers, etc. The main advantage of organic technologies over silicon technologies is the possibility of making low-cost, large area electronics. The main processes which allow patterning with suitable resolution on a large areas are printing methods. Here we will provide an overview of methods that can be useful in the low-cost production of large area electronics.
While the scaling efforts continue into a device regime performance simply may not come without large scale off state leakage issues, significant device changes are being considered such as FinFETs. The concept of a double- or triple-channel device is not new, but the practical roadblock to implementing such a device has some familiar problems from an integration standpoint. Furthermore, new issues that the 3-dimensionality of FinFETs presents create integration challenges for series resistance and overall packing density. In this paper, we outline the critical issues and present practical solutions to these problems from a theoretical standpoint. It is shown that clear pathways do exist in spacer, silicide and epitaxial source/drain with unit process development. Finally, the implementation of necessary techniques such as spacer transfer and compatibility with high k/metal gate integration is examined.
As MOSFET scales below 45nm, conventional SiO2 cannot sustain equivalent oxide thickness (EOT) and leakage current requirements set in the International Technology Roadmap for Semiconductors (ITRS), due to the limitation of physical-thickness scaling, and high tunneling current [1]. Metal gate and high-k dielectric have been extensively studied to overcome the limitation of conventional poly gate and SiO2 technology. Although recent advancements of the technology enable the metal gate and high-k dielectric to be implemented in actual manufacturing, several issues remain associated with integration the new materials in CMOS field-effect transistors (FETs). This paper will introduce various integration schemes for fabricating dual metal gate CMOSFET, and review pros and cons of each approach to propose general integration guide for the desired application.
Multigigahertz flexible electronics are attractive and have broad applications. A gate‐after‐source/drain fabrication process using preselectively doped single‐crystal silicon nanomembranes (SiNM) is an effective approach to realizing high device speed. However, further downscaling this approach has become difficult in lithography alignment. In this full paper, a local alignment scheme in combination with more accurate SiNM transfer measures for minimizing alignment errors is reported. By realizing 1 μm channel alignment for the SiNMs on a soft plastic substrate, thin‐film transistors with a record speed of 12 GHz maximum oscillation frequency are demonstrated. These results indicate the great potential of properly processed SiNMs for high‐performance flexible electronics.
To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs.
Impressive advances in vapor-phase deposition and photolithographic patterning techniques have been fueling the silicon microelectronics revolution over the last 40 years. However, for many interesting classes of materials, including biological materials or functional synthetic polymers, vacuum deposition and photolithography are not the techniques of choice for producing ordered structures and devices. Many of these materials selfassemble into well-ordered microstructures when deposited from solution, and patterning may be more readily achieved by solution-based selective deposition and direct-printing techniques. It is appealing to consider novel ways of manufacturing functional circuits and devices based on techniques that are similar to printing visual information onto paper.
Organic thin-film transistors (OTFTs) are considered indispensable in applications requiring flexibility, large area, low processing temperature, and low cost. Key challenges to be addressed include developing solution-processable gate dielectric materials that form uniform films over large areas and exhibit excellent insulating properties, reducing contact resistance at interfaces between organic semiconductors and electrodes, and optimizing the patterning of organic semiconductors. High-performance pentacene-based OTFTs have been reported with polymeric gate dielectrics and indium tin oxide source/drain electrodes. Using such OTFT backplates, a 15-in. 1024 X 768 pixel full-color active-matrix liquid-crystal display (AMLCD) and a 4.5-in. 192 X64 pixel active-matrix organic light-emitting diode (AMOLED) have been fabricated.
Can we build a flexible and transparent truly high performance computer? High-k/metal gate stack based metal–oxide–semiconductor capacitor devices are monolithically fabricated on industry's most widely used low-cost bulk single-crystalline silicon (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree of freedom to fabricate nanoelectronics devices using state-of-the-art CMOS compatible processes and then to utilize them in an unprecedented way for wide deployment over nearly any kind of shape and architecture surfaces. Electrical characterization shows uncompromising performance of post release devices. Mechanical characterization shows extra-ordinary flexibility (minimum bending radius of 1 cm) making this generic process attractive to extend the horizon of flexible electronics for truly high performance computers.
Schematic and photograph of flexible high-k/metal gate MOSCAPs showing high flexibility and C–V plot showing uncompromised performance.
(© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)
High performance computation with longer battery lifetime is an essential component in our today's digital electronics oriented life. To achieve these goals, field effect transistors based complementary metal oxide semiconductor play the key role. One of the critical requirements of transistor structure and fabrication is efficient contact engineering. To catch up with high performance information processing, transistors are going through continuous scaling process. However, it also imposes new challenges to integrate good contact materials in a small area. This can be counterproductive as smaller area results in higher contact resistance thus reduced performance for the transistor itself. At the same time, discovery of new one or two-dimensional materials like nanowire, nanotube, or atomic crystal structure materials, introduces new set of challenges and opportunities. In this paper, we are reviewing them in a synchronized fashion: fundamentals of contact engineering, evolution into non-planar field effect transistors, opportunities and challenges with one and two-dimensional materials and a new opportunity of contact engineering from device architecture perspective.
In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.
For the first time, we present a simple process to fabricate a thin (>5Lim), mechanically flexible, optically transparent, porous mono-crystalline silicon substrate. Relying only on reactive ion etching steps, we are able to controllably peel off a thin layer of the original substrate. This scheme is cost favorable as it uses a low-cost silicon wafer and furthermore it has the potential for recycling the remaining part of the wafer that otherwise would be lost and wasted during conventional back-grinding process. Due to its porosity, it shows see-through transparency and potential for flexible membrane applications, neural probing and such. Our process can offer flexible, transparent silicon from post high-thermal budget processed device wafer to retain the high performance electronics on flexible substrates.
In today's world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.
This letter presents studies of multiwavelength flexible photodetectors on a plastic substrate by use of printing transferred single-crystal germanium (Ge) membranes. Ge membranes of 250 nm thickness with selectively ion-implantation doped regions were released from a germanium-on-insulator substrate and integrated with a 175-mum-thick polyethylene terephthalate substrate via a dry printing technique. Photodiodes configured in lateral p-i-n configuration using the flexible Ge membranes with an intrinsic region width of 10 mum exhibit an external quantum efficiency that varies from 5% at 411 nm to 42% at 633 nm under -1 V bias condition. These results demonstrate the potential of utilizing single-crystal Ge-membrane photodiodes for imaging applications and as solar cells on objects with arbitrary curvatures and shapes.
Traditional MOSFET scaling served our industry well for more than three decades by providing continuous improvements in transistor performance, power and cost. This was the era of homogeneous scaling where similar materials and device structures were scaled from generation to generation and served a wide range of integrated circuits from memory to logic applications. Traditional scaling ran out of steam in the early 2000s due mainly to the inability to further scale the SiO2 gate oxide and this ushered in the beginning of the heterogeneous era where new materials and new device structures are being continually introduced to deliver the expected benefits of scaling. Going forward, an ever wider range of device types will be needed and the challenge we face is how to identify, develop and manufacture these revolutionary devices, and also how to integrate heterogeneous devices into compelling products.
Electronic systems that use rugged lightweight plastics
potentially offer attractive characteristics (low-cost processing,
mechanical flexibility, large area coverage, etc.) that are not easily
achieved with established silicon technologies. This paper summarizes
work that demonstrates many of these characteristics in a realistic
system: organic active matrix backplane circuits (256 transistors) for
large (≈5 × 5-inch) mechanically flexible sheets of electronic
paper, an emerging type of display. The success of this effort relies
on new or improved processing techniques and materials for plastic
electronics, including methods for (i) rubber stamping
(microcontact printing) high-resolution (≈1 μm) circuits with low
levels of defects and good registration over large areas,
(ii) achieving low leakage with thin dielectrics
deposited onto surfaces with relief, (iii) constructing
high-performance organic transistors with bottom contact geometries,
(iv) encapsulating these transistors, (v)
depositing, in a repeatable way, organic semiconductors with uniform
electrical characteristics over large areas, and (vi)
low-temperature (≈100°C) annealing to increase the on/off ratios
of the transistors and to improve the uniformity of their
characteristics. The sophistication and flexibility of the patterning
procedures, high level of integration on plastic substrates, large area
coverage, and good performance of the transistors are all important
features of this work. We successfully integrate these circuits with
microencapsulated electrophoretic “inks” to form sheets of
electronic paper.
In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ∼16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.
A high-k/metal film stack in a conventional complementary metal oxide semiconductor (CMOS) flow is a key candidate in the semiconductor industry for replacing the existing poly-silicon gate and silicon dioxide (SiO2) gate dielectric to reduce poly depletion and gate leakage. During conventional CMOS integration, the high-k/metal film stack is exposed to a high thermal budget process. In this work, an atomic layer deposition (ALD)-based hafnium oxide (HfO2)/titanium nitride (TiN) film stack (representative of the high-k/metal film stack) was annealed at 1000 °C to determine any change in the physical and electrical properties, such as thickness, surface roughness, density, sheet resistance, refractive index, extinction coefficient, composition, C–V characteristics, work function and etch rate. Although there was no significant electrical impact, some significant physical changes have been observed, which impact the process of integrating high-k/metal film stacks, especially in dual metal gate CMOSs.
Since the 1990s, printable, transparent, and low-voltage transistors have attracted great attention from academia and industry due to the demand for specialized circuitry such as in radio-frequency identification (RFID) tags, medical sensors, and electronically active textiles. Some flexible and portable devices have been available commercially; however, the challenge to convert more conceptual devices into real-life applications is still the materials. This article starts with a brief summary of some examples from silicon electronics, to place the other materials in context, followed by the topics including high-capacitance dielectrics, transparent conductors and semiconductors, and printability of recently developed electronic materials. The recent progress about these topics is reviewed, and discussions of each topic suggest future science and engineering research opportunities.
Research in organic electronics has included advances in materials, devices, and processes. Device architectures, increasingly complex circuitry, reliable fabrication methods, and new semiconductors are enabling the incorporation of organic electronic components in products including OLED displays and flexible electronic paper. Introduction Organic electronics as a field of study has come a long way in the past 10 years. From a literature search covering many of the available R&D materials data-bases, and using the search terms "organic thin film transistor," 12 publications were found for 1993, but well over 300 were found for 2003! If the search is broadened to include organic thin film electronic devices such as memory, photovoltaics, and organic light-emitting di-odes (OLEDs), over 40,000 publications are found for the period of 1998-2003. This implies a very active research subject spanning many areas, including ma-terials development, device design, deposition processes, and modeling. More researchers continue to join the field, with few dropping out each year, even though, as a community, we still await the key applications that may drive organic electronics toward mature industrial persistence. Several companies are in the process of bringing the first commercial organic electronic products to market, with Pioneer's OLED car stereo display, launched in 1998, Motorola's Timeport color OLED cell phone, using Pioneer's display, 1 and Kodak's color OLED digital camera. 2 Although all of these devices are OLED with traditional Si-based backplanes and control electronics, they are a tremendous step toward realizing an organic share of the electronics markets. Additional progress is being made in active matrix backplanes using organic semiconductors by Philips 3 and others, 4 and a smattering of articles implies progress in organic sensors, 5 organic memories, 6 and possibly smart tex-tiles. 7 One aspect we should not neglect as a technolog-ical community is competitionsthe downward march in the cost of silicon-based electronics, 8 the emergence of hybrid organic/inorganic systems, 9 and the concept of systems designed to combine the performance of silicon-based electronics and functionality of organic compo-nents for sensing, flexibility, and actuation. 10 In addi-tion, recent reports decoupling fabrication of high quality, single-crystal Si semiconductors from lower-temperature processing steps present potential alterna-tive approaches toward the realization of low cost electronics. 11 Since all approaches face similar chal-lenges and address similar markets, organic electronic solutions must provide unique advantages such as cost, flexibility, functionality, or appearance. In terms of review, we wish to use this space to highlight the areas of recent progress, including some of our own results, which we believe are essential to the continuing development and successful commercializa-tion of organic electronics. Rather than a comprehensive review, we will present some of the highlights of the last several years with a focus on materials, devices, and manufacturing methods.
This article reviews several classes of inorganic semiconductor materials that can be used to form high-performance thin-film transistors (TFTs) for large area, flexible electronics. Examples ranging from thin films of various forms of silicon to nanoparticles and nanowires of compound semiconductors are presented, with an emphasis on methods of depositing and integrating thin films of these materials into devices. Performance characteristics, including both electrical and mechanical behavior, for isolated transistors as well as circuits with various levels of complexity are reviewed. Collectively, the results suggest that flexible or printable inorganic materials may be attractive for a range of applications not only in flexible but also in large-area electronics, from existing devices such as flat-panel displays to more challenging (in terms of both cost and performance requirements) systems such as large area radiofrequency communication devices, structural health monitors, and conformal X-ray imagers.
This article demonstrates a method for fabricating high quality single-crystal silicon ribbons, platelets and bars with dimensions between ∼100 nm and ∼5 cm from bulk (111) wafers by using phase shift and amplitude photolithographic methods in conjunc- tion with anisotropic chemical etching procedures. This "top-down" approach affords excellent control over the thicknesses, lengths, and widths of these structures and yields almost defect-free, monodisperse elements with well defined doping levels, surface morphologies and crystalline orientations. Dry transfer printing these elements from the source wafers to target sub- strates by use of soft, elastomeric stamps enables high yield integration onto wafers, glass plates, plastic sheets, rubber slabs or other surfaces. As one application example, bottom gate thin-film transistors that use aligned arrays of ribbons as the channel material exhibit good electrical properties, with mobilites as high as ∼200 cm2V-1 s-1 and on/off ratios >104.
A new class of thin, releasable single-crystal silicon semiconductor device is presented that enables integration of high-performance electronics on nearly any type of substrate. Fully formed metal oxide–semiconductor field–effect transistors with thermally grown gate oxides and integrated circuits constructed with them demonstrate the ideas in devices mounted on substrates ranging from flexible sheets of plastic, to plates of glass and pieces of aluminum foil. Systematic study of the electrical properties indicates field-effect mobilities of ≈710 cm2 V−1 s−1, subthreshold slopes of less than 0.2 V decade−1 and minimal hysteresis, all with little to no dependence on the properties of the substrate due to bottom silicon surfaces that are passivated with thermal oxide. The schemes reported here require only interconnect metallization to be performed on the final device substrate, which thereby minimizes the need for any specialized processing technology, with important consequences in large-area electronics for display systems, flexible/stretchable electronics, or other non-wafer-based devices.
Field-effect transistors fabricated from thin and conformable organic single crystals on flexible substrates was analyzed. Rapid growth of single crystals by physical vapor transport enabled them to grow as thin as 150nm and as large as 1cm*1 cm in size. The quality of the single crystals was confirmed from the large birefringence observed under cross polarized light and from the narrow peak with a full width at half maximum of 0.02° corresponding to the Bragg diffraction. The thin crystals for flexible devices, were electrostatically adhered onto bottom-contact source-drain electrodes with a poly-4-vinylphenol (PVP) thin film serving as the dielectric layer. All measurements on single-crystal devices were made in a normal room atmosphere. Flexible transistors based on thin, conformable organic single crystals can give rise to alternative applications, which can have a major impact on consumer electronics.
Copper phthalocyanine (Cu-Pc) single crystals were grown by physical vapor transport and field-effect transistors (FETs) on the surface of these crystals were prepared. These FETs function as p-channel accumulation-mode devices. Charge carrier mobilities of up to 1 cm(2)/V s combined with a low field-effect threshold were obtained. These remarkable FET characteristics, along with the highly stable chemical nature of Cu-Pc, make it an attractive candidate for device applications. (C) 2005 American Institute of Physics.
Within the electronic circuit board industry flexible circuit still cover a small the market share, however, with the fastest growth rate. The technology is increasingly used in automotives and aerospace, in handheld mobile appliances and many medical devices like pace makers or hearing aids [1,2]. Over past years a European consortium of research institutes and industry has explored the future technological potential of flexible printed circuits in the framework of the project SHIFT. One aspect was to investigate the frontiers of flexible circuit fabrication with respect to minimum feasible line width and pitch using different manufacturing methods. Still further beyond today mainstream flex fabrication technologies were the developments to integrate active and passive components into the buildup layers of flex circuits. In this way extremely high integration of electronic systems and highest functional densities can potentially be realized. Techniques and results of these developments will be presented in this paper. Embedded components in order to comply with the thin buildups of flexible circuits should be very thin as well. To this aim components were be mechanically thinned to 20 ptm. A dicing by grinding technique was applied using etched separation grooves on the wafer. Two technologies for embedding of ultra thin components were developed. The first one is thin flip chip assembly on inner layers of the flex and embedding by subsequent lamination of build up layers. The gap between chip and substrate was in the order of a few microns using either low profile solder or anisotropic adhesive.
A new ultrathin chip fabrication and assembly process, consisting of a preprocess module Chipfilm and a postprocess module Pick, Crack, and Place, is presented. In contrast to the established wafer thinning technique, the preprocessed wafer substrates are prepared with extremely narrow buried cavities beneath the chip areas at a well-defined distance from the wafer surface, thus precisely defining the chip thickness a priori . After CMOS integration on those dedicated wafer substrates, chips are detached from the wafer surface by etching trenches at the chip edges into the buried cavities and breaking of residual anchors by mechanical force in the postprocess. The feasibility of the new process is demonstrated through a mixed-signal circuit having 38 000 digital and 2700 analog transistors, showing full functionality within specifications for 20-mum-thin chips even under a bending stress of up to 110 MPa.
This paper discusses thermo-mechanical behavior of plasma-enhanced chemical vapor deposited oxide films during and after post-deposition thermal cycling and annealing. A series of thermal cycling experiments were conducted with various types of oxide and nitride films to elucidate the control mechanism of intrinsic stress generation and to develop engineering solutions for improving reliability of microelectromechanical system fabrication processes. Tensile intrinsic stress generation was observed during thermal cycling and the depletion of hydrogen and the shrinkage of micro voids existing in the oxide films was postulated as a major control mechanism for the stress generation and was modeled by an energy-based formulation. Subsequent experiments indicated that annealing at high temperature could reduce this intrinsic tensile stress. Both stress generation and relaxation were modeled to guide the development of engineering solutions to maintain structural integrity and improve fabrication performance.
We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.
Research in electronic nanomaterials, historically dominated by studies of nanocrystals/fullerenes and nanowires/nanotubes, now incorporates a growing focus on sheets with nanoscale thicknesses, referred to as nanomembranes. Such materials have practical appeal because their two-dimensional geometries facilitate integration into devices, with realistic pathways to manufacturing. Recent advances in synthesis provide access to nanomembranes with extraordinary properties in a variety of configurations, some of which exploit quantum and other size-dependent effects. This progress, together with emerging methods for deterministic assembly, leads to compelling opportunities for research, from basic studies of two-dimensional physics to the development of applications of heterogeneous electronics.
The high natural abundance of silicon, together with its excellent reliability and good efficiency in solar cells, suggest its continued use in production of solar energy, on massive scales, for the foreseeable future. Although organics, nanocrystals, nanowires and other new materials hold significant promise, many opportunities continue to exist for research into unconventional means of exploiting silicon in advanced photovoltaic systems. Here, we describe modules that use large-scale arrays of silicon solar microcells created from bulk wafers and integrated in diverse spatial layouts on foreign substrates by transfer printing. The resulting devices can offer useful features, including high degrees of mechanical flexibility, user-definable transparency and ultrathin-form-factor microconcentrator designs. Detailed studies of the processes for creating and manipulating such microcells, together with theoretical and experimental investigations of the electrical, mechanical and optical characteristics of several types of module that incorporate them, illuminate the key aspects.
This article reviews the properties, fabrication and assembly of inorganic semiconductor materials that can be used as active building blocks to form high-performance transistors and circuits for flexible and bendable large-area electronics. Obtaining high performance on low temperature polymeric substrates represents a technical challenge for macroelectronics. Therefore, the fabrication of high quality inorganic materials in the form of wires, ribbons, membranes, sheets, and bars formed by bottom-up and top-down approaches, and the assembly strategies used to deposit these thin films onto plastic substrates will be emphasized. Substantial progress has been made in creating inorganic semiconducting materials that are stretchable and bendable, and the description of the mechanics of these form factors will be presented, including circuits in three-dimensional layouts. Finally, future directions and promising areas of research will be described.
We demonstrate a manufacturable, large-area separation approach for producing high-performance polycrystalline silicon thin-film transistors on flexible plastic substrates. The approach allows the use of high growth-temperature gate oxides and removes the need for hydrogenation. The process flow starts with the deposition of a nano-structured high surface-to-volume ratio film on a reuseable "mother" substrate. This film functions as a sacrificial release layer and is Si-based for process compatibility. After high-temperature TFT fabrication (up to 1100/spl deg/C) is carried to completion on the sacrificial film coated mother substrate, a thick plastic top layer film is applied, and the sacrificial layer is removed by chemical attack. By using this separation process, the temperature, smoothness, and mechanical limitations posed by plastic substrates are completely circumvented. Both excellent n-channel and p-channel TFTs on plastic have been produced. We report here on p-channel TFTs on separated plastic with a linear field effect (hole) mobility of 174 cm/sup 2//V/spl middot/s, on/off current ratio of >10/sup 8/ at V/sub ds/=-0.1 V, off current of <10/sup -11/ A//spl mu/m-channel-width at V/sub ds/=-0.1 V, sub-V/sub t/ swing of /spl sim/200 mV/dec, and threshold voltage of -1.1 V.
We have investigated the contact resistance of rubrene single-crystal field-effect transistors (FETs) with Nickel electrodes by performing scaling experiments on devices with channel length ranging from 200 nm up to 300 $\mu$m. We find that the contact resistance can be as low as 100 $\Omega$cm with narrowly spread fluctuations. For comparison, we have also performed scaling experiments on similar Gold-contacted devices, and found that the reproducibility of FETs with Nickel electrodes is largely superior. These results indicate that Nickel is a very promising electrode material for the reproducible fabrication of low resistance contacts in organic FETs.