Vladimir Zolotov

IBM · Computer Science, T.J. Watson Center

The paper [1] shows that simple linear classifier can compete with complex deep learning algorithms in text classification applications. Combining bag of words (BoW) and linear classification techniques, fastText [1] attains same or only slightly lower accuracy than deep learning algorithms [2-9] that are orders of magnitude slower. We proved forma...

Timing macro-modeling captures the timing characteristics of a circuit in a compact form for use in a hierarchical timing environment. At the same time, statistical timing provides coverage of the impact from variability sources with the goal of enabling higher chip yield. This paper presents an efficient and accurate method for generation and use...

This paper considers the practical nuances of using current source gate models in an industrial statistical timing analysis environment. Specifically, the memory overhead of a naive implementation combining statistical and current source models to obtain and store gate output waveforms is found to be impractical for large microprocessor designs. A...

The accurate analysis of cross-talk noise in VLSI chIPs must consider the timing when signals can interfere, i.e., the switching windows. It is important to determine the time-alignment of signal switching events that cause maximal cross-talk noise. Moreover, it is necessary to include the effects of process and environmental variations, as they st...

Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least on...

A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a...

Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA...

Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions...

Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table...

Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning sch...

Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean val...

Approaches for binning integrated circuits using timing are provided. A method includes performing a statistical timing analysis of a design. The method also includes identifying bin sub-spaces within a process space of the design. The method further includes determining a frequency limit for each said bin sub-space. The method additionally include...

A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timin...

In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on...

Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis a...

A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of...

At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at least one target metric and the at leas...

Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes per...

In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and construc...

Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing...

Although order statistics have been studied for several decades, most of the results are based on the assumption of independent and identically distributed (i.i.d.) random variables. In the literature, how to compute the mth order statistics of n correlated random variables is still a problem. This article proposes a recursive algorithm based on st...

In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in mult...

Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussi...

A statistical single library that includes on-chip variation (OCV) is created for timing and power analysis of a digital chip design. Initially, library values for all cells of a digital chip design, including ranges for environmental and process parameters, are subject to a statistical model to create statistical timing for the ranges of the param...

A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel...

In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose co...

Statistical static timing analysis (SSTA) is ideal for random variations but is not suitable for environmental variations like Vdd and temperature. SSTA uses statistical approximation, according to which circuit timing is predicted accurately only for highly probable combinations of variational parameters. SSTA is not able to handle accurately dete...

The increasing significance of variability in modern sub-micron manufacturing process has led to the development and use of statistical techniques for chip timing analysis and optimization. Statistical timing involves fundamental operations like statistical-add, sub, max and min to propagate timing information (modeled as random variables with know...

This paper presents a method to compute criticality probabilities of paths in parameterized statistical static timing analysis. We partition the set of all the paths into several groups and formulate the path criticality into a joint probability of inequalities. Before evaluating the joint probability directly, we simplify the inequalities through...

A chip disposition criterion is used to decide whether to accept or discard a chip during chip testing. Its quality directly impacts both yield and product quality loss (PQL). The importance becomes even more significant with the increasingly large process variation. For the first time, this paper rigorously formulates the optimal chip disposition...

In the face of large-scale process variations, statistical timing methodology has advanced significantly over the last few years, and statistical path selection takes advantage of it in at-speed testing. In deterministic path selection, the separation of path selection and test generation is known to require time consuming iteration between the two...

This paper presents a method to compute criticality probabilities of paths in parameterized statistical static timing analysis (SSTA). We partition the set of all the paths into several groups and formulate the path criticality into a joint probability of inequalities. Before evaluating the joint probability directly, we simplify the inequalities t...

Transistor sizing is a classic Computer-Aided Design problem that has received much attention in the literature. Due to the increasing importance of process variations in deep sub-micron circuits, nominal circuit tuning is not sufficient, and the sizing problem warrants revisiting. This paper addresses the sizing problem statistically in which tran...

This paper presents an efficient method to model spatial correlations in the context of parameterized statistical static timing analysis (SSTA). Multiple spatially-correlated process parameters with different spatial properties can be handled by this method simultaneously and efficiently. Experiment results with industrial circuits show that the pr...

In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly higher speed than the target frequency required in the field. The additional performance required on the tester is called test margin . There are many good reasons for margin, inc...

Correct ordering of timing quantities is essential for both timing analysis and design optimization in the presence of process variation, because timing quantities are no longer a deterministic value, but a distribution. This paper proposes a novel metric, called tiered criticalities, which guarantees to provide a unique order for a set of correlat...

As device sizes continue to shrink and circuit complexity continues to grow, power has become the limiting factor in today's processor design. Since the power dissipation is a function of many variables with uncertainty, the most accurate representation of chip power or macro power is a statistical distribution subject to process and workload varia...

Increasingly large process variations make selection of a set of critical paths for at-speed testing essential yet challenging. This paper proposes a novel multilayer process space coverage metric to quantitatively gauge the quality of path selection. To overcome the exponential complexity in computing such a metric, this paper reveals its relation...

Process variation is recognized as a major source of parametric yield loss, which occurs because a fraction of manufactured chips do not satisfy timing or power constraints. On the other hand, both chip performance and chip leakage power depend on supply voltage. This dependence can be used for converting the fraction of too slow or too leaky chips...

Path delay testing is becoming increasingly important for high-performance chip testing in the presence of process variation. To guarantee full process space coverage, the ensemble of critical paths of all chips irrespective of their manufacturing process conditions needs to be tested, as different chips may have different critical paths. Existing...

Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed in contrast to the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process space, and the union of such paths must be tested to obtain good...

As the device size continues to shrink and circuit complexity continues to grow, power has become the limiting factor in today's micro- processor design. Since the power dissipation is a function of many vari- ables with uncertainty, the most accurate representation of chip power or macro power is a statistical distribution subject to process and w...

Existing static timing methodologies apply various techniques to address increasingly larger process variations. The techniques include multi-corner timing, on-chip variation (OCV) derating coefficients, and path-based common path pessimism removal (CPPR) procedures. These techniques, however, destroy the benefits of linear run-time and incremental...

In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly higher speed than the target frequency required in the field. The additional performance required on the tester is called test margin. There are many good reasons for margin inclu...

Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing optimization and timing-driven physical synthesis. Existing work in the literature, however, computes both metrics in a non-incremental manner, i.e., after one or more changes...

Meeting the tight performance specifications mandated by the customer is critical for contract manufactured ASICs. To address this, at speed test has been employed to detect subtle delay failures in manufacturing. However, the increasing process spread in advanced nanometer ASICs poses considerable challenges to predicting hardware performance from...

In ultra-deep sub-micron technologies, modeling waveform shapes correctly is essential for accurate timing and noise analysis. Due to process and environmental variations, there is a need for a variational waveform model that is compact, efficient and accurate. The mode) should capture correlations due to common dependence on process parameters. Th...

Meeting the tight performance specifications mandated by the customer is critical for contract manufactured ASICs. To address this, at speed test has been employed to detect subtle delay failures in manufacturing. However, the increasing process spread in advanced nanometer ASICs poses considerable challenges to predicting hardware performance from...

The increased variability of process parameters makes it important yet challenging to extract the statistical characteristics and spatial correlation of process variation. Recent progress in statistical static-timing analysis also makes the extraction important for modern chip designs. Existing approaches extract either only a deterministic compone...

Increased variability of process parameters and recent prog- ress in statistical static timing analysis make extraction of statistical characteristics of process variation and spatial correlation an important yet challenging problem in mod- ern chip designs. Unfortunately, existing approaches either focus on extraction of only a deterministic compo...

This paper presents a linear system formulation for evaluating full-chip electromigration (EM) risk in general (straight line, tree, and mesh) wiring topologies, considering stress-induced backflow of metal ions. The system of equations is based on stress gradients and mass displacements in wire segments as variables, and is formulated for efficien...

Power-distribution networks of very large-scale integrated (VLSI) chips should be designed carefully to ensure reliable performance. A sound power network requires an adequate number of power-supply input connections (pads and pins). Placing them at the best vantage locations helps to reduce the number of supply connections necessary for obtaining...

Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult since different paths are frequency-limiting in different parts of the multi-dimensional process space. Therefore, it is desirable to have a new diagnostic metric for robu...

This paper presents a novel approach towards the simultaneous Vt-assignment and gate-sizing problem. This inherently discrete problem is formulated as a continuous problem, allowing it to be solved using any of several widely available and highly efficient non-linear optimizers. We prove that, under our formulation, the optimal solution has discret...

In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is difficult to capture the quality of a distribution with a single metric. Hence, we first introduce a new objective function that provides an effective measure for the quality...

Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical static timing analysis (statistical STA) has been proposed as a solution. Unfortunately, the existing approaches either do not consider explicit gate delay dependence on proce...

In this paper we present a new gate delay model for accurate modeling of difficult waveform shapes, such as those resulting from coupling capacitance noise, inductive ringing and resistive shielding. Our modeling approach uses a process of time shifting and time stretching of a set of so-called base-waveforms. These base-waveforms are selected from...

This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exclusively on the optimization algorithms without considering the effects of the variation models and objective functions. This work empirically derives a simple variation m...

As technology scales into the sub-90 nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as statistical distributions during both analysis and optimization. This paper uses incremental, parametric statistical static timing analysis (SSTA) to perform gate sizing with a...

Abstract—High,performance,circuits are facing increasingly severe,signal,integrity problems,due,to crosstalk,noise,and crosstalk noise awareness,has become,an integral part of static timing analysis (STA). Existing crosstalk noise aware,STA methods compute,noise induced,delay uncertainty,on a net by net basis and in a pessimistic way, without consi...

Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that, by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. T...

Even after the successful introduction of Cu ‐based metallization, the electromigration (EM) failure risk has remained one of the most important reliability concerns for most advanced process technologies. Ever increasing operating current densities and the introduction of low‐k materials in the backend process scheme are some of the issues that t...

High-performance digital circuits are facing increasingly severe signal integrity problems due to crosstalk noise and therefore the state-of-the-art static timing analysis (STA) methods consider crosstalk-induced delay variation. Current noise-aware STA methods compute noise-induced delay uncertainty for each net independently and annotate appropri...

With shrinking cycle times, clock skew has become an increasingly difficult and important problem for high performance designs. Traditionally, clock skew has been analyzed using case-files which cannot model intradie-process variations and hence result in a very optimistic skew analysis. In this paper, we present a statistical skew analysis method...

Power delivery networks of VLSI chips require adequate input supply connections to ensure reliable performance. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power supply network, subject to constraints on the voltage drops in the network and maximum currents...

High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, producing the worst-case noise. However, due to logic correlations in the circuit, this worst-case noise may...

Even after the successful introduction of Cu-based metallization, the electromigration (EM) failure risk has remained one of the most important reliability concerns for most advanced process technologies. Ever increasing operating current densities and the introduction of low-k materials in the back-end process scheme are some of the issues that th...

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In this paper, we address the problem of signal pruning in static timing analysis (STA). Traditionally, signals are propagated through the circuit and are pruned, such that only the signal with the latest arrival time at each node is propagated forward. This signal pruning is a key to the linear run time of STA. However, it was previously observed...

Power delivery networks of VLSI chips require adequate input supply :connections to ensure reliable performance. This paper addresses the problem offinding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power supply network, subject to constraints on the uoltage drops in the network and maximum currents...

Progress in semiconductor process technology has made SOI transistors one of the most promising candidates for high performance and low power designs. With smaller diffusion capacitances, SOI transistors switch significantly faster than their traditional bulk MOS counterparts and consume less power per switching. However, design and simulation of S...

Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for inter- and intra-die process variations and their spatial correlations. Since statistical timing analysis has an exponential run time complexity, we propose a method whereby...

The impact of power supply integrity on a design has become a critical issue, not only for functional verification, but also for performance verification. Traditional analysis has typically applied a worst case voltage drop at all points along a circuit path which leads to a very conservative analysis. We also show that in certain cases, the tradit...

Signal integrity has become a critical issue in the design of high-performance circuits. Noise on a net arises both through propagation of noise from previous stages through the driver gate of the net and through injection of new noise through coupling capacitance with neighboring nets. Typically, propagated noise and injected noise are added linea...

Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. Th...

With the increase in current densities, electromigration has become a critical concern in high-performance designs. Typically, electromigration has involved the process of time-domain simulation of drivers and interconnect to obtain average, RMS, and peak current values for each wire segment. However, this approach cannot be applied to large proble...

The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper...

Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter- and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probabilit...

With the increase in current densities, electromigration has become a critical concern in high-performance designs. Typically, electromigration has involved the process of time-domain simulation of drivers and interconnect to obtain average, root mean square (r.m.s.), and peak current values for each wire segment. However, this approach cannot be a...

In this paper, a precorrected-fast-Fourier-transform (FFT) approach for fast and highly accurate simulation of circuits with on-chip inductance is proposed. This work is motivated by the fact that circuit analysis and optimization methods based on the partial element equivalent circuit model require the solution of a subproblem in which a dense ind...

The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit. In this paper...

The growing impact of within-die process variation has created the need for statistical timing analysis, where gate delays are modeled as random variables. Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to arrival time dependencies created by reconverging paths in the circuit. In t...

A compact model for RLC interconnect lines, in the form of a two-path hybrid ladder, is proposed for on-chip interconnect timing and noise analysis. The model parameters are synthesized through constrained nonlinear optimization to directly match the circuit response characteristics over a range of transition times and loads, both at the driving po...

With shrinking cycle times, clock skew has become an increasingly difficult and important problem for high performance designs. Traditionally, clock skew has been analyzed using case-files which cannot model intra-die process variations and hence result in a very optimistic skew analysis. In this paper, we present a statistical skew analysis method...

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based m...

Noise analysis has become a critical concern in advanced chip designs. Traditional methods suffer from two common issues. First, noise that is propagated through the driver of a net is combined with noise injected by capacitively coupled aggressor nets using linear summation. Since this ignores the non-linear behavior of the driver gate the noise t...

Static timing analysis has traditionally used the PERT method for identifying the critical path of a circuit. The authors show in this paper that due to the influence of the transition time of a signal on the subsequent path delay, the traditional timing analysis approach can report an optimistic circuit delay and may identify the wrong critical pa...

Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes the assumption that all aggressing nets can simultaneously switch in the same direction. This creates a worst-case noise pulse on the victim net that often leads to false noise violations. In this article we present a new approach tha...

Noise estimation and avoidance are becoming critical, `must have' capabilities in today's high performance IC design. An accurate yet efficient crosstalk noise model which contains as many driver/interconnect parameters as possible, is neccesary for any sensitivity based noise avoidance approach. In this paper, we present a complete analytical cros...

Signal integrity has become a critical issue in the design of high-performance circuits. Noise on a net arises both through propagation of noise from previous stages through the driver gate of the net and through injection of new noise through coupling capacitance with neighboring nets. Typically, propagated noise and injected noise are added linea...

High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, thereby producing the worst-case noise on a net. However, due to the logic correlations in the circuit, this...

Noise estimation and avoidance are becoming critical, 'must have' capabilities in today's high performance IC design. An accurate yet efficient crosstalk noise model which contains as many driver/interconnect parameters as possible, is necessary for any sensitivity based noise avoidance approach. In this paper, we present a complete analytical cros...

Abstract The growing impact of within - die process variation has created the need for statistical timing analysis, where gate delays are mod - eled as random variables Statistical timing analysis has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by reconverging paths in the circuit I...

On-chip power distribution networks are resistive in nature and hence create large variations in the voltage levels across the chip. These variations have significant impact on the delays of global signals, such as the clock, which span the entire chip. A clock network that is balanced without considering delay variations induced by power supply va...

The simulation of on-chip inductance using PEEC-based circuit analysis methods often requires the solution of a subproblem where an extracted inductance matrix must be multiplied by a current vector, an operation with a high computational cost. This paper presents a highly accurate technique, based on a precorrected-FFT approach, that speeds up thi...

Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter-and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probability...