Apangshu Das

National Institute of Technology, Agartala | NITA · Department of Electronics and Communication Engineering

The integration of a large number of transistors and device scaling results in the development of high-power density within Very Large-Scale Integrated (VLSI) circuits. Power density is directly proportional to chip temperature and grows exponentially as package density increases. As a result, considering temperature impacts at all levels of the VL...

In this work, a multi‐objective algorithm based on nondominated sorting genetic algorithm‐II (NSGA‐II) for thermal‐aware realization of a combinational logic network has been implemented. Input variable ordering of shared reduced ordered binary decision diagram (SROBDD) is done using NSGA‐II such that resulting combinational circuit generates low h...

Proposed work presents an OR-XNOR-based thermal-aware synthesis approach to reduce peak temperature by eliminating local hotspots within a densely packed integrated circuit. Tremendous increase in package density at sub-nanometer technology leads to high power-density that generates high temperature and creates hotspots. A nonexhaustive meta-heuris...

Proposed work addresses the existing thermal problem of OR-XNOR based circuit by introducing design time thermal management technique at the logic level. The approach is used to reduce the peak temperature by eliminating local hotspots. In proposed thermal-aware synthesis, non-dominated sorting genetic algorithm-II (NSGA-II) based meta-heuristic se...

At sub-nanometre technology, temperature is one of the important design parameters to be taken care of during the target implementation for the circuit for its long term and reliable operation. High device package density leads to high power density that generates high temperatures. The temperature of a chip is directly proportional to the power de...

In this paper, an attempt is made to reduce the rise in circuit temperature by optimising power-density during logic synthesis level. Reduced ordered binary decision diagram (ROBDD) being canonical in nature makes a suitable choice of logic realisation in this work. ROBDD is used here not only to reduce area (node) but also the possibility of reduc...

Modern Integrated circuits (ICs) suffer from excessive power and temperature issues because of embedding a large number of applications on small silicon real estate. Low power technique is introduced to reduce the power. With the reduction of power, area of circuit increases and vice versa. It shows a trade-off nature between them. Increase of area...

Background: Output polarity of the sub-function is generally considered to reduce the area and power of a circuit at two-level realization. Along with area and power, the power-density is also one of the significant parameter which needs to consider, because power-density directly converges to circuit temperature. More than 50% of the modern day in...

The increased number of complex functional units exerts high power-density within a very-large-scale integration (VLSI) chip which results in overheating. Power-densities directly converge into temperature which reduces the yield of the circuit. An adverse effect of power-density reduction is the increase in area. So, there is a trade-off between a...

With the advent of incorporating increased number of complex logic blocks within a VLSI chip, power-density is increasing. Power-density directly converges into temperature which reduces the yield of the circuit. Adverse affect of power-density reduction is increase in area. So, there is a trade-off between area and power-density. Previous works ha...

Intensive scaling and large number of logic blocks embedded within a VLSI chip results increased power-densities. Power-density directly converging into temperature which reduces the yield of the circuit. Adverse affect of power-density reduction is increase in area So, there is a trade-offs between area and power-density. Previous works has been d...

Due to trade-offs between the VLSI circuit parameters, chip suffers from reliability issues. It needs to be optimizing for better performance. Such problems are defined as NP-hard problems. In this paper a heuristic has been developed using genetic algorithm for solving the floorplan problem. The proposed algorithm is an improved floorplan algorith...