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Trial division circuit components
Source publication
Trial division is the most straightforward way to determine the prime fac- tors of a number, but the execution time is exponentially dependent on the size of the number. We have developed a novel hardware architecture which performs trial division of large dividends by small prime divisors at a much higher throughput than previously reported archit...
Context in source publication
Context 1
... circuit was divided into the following major components: a highly pipelined array divider, a multi-cycle sequential divider, and a ROM to store the prime divisors, along with a control unit and registers to control dataflow, as shown in Figure 2. The circuit was designed to accept a large input value, typically 512 bits, so we used a shift register to store the number that was be- ing processed as the input. ...
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Citations
Cofactorization, checking smoothness of mid-size integers, is usually adopted in General Number Field Sieve. In this paper, we present a specific cofactorization hardware implementation, which performs smoothness test for mid-size integers at a much higher throughput than previous works. The proposed design, based on highly-parallel and pipeline structure, can analysis a 125-bit integer and determine in less than 130 clock cycles whether it could factor completely over a factor base. Besides, the algorithm used in architecture can be performed by multiplication, addition and some logical operations only, which brings simple circuit structure, low hardware cost and short time delay. Moreover, the comparison results show that our architecture achieves a speedup of one or two orders of magnitude over implementation based on Elliptic Curve Method. Our design therefore can be a good solution to cofactorization.
Due to the widespread use of public key cryptosystems whose security depends on the presumed difficulty of the factorization problem, the algorithms for finding the prime factors of large composite numbers are becoming extremely important. In recent years the limits of the best integer factorization algorithms have been extended greatly, due in part to Moore's law and in part to algorithmic improvements. Furthermore, new silicon devices, such as FPGAs, give us the advantage of custom hardware architectures for minimizing execution time for such difficult computations. This paper demonstrates a very efficient FPGA-based design executing Pollard's (rho - 1) factorization algorithm. The proposed device offers a speedup from 20 to 231 when compared to the software implementation of the same algorithm in a state-of-the-art CPU.
