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Pseudorandom numbers (PRN) are used in various cryptographic applications, such as cryptographic protocols and stream ciphers. The most efficient hardware method used to generate PRNs is to use a Linear Feedback Shift Register (LFSR) structure, which is generally composed of a Shift Register (SR) and an XOR gate. The most important factors in desig...
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... CA find many different practical engineering applications (watermark and image encryption, complex logic puzzles, simulation of complex physical phenomena: solitons, fractals, and chaos; modeling and simulation of population density scenarios and the behavior of crowds, etc.) [32][33][34][35][36], including the use of CA concepts in solving the DCP, as demonstrated in this paper. ...
This paper describes a solution for the image density classification problem (DCP) using an entirely distributed system with only local processing of information named cellular automata (CA). The proposed solution uses two cellular automata’s features, density conserving and translation of the information stored in the cellular automata’s cells through the lattice, in order to obtain the solution for the density classification problem. The motivation for choosing a bio-inspired technique based on CA for solving the DCP is to investigate the principles of self-organizing decentralized computation and to assess the capabilities of CA to achieve such computation, which is applicable to many real-world decentralized problems that require a decision to be taken by majority voting, such as multi-agent holonic systems, collaborative robots, drones’ fleet, image analysis, traffic optimization, forming and then separating clusters with different values. The entire application is coded using the C# programming language, and the obtained results and comparisons between different cellular automata configurations are also discussed in this research.
A strong need for high-speed and low-power consumption devices seems inevitable due to the high speed of technological advancement in the field of microelectronics. Designers are highly interested in designing and making nanoscale devices. The Quantum Cellular Automaton (QCA) is known as one of these technologies, which makes it feasible to implement digital circuits with a high operating speed. In this paper a 4-bits counter, a 3-bits bidirectional counter, a 4-bits counter with a reset terminal, and a 4-bit counter with both set and reset terminals are designed using the proposed D-latch to demonstrate that these circuits function accurately in more complex circuits. According to the results, the area was respectively reduced by 8.33 and 15.38% with a 4.76% reduction in the delay rate in the proposed 4-bits counter and 3-bits bidirectional counter compared to the best previous designs. All the designs and simulation results are being done in the QCAPro and QCADesigner software.
The current research goal is set to provide efficient design and a practical arrangement of the multiplexer, D-latch, and shift register in the quantum-dot cellular automata (QCA) technology. In the proposed multiplexer, including 14 cells, an area of 0.01 \({\mu {\text{m}}}^{2}\), a 0.5 clock cycle delay, and an energy consumption of 17.31 \({\text{meV}}\), the number of cells and energy consumption rates are reduced by 6.66 and 7.53% compared to the previous designs. Also, a D-latch is designed in this paper using the proposed multiplexer, which has been improved dramatically compared to the previously proposed methods. The proposed D-latch with 24 cells, an area of 0.02 \({\mu {\text{m}}}^{2}\), a 0.5 clock cycle delay, and energy consumption of 26.18 \({\text{meV}}\) reduced the delay and energy consumption rates, respectively, by 50 and 16.14% in comparison with the best previous designs. The reset and set terminals are also added to the proposed D-latch. The designed D-latches were used in a 4-bit shift register to demonstrate their accurate functioning in more complicated circuits. Accordingly, a 14.28% delay rate reduction resulted. Also, the proposed shift register contains 149 cells, an area of 0.11 \({\mu {\text{m}}}^{2}\), a 1.5 clock cycle delay, and an energy consumption of 156.05 \({\text{meV}}\). The simulation of the proposed circuits was made by QCADesigner and QCAPro tools.
