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Electrical model of a DRAM with a defect connecting three memory cells together.

Electrical model of a DRAM with a defect connecting three memory cells together.

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Conference Paper
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As the complexity of memory faulty behavior increases, it is becoming more difficult to precisely identify the faults the memory exhibits. Knowledge of the precise set of faults is essential for designing an optimal set of memory tests with low test time and high fault coverage. This paper presents an automatic method to analyze the observed faulty...

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... 4 This example is based on the faulty behav- ior resulting from a defect injected into a DRAM design. The defect is modeled at the electrical level by two re- sistors from the victim to two aggressors, as shown in Figure 2. All three cells, the victim and the two aggres- sors, are located on the true bit line (BT). ...

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Recently, a framework describing the space of all fault models has been established. Subsequently, it has been shown that many new faults of that space do exist. Gradually, The number and complexity of observed memory fault models has been gradually increasing. As a result, it has become increasingly difficult to identify the precise functional fault models that a memory suffers from. This paper shows that there are two types of possible imprecision in describing faults: under specification, which leads to tests with insufficient fault coverage, and over specification, which leads to time-inefficient tests. A general method is presented to analyze faulty memory behavior based on electrical simulation and map it precisely onto the corresponding fault models, which makes it possible to generate time-optimal tests with optimal fault coverage.