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Cross-sectional QED at the middle of a GAA 15 nm wide Si NW JL MOSFET for three operation regimes (oxide is not shown; channel doping: 1 × 10 19 cm − 3 ). (Left) Subthreshold ( V GS = − 0.200 V ) . (Center) Above threshold ( V GS = 0.100 V ) . (Right) Strong accumulation ( V GS = 1.500 V ) .
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In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate
and deplete more electrons than the flat sides or the channel center, when above (local accumulation) a...
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Fig. 3 shows the second derivative of the total electron density per unit length ( d 2 N /dV 2 ) versus V for the GAA 15 nm wide Si NW MOSFETs for three channel doping concentrations, considering classical and quantum effects. The results reported in Table I show that the quantization is upshifting both the threshold and the flat-band voltages, due to the higher quantized subband energies [9], [23], [24]. Note that, even for the heavily doped structure and on the contrary to the IM devices [19], there is no hump effect below the gate voltage corresponding to the main peak in the d 2 N t /dV GS 2 versus V GS curve, thus representing a unique threshold voltage in the system. The hump appearing above the threshold voltage of the heavily doped device in the classical simulation is due to the nonlinear operation of bulk regime between the threshold and the flat-band voltages as well as creation of accumulation conduction paths in the channel, reported before for the planar AM devices [2]. IV. L OCAL E LECTRON D ENSITY D ISTRIBUTION A CROSS THE C HANNEL F ROM S UBTHRESHOLD TO S TRONG A CCUMULATION Figs. 4 and 5 show the quantum electron density (QED) and classical electron density (CED) in the cross-section of a GAA 15 nm wide Si NW JL MOSFET (channel doping: 1 × 10 19 cm − 3 ) in subthreshold, above threshold, and strong accumulation regimes. According to the figures, the majority of electrons are accommodated in the corner regions only in strong accumulation. To study better the bias-dependent charge distribution mechanism in the channel cross-section, local QED and CED profiles as functions of gate voltage are plotted along y = 0 (see e.g., Fig. 4) in Fig. 6. This provides a wide range of information on the local electron density variation in the corner, side, and volume. The maximum and minimum of the local CEDs in accumulation and depletion regimes are both occurring on the Si NW–dielectric interface, respectively. Therefore, a simple way to study the effect of corners on the local electron density variation can be the local CED corner to side ratio at different channel doping and gate voltages. Note that, due to the quantization effects, the peak of QED occurs inside the channel volume. Fig. 6 inset shows this classical ratio as a function of V GS – V FB . According to this figure (as well as from the local CEDs at different channel doping levels in Fig. 7), corners accumulate more electrons in comparison to the side in accumulation regime ( > V FB ) , while they deplete also further below the flat-band voltage. The different corner effects and device behavior in the IM and the AM/JL MOSFETs come from a distinct conduction mechanism, surface versus volume conduction in different regimes, as well as conduction of minority versus majority carriers. Analyzing the effect of corners on the carrier density distribution in the channel cross-section is not simple. According to the simulations, it strongly depends on the channel geometry, doping level, and dielectric thickness (see e.g., [19], [25]–[27]). There is no clear geometrical definition of the corner region, while the analysis becomes even more complex including quantization. The surface conduction by minority carriers is the only conduction mechanism in the IM devices, while the AM/JL MOSFETs exhibit surface conduction above V FB and volume conduction below V FB , both involving majority carriers. Due to having a maximized surface to volume ratio in the corner region in comparison to the side region, the surface conduction mechanisms (above V FB for the AM/JL, all operation regimes for the IM devices) should provide a higher local mobile charge density in the corner region (local volume inversion or local volume accumulation in the IM and the AM/JL devices, respectively). On the other hand, reduction of the local effective channel doping in the corners because of side gates and the effective body thickness reduction in the corners were suggested previously to describe the local threshold voltage downshift and the local volume inversion in the corners of the IM devices in subthreshold regime as well [21]. Due to having a smaller effective channel body thickness in the corner region in comparison to the side, the volume conduction mechanism in the corner region is expected to be minimized with respect to the side region below the flat-band voltage, since the volume of corner is negligible. Therefore, no subthreshold conduction path in the corner regions of the AM/JL MOSFETs is expected to emerge from I D – V GS characteristics, as already observed in Fig. 3 (no hump below the main peak of the d 2 N /dV 2 versus V curves). To assess corner effects on the global device characteristics, the normalized total accumulation electron density per unit length in the entire channel cross-section is defined ...
Citations
... Previous work focused on the planar GaAs x Sb 1−x /In y Ga 1−y As heterojunction TFETs. [13,14] Research on the performance of the SG mixed-As/Sb heterojunction TFET with cylindrical cross-section, which can eliminate the corner effect, [15] has not been found so far in the literature. ...
A III?V heterojunction tunneling field-effect transistor (TFET) can enhance the on-state current effectively, and GaAsx Sb1?x /Iny Ga1?y As heterojunction exhibits better performance with the adjustable band alignment by modulating the alloy composition. In this paper, the performance of the cylindrical surrounding-gate GaAsx Sb1?x /Iny Ga1?y As heterojunction TFET with gate?drain underlap is investigated by numerical simulation. We validate that reducing drain doping concentration and increasing gate?drain underlap could be effective ways to reduce the off-state current and subthreshold swing (SS), while increasing source doping concentration and adjusting the composition of GaAsx Sb1?x /Iny Ga1?y As can improve the on-state current. In addition, the resonant TFET based on GaAsx Sb1?x /Iny Ga1?y As is also studied, and the result shows that the minimum and average of SS reach 11 mV/decade and 20 mV/decade for five decades of drain current, respectively, and is much superior to the conventional TFET.
... [6][7][8][9][10][11][12]). Precise carrier mobility extraction in such multi-gate devices especially with a deeply scaled cross-section is not simple due to the non-uniform electron density and the normal electric field variation in the channel mainly due to the corners (see e.g. [13][14][15]). Two major mobility extraction methods were reported previously: Y-function (I D / ffiffiffiffiffiffi g m p ) [16] and split-CV [17]. ...
... We intentionally mainly focus on strong accumulation regime, having a channel doping level of 1 Â 10 19 cm À3 and different channel cross-section dimensions (5-20 nm nanowire width) at V DS = 100 mV (T = 300 K), including the impact of corners. A channel length of 100 nm (>6 times longer than the natural length [15,20] of the widest nanowire) was chosen to provide a clear short channel free mobility extraction assessment in such architectures. Such studies can be extended further to the shorter channel junctionless devices e.g. ...
... TCAD Sentaurus Device (G.2012-06) was used for quasistationary numerical simulation of GAA Si nanowire nMOSFETs, adapting the 3D TCAD Si nanowire simulation platform that we developed earlier in [15] with the current geometrical dimensions (see Fig. 1-top). For all the nanowire widths (5, 10 and 20 nm), the gate length and SiO 2 gate oxide thickness are 100 and 2 nm, respectively. ...
In this paper, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm. 1 × 1019 cm−3 n-type channel doping, 5–20 nm Si nanowire width together with 2 nm SiO2 gate oxide thickness were used in the quasistationary TCAD device simulations of 100 nm long channel devices (VDS = 100 mV, T = 300 K). All the extensive studies were performed in strong accumulation regime, as a first step, using a constant electron mobility model (100 cm2/V s). The effects of non-uniform electron density due to corners and quantum confinement effects are investigated. Suppressing the bias-dependency of various key MOSFET parameters e.g. series resistance, by contact engineering, and the product of channel width and gate-channel capacitance, CWeff, by rounding the sharp corners, to improve the accuracy of mobility extraction in strong accumulation is addressed in details. A significant bias-dependent series resistance modulation is reported in GAA Si nanowire junctionless nMOSFETs, leading to a significant electron mobility extraction inaccuracy of ~50% in strong accumulation regime.
This paper examines the reliability issue of single metal gate (SMG) and dual metal gate (DMG) junctionless accumulation mode surrounding gate (JAM-SG) MOSFET. The impact of trap charges has also been considered along with the variation of different temperature range (200–400 K). In addition, the analog/RF performance of SMG-JAM-SG and DMG-JAM-SG MOSFET evaluated in terms of the fundamental figure of merits such as ON-state current (ION), OFF-state current (IOFF), ION/IOFF, transconductance (gm), cutoff frequency (fT), current gain, transducer power gain, VIP2, VIP3, IIP3, IMD3 and higher order transconductance parameters gm1, gm2 and gm3. An extensive comparative analysis in terms of overall performance degradation is accomplished between DMG-JAM-SG and SMG-JAM-SG MOSFET using numerical simulation tool (ATLAS 3-D). The temperature sensitivity of device has also been explained with the effect of trap charges. The results reveal that DMG-JAM-SG MOSFET has better immunity contrary to impact of interface trap charges and exhibit high linearity performance, as compared to SMG-JAM-SG MOSFET and DMG-JAM-SG MOSFET is appropriate for highly efficient RFICs and wireless device applications.
This chapter discusses the device architectures, which have the potential to enable the junctionless field‐effect transistors (JLFETs) to replace the conventional metal‐oxide‐semiconductor field‐effect transistors (MOSFETs). JLFETs with an additional source/drain implantation are known as junctionless accumulation‐mode field‐effect transistors (JAMFETs). Although the JAMFETs offer a significantly high drain current as compared to the JLFETs, they are more susceptible to the short‐channel effects as compared to the JLFETs due to a reduction in the effective channel length owing to the high‐low junction. The bulk planar JLFET (BPJLFET) consists of a uniformly doped active device layer, which does not have any source/channel or channel/drain metallurgical junction. To achieve volume depletion in a JLFET, an ultrathin active silicon film is required and the film doping should be high enough to achieve a decent source/drain series resistance while realizing efficient volume depletion.
An analytical model for Junctionless Accumulation Mode Surrounding Gate (JLAMSG) MOSFET is developed using superposition technique. The model incorporates source/drain and channel depletion for an accurate analysis. The device parameter dependent electrostatic center potential, drain current (IDS) and subthreshold slope (SS) have been evaluated. The numerical simulation results using ATLAS-3D device simulator are in good agreement with the results obtained from the developed analytical model. A comparative assessment between Junctionless (JL) and Junctionless Accumulation Mode (JLAM) Surrounding Gate (SG) devices for analog/RF performance is also carried out. The superiority of JLAMSG MOSFET over Junctionless Surrounding Gate (JLSG) is discussed for Analog and RF application.
This paper presents physics based analytical model for center potential, electric field and subthreshold drain current of Junctionless Accumulation Mode Cylindrical Surrounding Gate MOSFET (JAM-CSG). The expressions are derived from Poisson's equation in cylindrical co-ordinate system based on parabolic potential approximation (PPA). The influence of technology parameter variations such as gate length, silicon pillar diameter and oxide thickness on electrical characteristics is studied in detail. Developed analytical model results are validated through the good agreement with simulated data obtained from ATLAS 3D simulator. Copyright
Dataset to the IEEE DRC 2015 paper, Ohio State University, Columbus, USA
The precision of carrier mobility extraction in a JAM device strongly depends on the doping level in the S/D extensions. The bias-dependency of several key MOSFET parameters (e.g. gate-channel capacitance, effective channel width and series resistance) together with the non-linear mobile charge accumulation in the channel due to the corners in the GAA Si nanowires, with cross-section down to 5 nm, and their impacts on the carrier mobility extraction are addressed in details for the first time.
Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising candidates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of such architectures due to higher electrostatic control of the channel. On the other hand, Si nanowires show excellent mechanical properties e.g. yield and fracture strengths of 10±2% and 30±1% in comparison to 3.7% and 4.0% for bulk Si, respectively, a strong motivation to be used as exclusive platforms for innovative nano-electronic applications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3D suspended channels or local band-gap modulation using >4 GPa uniaxial tensile stress in suspended Si channels to enhance the band-to-band tunneling current in multi-gate Tunnel-FETs, all without plastic deformation and therefore, no carrier mobility degradation in deeply scaled channels.
In this thesis and as a first step, a precise built-in stress analysis during local thermal oxidation of suspended Si NWs in the presence of a Si3N4 tensile hard mask was done. Accumulation of up to 2.6 GPa uniaxial tensile stress in the buckled NWs is reported. The contribution of hard mask/spacer engineering on the stress level and the NW formation was studied and buckled self-aligned dual NW MOSFETs on bulk Si with two sub-100 nm cross-sectional Si cores including ~0.8 uniaxial tensile stress are reported. Micro-Raman spectroscopy was widely used in this thesis to measure stress in the buckled NWs on both bulk and SOI substrates. A process flow was designed to make dense array of GAA sub-5 nm cross-sectional Si NWs using a SOI substrate including a high level of stress. The NW stress level can be engineered simply using e.g. metal-gate thin film stress suitable for both NMOS and PMOS devices. Lately, highly and heavily doped architectures with a single-type doping profile from source to drain, called junctionless and accumulation-mode devices, are proposed to significantly simplify the fabrication process, address a few technical limitations e.g. ultra-abrupt junctions in order to fabricate shorter channel length devices. Therefore, in this process flow, a highly doped accumulation-mode was targeted as the operation mechanism.
Finally, extensive TCAD device simulation was done on GAA Si NW JL MOSFETs to study the corner effects on the device characteristics, from subthreshold to strong accumulation, report the concept of local volume accumulation/depletion, quantum flat-band voltage, significant bias-dependent series resistance in junctionless MOSFETs and finally, support the experimental data to extract precisely the carrier mobility in sub-5 nm Si NW MOSFETs.
