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A 10-bit 120 kS/s successive-approximation-register analog-to-digital converter (SAR ADC) is realized for implantable multichannel neural recording system. In order to reduce power consumption and area occupation, an improved energy-efficient VCM-based switching scheme is proposed. Different from the monotonic switching scheme, the switching proced...
Citations
... The comparison of the proposed ADC to other advanced SAR ADCs employs the figure of merit (FOM). According to [31], FOM is defined as follows: (9) where Fs is the sampling frequency, and ENOB is the effective number of bits of the Nyquist input, while Power is the total power consumption of the SAR ADC. The proposed SAR ADC achieves an FOM of 2.87 fJ/conv.-step, ...
... The comparison of the proposed ADC to other advanced SAR ADCs employs the figure of merit (FOM). According to [31], FOM is defined as follows: ...
A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s.
... The comparison of the proposed ADC to other advanced SAR ADCs employs the figure of merit (FOM). According to [32], FOM is defined as follows: ...
... The comparison of the proposed ADC to other advanced SAR ADCs employs the figure of merit (FOM). According to [32], FOM is defined as follows: FOM = Power 2 ENOB × F s (5) where F s is the sampling frequency, and ENOB is the effective number of bits of the Nyquist input, while Power is the total power consumption of the SAR ADC. The proposed SAR ADC achieves an FOM of 22.2 fJ/conv.-step, ...
A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of Vcm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low sampling error sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrate that the ADC achieves a 61.77 dB SNDR and a 78.06 dB SFDR and consumes 4.45 μW of power in a 180 nm process with a 1 V power supply, a full-swing input signal frequency of 93.33 kHz, and a sampling rate of 200 kS/s.
... Recently, with the rise of Internet-of-things (IOT) application, there is a trend to design low-power high-resolution ADC for the battery-powered IOT sensors [1,2,10,22,25]. Fully dynamic operation is preferred to achieve high-power efficiency. SAR ADC is a popular architecture for the design of low-power high-resolution ADC. ...
A low-power common-mode detector (LPCMD) with process, supply voltage and temperature (PVT)-compensation technique for the dynamic amplifier in delta-sigma modulator (DSM) is proposed. By adopting the varying supply voltages to compensate the variation of the transistors’ threshold voltage, the proposed LPCMD improves the robustness of the dynamic amplifier (DA). Additionally, the auxiliary circuit providing the varying supply voltages is realized by the low-power regulator, which has the advantage of low power and low complexity. To demonstrate the feasibility of the proposed LPCMD with the PVT-compensation technique, a second-order 2-bit quantization-based DSM is designed in 180 nm CMOS technology and the postlayout simulation is performed. The DSM achieves a signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic range (SFDR) of 93 dB and 95 dB at the sampling frequency of 204.8 kHz, respectively, with the power consumption of 11 µW, leading to a 171.6 dB SNDR-based Schreier figure-of-merit (FoMSNDR). Furthermore, the SNDR degradation of the DSM under all process corner and temperature from − 40 to 125 ℃ is less than 3 dB. The postlayout simulation result of the DSM verifies the feasibility and effectiveness of the proposed LPCMD and PVT-compensation technique.
... In recent years, successive-approximation register (SAR) analogue-to-digital converters (ADCs) have been preferred for biosensor applications [1][2][3][4][5]. SAR ADC is based on a successive approximation algorithm, which is suitable for designing resolution-reconfigurable SAR ADCs [6][7][8]. ...
... The comparator compares VP (2) with VN(2) and obtains D2. The comparator compares the sampling signals (V ip and V in ) and obtains D 1 . ...
A DAC switching scheme that combines energy efficiency and resolution reconfigurability is proposed. Compared with the conventional switching scheme, the proposed scheme achieves 93.8%, 96.1%, and 97.3% switching energy saving in 8-bit, 9-bit, and 10-bit modes, respectively. Based on the proposed switching scheme, an 8–10-bit resolution-reconfigurable SAR ADC for biosensor applications is designed. The ADC consists of resolution-reconfigurable binary-weighted capacitive DAC, a two-stage full dynamic comparator, sampling switch, and the resolution-control SAR logic. Simulated in 180 nm CMOS process and 100 kS/s sampling rate, the ADC achieves the 46.80/53.89/60.14 dB signal-to-noise and distortion ratio (SNDR), the 55.22/62.51/73.09 dB spurious-free dynamic range (SFDR) and the 0.81/0.91/1.01 μW power consumption in 8/9/10-bit mode, respectively.
... Furthermore, the closed-loop charge recycling method presented in [7] realizes 100% switching energy reduction at the expense of the capacitor area. Tong [16] saves 75% area overhead with only √ 2 × INL performance enhancement. Besides, the switching energy reduction in [4] and [11] is also attenuated by 0.56 and 0.89% due to the parasitic capacitance, respectively. ...
... The SAR ADC with the proposed switching scheme in Fig. 1 consists of the sampleand-hold circuits (S p1 /S n1 and S p0 /S n0 ), the connection switches (S p2 and S n2 ), the capacitive DAC array (C pm , C pl , C nm , C nl ), a comparator, and a dynamic SAR logic. For an N-bit conventional SAR ADC, 2 N flip-flops are required at least in SAR logic [16]. In this paper, the dynamic SAR control logic in [26] is adopted to reduce power and complexity. ...
... In this paper, the dynamic SAR control logic in [26] is adopted to reduce power and complexity. The MSB capacitor 128C is split into 8 capacitors (64, 32, 16,8,4, 2C, C, C), which have the identical binary form to the LSB capacitors. C pl and C nl are the LSB capacitors, and C pm and C nm are the MSB splitting capacitors. ...
A high energy efficiency and linearity switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converter (ADC). With the tri-level switching scheme, the capacitor area is reduced by 75% compared with the conventional switching scheme. In addition, the proposed switching scheme also combines the most significant bit (MSB) splitting method and the monotonic switching scheme for linearity and energy efficiency improvement. Furthermore, by inserting a connection switch between the MSB splitting capacitors and the least significant bit (LSB) capacitors, the reset energy can be avoided. The MATLAB simulation results show that compared to the monotonic switching scheme, the proposed switching scheme achieves a 93.29% reduction in average switching energy and 50% capacitor area saving without the reset energy when the parasitic capacitance is taken into consideration. Meanwhile, the linearity is enhanced by √2 × from the Monte Carlo simulation. The post-simulation results indicate that a 10-bit SAR ADC with the proposed switching scheme can achieve a signal-to-noise distortion ratio (SNDR) of 57.81 dB and a spurious-free dynamic range (SFDR) of 68.63 dB at the sampling rate of 1 MS/s in a 180-nm CMOS process. The SAR ADC consumes 15.25 μW power at a 1 V supply, resulting in a figure of merit (FoM) of 24.03 fJ/conv.-step. The active area of this ADC is only 0.057 mm².
... The energy reduction was 2.97 W at a sampling rate of 120 kS/s, that included the I/O and two 4-to-1 demultiplexer. This suggested SAR ADC's meritocracy estimate was around 36.9 Volts [10]. ...
A Digital-to-Analog Converter (ADC) converts various forms of communication in the real world to portable digital integers. ADCs play a vital role as it interfaces between the analog world and digital world. Wireless sensor networks and biomedical interfaces are common examples of applications that demand ultra-low power consumption in the ADC. This research paper shows reduction in the energy consumption of an ADC used in neurostimulator which stimulates the brain for the people suffering from various disorders which includes Tumours, Parkinson’s disease, Obsessive Compulsive Disorder (OCD), Epilepsy, and many more. The simulation is carried out by Cadence Virtuoso tool using various technologies.
... The comparator now performs comparison at its inputs, MSB bit in the SAR register is set then 32Cu is connected to GND, similarly the operation is repeated by connecting 16Cu to VREF and the cycle is repeated until the LSB bit is decided and all the 14-bits are set/reset in SAR register. This sort of DAC operation is referred to as monotonic since only one capacitor switch is used for each bit cycle, reducing charge transfer and resulting in lower power dissipation [29]. ...
The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.
... The mixed-signal chips in portable electronic devices such as smart phones and smart watches, are power hungry systems, and the demand for efficient ultra-low power circuits is increasing just as rapidly due to the required battery operations of these handheld devices [1,2]. These devices usually have an ultra-low supply voltage in order to reduce power consumption and safety [3]. ...
A bulk-driven low-impedance compensation technique is proposed for ultra-low supply voltage amplifiers. By using the low resistance node of the current mirror of input, the efficiency of Miller compensation capacitor is greatly improved. By using this compensation method, a rail-to-rail input & output bulk-driven fully differential operational amplifier is also presented in the paper. The effectiveness of the circuit has been verified in a 65 nm CMOS process, the proposed three-stage amplifier has over 70.69 dB gain, 19.95 kHz gain-bandwidth product, and 69.7° phase margin while consuming only 8.72 nW power, and occupying die area of 0.00082 mm² from a 0.3 V supply while driving a 100pF load.
... In the literature, a wide variety of ADC architectures [16,19] have been reported considering contrasting metrics of speed, resolution and power efficiency. Any ADC must be power efficient in the context of remote patient monitoring, and in recent years, successive approximation register (SAR) ADCs have been regarded as the most suitable architecture for such applications [2,11,14,28]. A SAR ADC comprises of feedback digital-to-analog converter (DAC), comparator and successive approximation logic. ...
In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of \(568\,\upmu \hbox {m} \times 298\,\upmu \hbox {m}\) and consumes a power as less as \(0.28\,\upmu \hbox {W}\). It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/− 0.84 least significant bit (LSB) and + 0.1/− 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step.
... WITH THE RELATED WORKSRef.[9](Sim.)Ref.[10](Chip)Ref.[3] (Chip) This Work (Sim.) ...
In this contribution, it is proposed to limit the quantization search space of a successive approximation analog-to-digital converter through an analytic derivation of maximum possible sample-to-sample variation. The presented example design of the proposed ADC is an 8-bit 1MS/s ADC with SAR logic customized to incorporate this priori information while no modification has been required to the analog circuitry. In comparison to conventional SAR conversion, the proposed tracking approach yields significant reduction in total power consumption in oversampling mode. The power savings are due to the reduced number of SAR cycles, and voltage variation minimization across DAC capacitors. The design is reconfigurable both to conventional SAR sampling and the proposed tracking scheme. The approach is attractive for SAR ADCs embedded in very low power micro-controllers.
