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This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (1...
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... support the proposed baseband processing associated with the block-level interleaved-BCH ECC, we introduce in this work the dedicated hardware architecture that minimizes the hardware overheads while proving the high-throughput and low-latency data transmission. Figure 7 illustrates the block diagram of the proposed baseband architecture that can support both TX and RX modes. Note that we utilize the flexible FIFO architectures that can change the bandwidth of interfaces. ...
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... precisely, the IFIFO can support 16b and 18b input interfaces, which are used for TX and RX modes, respectively. Similarly, the OFIFO provides two options at the output interface, as depicted in Figure 7. By utilizing the flexible interfaces, it is possible to minimize the complexity overheads to support the different transmitting rates between the serialized video stream and the RF data, which are caused by appending the ECC parity information. ...
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... utilizing the flexible interfaces, it is possible to minimize the complexity overheads to support the different transmitting rates between the serialized video stream and the RF data, which are caused by appending the ECC parity information. Then, the 18-parallel BCH encoder in Figure 7 accesses IFIFO to get one 18b data block at a time. In the parallel encoder, whose internal processing architecture is detailed in Figure 8a [28,29], there is a path to directly transfer the issued data block to the interleaver so that the proposed digital baseband processing continuously constructs the frame segments. ...
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... encoding all the CCs, i.e., generating a data frame to be transmitted, the OFIFO accesses the FBx through the unified buffer manager to take 18 bits at a time, which is transferred to the analog serializer producing the bit-stream for a transmission lane of 60 GHz RF circuits. Note that the proposed baseband architecture in Figure 7 can be also used for supporting the RX mode. In contrast to the digital baseband system in TX mode receiving 16b-parallel data stream from the de-serializer handling the host multimedia source, the de-serializer now manages the input Electronics 2019, 8, 815 8 of 13 bit-stream from the RFIC associated with the higher transmission rate, generating the parallel data stream of 18 bits. ...
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... precisely, as described in Figure 8b, the well-known three-stage pipelined decoder architecture associated with the codeword FIFO is introduced where each stage is fully optimized by adopting the previous techniques including the common subexpression (CSE)-elimination on syndrome calculation (SC) and Chien search (CS) units [34] and the low-complexity folded architecture on key equation solver (KES) unit [35]. As depicted in Figure 7, the decoded block is moved to the OFIFO, which is accessed by the serializer with the 16b output interface, providing the original media information to the wireless HMD. ...
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... provide the data rate of more than 12 Gbps, which is sufficient to transfer the uncompressed FHD video stream, we utilize two identical baseband systems in Figure 7, each of which is connected to the orthogonal transmission lane of QPSK modulation. By removing all the complicated iterative processing in the previous specifications targeting the near-field wireless communication [6][7][8], the proposed baseband processing still recovers the erroneous channel conditions with the simple hardware configurations, acceptable for wireless VR systems whose HMD architecture is normally energy-limited. ...
Citations
... Power consumption was estimated from the synthesized design using synthesis Design Compiler tools from Synopsys. It is worth noting that the 65 nm technology has been widely considered for the design of various wireless communications systems as reported in [37] and the references listed therein. ...
Estimating the power consumption and computational complexity of various digital signal processing (DSP) algorithms used in wireless communications systems is critical to assess the feasibility of implementing such algorithms in hardware, and for designing energy-constrained communications systems. Therefore, this paper presents a novel approach, based on practical system measurements using field programmable gate array (FPGA) and application-specific integrated circuit (ASIC), to evaluate the power consumption and the associated computational complexity of the most common mathematical operations performed within various DSP algorithms. Using the proposed approach, a new metric is developed for mapping the computational complexity to the computational power consumed by the mathematical operation in wireless transceivers. This allows combining the commonly used computational complexity metrics that are typically computed for each mathematical operation separately. Consequently, a single unified metric can be used to describe the entire algorithm. Therefore, the comparison and trade-offs between different algorithms become easier and more informative. The developed approach is used to evaluate the computational power of several DSP algorithms used in wireless communications systems, and perform thorough computational complexity comparisons. The obtained results reveal that computational complexity comparisons using different mathematical operations can be highly misleading in several scenarios. The power consumption evaluation of the considered DSP algorithms show that some algorithms may require a prohibitively high power, which makes such algorithms unsuitable for power-constrained wireless communications systems. The results also show that the proposed methodology can be adopted for various hardware implementation, however, some calibration might be required based on the adopted platform.
... However, OFDM has two major drawbacks: high sensitivity to Doppler spread, dependent on the system's mobility, and a high peak-to-average power ratio (PAPR), proportional to the length of the Fourier transform. In high carrier frequency bands (e.g., 60-70 GHz), even a small movement in the transceivers can cause a high Doppler spread, provoking intercarrier interference and long transmission latencies [1]. To avoid excessive PAPR while complexity equalization remains low in the frequency domain, the discrete-Fourier-transform (DFT)-Spread OFDM has been employed. ...
Maximum likelihood sequence estimation (MLSE) and maximum a posteriori probability (MAP) equalizers are optimum receivers for dealing with intersymbol interference (ISI) in time-dispersive channels. However, their high complexity and latency limit their widespread implementation; therefore, research into reducing their complexity is an open topic. This paper proposes a novel modification to reduce the computational complexity of the aforementioned algorithms, which exploits the representation of the communication channels in a time-delay-domain basis expansion model (BEM). It is shown that an appropriate basis is a set of modified prolate functions, in which the transmitter and receiver filters are considered in the kernel construction. Simulation results show that a reduction in sums and multiplications on the order of 55% can be obtained, maintaining the same bit error rate performance as in the traditional implementation.
