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Embedded systems are increasingly pervasive, interdependent and in many cases critical to our every day life and safety. Tiny devices that cannot afford sophisticated hardware security mechanisms are embedded in complex control infrastructures, medical support systems and entertainment products [51]. As such devices are increasingly subject to atta...
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... addition to validating the data ad- dress generated by the instruction execute unit, the instruc- tion address of the executing instruction is also considered. The resulting scheme is illustrated in Figure 2, where the MPU not only validates data accesses (object, read/write/ex- ecute) but additionally considers the currently active instruc- tion pointer (curr_IP) as the subject performing the access. ...
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... target technology was a Xilinx Virtex-6 FPGA. In par- ticular, we realized execution-aware memory protection by linking the respective code and data regions provided by the stock MPU as illustrated in Figure 2, using the first four bytes of each code region as its respective entry vector. Ad- ditionally, a 32 bit register storing the secure stack pointer location of each trustlet is associated with each code region to facilitate secure exception handling. ...
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In this paper, a runtime diagnosis infrastructure is presented for embedded systems. Different from existing methods of tracing system logs offline, our research focuses on analyzing system kernel data structures from runtime memory against predefined constraints periodically. The prototype system is developed based on a system virtualization layer...
Citations
... All existing symmetric CRAs utilize Trusted Execution Environment (TEE) architectures, such as SMART [33], TrustLite [34], and TyTan [35]. These architectures are distinct from SDATA; hence, a comparison with them has not been conducted. ...
Efficient safeguarding of the security of interconnected devices, which are often resource-constrained, can be achieved through collective remote attestation schemes. However, in existing schemes, the attestation keys are independent of the device configuration, leading to increased requirements for the trusted computing base. This paper introduces a symmetrical aggregate trust attestation that is compatible with devices adhering to the device identifier composition engine framework. The proposed scheme simplifies the trusted computing base requirements by generating an attestation key that is derived from the device configuration. Moreover, the scheme employs distributed aggregate message authentication codes to reduce both the communication volume within the device network and the size of the attestation report, thereby enhancing the aggregation efficiency. In addition, the scheme incorporates interactive authentication to accurately identify compromised devices.
... RA presents a security technique in which a trusted verifier assures the integrity of a prover, i. e., the untrusted device. There are a number of research efforts that propose secure and lightweight hardware architectures such as SMART (Eldefrawy et al., 2012) and TrustLite (Koeberl et al., 2014) to provide a secure remote attestation for embedded and IoT devices. Such architectures adopt minimal hardware components such as simple memory protection units (MPU) (Mohan et al., 2018). ...
Security in the Internet of Things (IoT) remains a predominant area of concern. Although several other surveys have been published on this topic in recent years, the broad spectrum that this area aims to cover, the rapid developments and the variety of concerns make it impossible to cover the topic adequately. This survey updates the state of the art covered in previous surveys and focuses on defences and mitigations against threats rather than on the threats alone, an area that is less extensively covered by other surveys. This survey has collated current research considering the dynamicity of the IoT environment, a topic missed in other surveys and warrants particular attention. To consider the IoT mobility, a life-cycle approach is adopted to the study of dynamic and mobile IoT environments and means of deploying defences against malicious actors aiming to compromise an IoT network and to evolve their attack laterally within it and from it. This survey takes a more comprehensive and detailed step by analysing a broad variety of methods for accomplishing each of the mitigation steps, presenting these uniquely by introducing a “defence-in-depth” approach that could significantly slow down the progress of an attack in the dynamic IoT environment. This survey sheds a light on leveraging redundancy as an inherent nature of multi-sensor IoT applications, to improve integrity and recovery. This study highlights the challenges of each mitigation step, emphasises novel perspectives, and reconnects the discussed mitigation steps to the ground principles they seek to implement.
... Similarly, Intel Turstlite [75], a generic security architecture suited to low-power embedded devices, allows remote management, authentication, and over the air (OTA) updating as well as remote attestation [76]. Among low-cost solutions, IoTware memory access control can also be implemented using SMART [79], using a ROM measurement routine with a secret key to provide remote attestation. ...
In recent years, the Internet of Things (IoT) paradigm has been widely applied across a variety of industrial and consumer areas to facilitate greater automation and increase productivity. Higher dependability on connected devices led to a growing range of cyber security threats targeting IoT-enabled platforms, specifically device firmware vulnerabilities, often overlooked during development and deployment. A comprehensive security strategy aiming to mitigate IoT firmware vulnerabilities would entail auditing the IoT device firmware environment, from software components, storage, and configuration, to delivery, maintenance, and updating, as well as understanding the efficacy of tools and techniques available for this purpose. To this effect, this paper reviews the state-of-the-art technology in IoT firmware vulnerability assessment from a holistic perspective. To help with the process, the IoT ecosystem is divided into eight categories: system properties, access controls, hardware and software re-use, network interfacing, image management, user awareness, regulatory compliance, and adversarial vectors. Following the review of individual areas, the paper further investigates the efficiency and scalability of auditing techniques for detecting firmware vulnerabilities. Beyond the technical aspects, state-of-the-art IoT firmware architectures and respective evaluation platforms are also reviewed according to their technical, regulatory, and standardization challenges. The discussion is accompanied also by a review of the existing auditing tools, the vulnerabilities addressed, the analysis method used, and their abilities to scale and detect unknown attacks. The review also proposes a taxonomy of vulnerabilities and maps them with their exploitation vectors and with the auditing tools that could help in identifying them. Given the current interest in analysis automation, the paper explores the feasibility and impact of evolving machine learning and blockchain applications in securing IoT firmware. The paper concludes with a summary of ongoing and future research challenges in IoT firmware to facilitate and support secure IoT development.
... For trusted sensors, we identify Sancus [28] and TrustZone [26] as suitable TEEs, as both can be deployed for low costs (G4) while achieving the discussed performance requirements (G5). Other embedded security architectures [85], [86] may similarly suffice as long as they provide isolation and attestation primitives. Similarly, the utilized attestation protocol and implementation are equally interchangeable, and respective related work on improving remote attestation can be integrated [15]. ...
Supply chains increasingly develop toward complex networks, both technically in terms of devices and connectivity, and also anthropogenic with a growing number of actors. The lack of mutual trust in such networks results in challenges that are exacerbated by stringent requirements for shipping conditions or quality, and where actors may attempt to reduce costs or cover up incidents. In this paper, we develop and comprehensively study four scenarios that eventually lead to end-to-end-secured sensing in complex IoT-based supply chains with many mutually distrusting actors, while highlighting relevant pitfalls and challenges—details that are still missing in related work. Our designs ensure that sensed data is securely transmitted and stored, and can be verified by all parties. To prove practical feasibility, we evaluate the most elaborate design with regard to performance, cost, deployment, and also trust implications on the basis of prevalent (mis)use cases. Our work enables a notion of secure end-to-end sensing with minimal trust across the system stack, even for complex and opaque supply chain networks.
... The hybrid (software/hardware co-design) attestation techniques use minimal hardware support as mentioned in [12,13]. Defrawy et al. in SMART [13] present secure attestation with minimal hardware changes in memory controller unit (MCU). ...
... SMART additionally utilizes MCU to provide access control to memory region to only the secure code, thus guarantying privacy and security of its contents. TrustLite [12], a follow-up work on SMART, generalizes this idea to introduce Execution Aware Memory Access Control (EA-MAC). TyTAN [14] extends TrustLite's approach with dynamic configuration of access control rules, albeit it incurs additional architectural complexity. ...
... After that, it receives cumulative member devices' attestation report. Both approaches need minimal trusted components-called trust anchors (i.e., read-only verification code, secure key storage, and atomicity of execution of verification code), as provided by SMART [13], TrustLite [12], and TyTAN [14] architectures. ...
Application domains in embedded systems such as Industrial Internet of Things (IIoTs) involve smart, mobile, and interconnected devices that operate in large numbers (devices swarms). These devices process and exchange safety, privacy, and mission-critical information. Thus, message exchanges, task collaborations, and service deliveries necessitate the communicating devices to trust each other. In this regard, it is essential to have a suitable device verification technique that scales to device swarms and establishes trust among collaborating devices. However, state-of-the-art device swarm attestation schemes assume a single external verifier and do not offer resiliency. In addition, in a swarm of self-organizing IoT networks, each member device independently changes its position (i.e., continuously entering and leaving the network). Thus, it becomes very challenging for the trusted external verifier to track these mobile devices, which further exacerbates the problem of authentication, identification, and management of swarm members. We present a novel AI-powered self-healing decentralized attestation that distributes attestation among devices for systems that work in swarms. Decentralization decreases delay and overcomes the problem of a single point of failure. To ensure swarm security, interoperability, and management, we use a reusable digital identity for each physical system (IoT node), allowing authentication and authorization of access. Each device is leveraged with an ML model, where verifications are carried out on its device twin, that is, the digital representations of the attestable properties of the member device. After each attestation, our system quickly extracts information about swarm members and establishes a chained relationship (chains of trusted blocks) with one another. This chain comprises devices with benign software configurations. We evaluate performance and demonstrate if the execution overhead is negligible. We also analyze security and show that the proposed technique is very effective and robust against various attacks.
... It also has a memory protection unit 610 (MPU) that manages access to the part of the ROM, holding attestation key. Similarly, the TrustLite [66] provides an attestation mechanism for devices equipped with Intel's Siskiyou Peak Research platform. TrustLite's secure architecture enables secure execution of the program code by incorporating an execution-aware memory protection unit (EA-MPU). ...
... The majority of current remote attestation methods [30,37,65,66] are susceptible to a single point of failure -the verifier node [73]. To address this issue, secure hardware-based or co-processor-based 895 attestation approaches have been developed that alleviate many of the vulnerabilities of software-based methods. ...
IoT devices, whether connected to the Internet or operating in a private network, are vulnerable to cyber attacks from external or internal attackers or insiders who may succeed in physically compromising an IoT device. Once compromised, the IoT device can join a botnet to participate in large-scale distributed attacks (potentially recruiting additional nodes), exfiltrating confidential data or injecting false data into critical data sets, corrupting subsequent data analytics. Although various device attestation techniques are available to detect malicious IoT devices, these methods do not fully address all aspects of a po- tentially compromised node. This study explores current state-of-the-art approaches for detecting a malicious/compromised node in the network, highlights related challenges, and proposes a way forward for developing secure and economical attestation protocols.
... isolates a portion of memory and prevents any programs from being loaded which could allow unauthorised access to this region of memory. Attestation code can reside within this region of memory instead of Read-Only Memory (ROM) as used by SMART [18] or TrustLite [25]. SIMPLE+ extends SIMPLE to collective remote attestation, where a single verifier attests an arbitrary number of provers. ...
... These keys are stored in a secure region of memory, alongside a counter , an attest variable (initially 1), and the prover's identifier . A secure region of memory is one that is protected by a secure architecture [13,18,25] that prevents access by any software, which could be malware, other than the attestation protocol. ...
... Many hardware-based isolation solutions exist for low-end embedded systems like TrustedFirmware-M [9], RIOT OS (MPU) [10], Zephyr RTOS (MPU) [11], FreeRTOS-MPU [12], EwoK [13], MINION [14], ACES [15], OPEC [16], MultiZone [17], TrustLite [18], CheriRTOS [19], MbedOS [20], TockOS [21], hardened Java Card Virtual Machine (JCVM) [22]. They show different isolation techniques that exhibit various levels of guarantees, ease of use, and functionalities. ...
... TrustedFirmware-M [9], RIOT OS (MPU) [10], Zephyr RTOS (MPU) [11], FreeRTOS-MPU [12], EwoK [13], MINION [14], ACES [15], OPEC [16], Multi-Zone [17], TrustLite [18], CheriRTOS [19], MbedOS [20], TockOS [21], hardened Java Card Virtual Machine [22] ProvenCore-M [30] (proprietary) ...
Pip-MPU is a minimalist separation kernel for constrained devices (scarce memory and power resources).In this work, we demonstrate high-assurance of Pip-MPU’s isolation property through formal verification.Pip-MPU offers user-defined on-demand multiple isolation levels guarded by the Memory Protection Unit (MPU).Pip-MPU derives from the Pip protokernel, with a full code refactoring to adapt to the constrained environment and targets equivalent security properties.The proofs verify that the memory blocks loaded in the MPU adhere to the global partition tree model.We provide the basis of the MPU formalisation and the demonstration of the formal verification strategy on two representative kernel services.The publicly released proofs have been implemented and checked using the Coq Proof Assistant for three kernel services, representing around 10000 lines of proof.To our knowledge, this is the first formal verification of an MPU-based separation kernel.The verification process helped discover a critical isolation-related bug.
... Trustlite (2014) [17] extends SMART, with larger access control rules for the MPU. It takes into account different kinds of memory hardware, such as DRAM and Flash, as well as peripherals, such as timers. ...
An exponential number of devices connect to Internet of Things (IoT) networks every year, increasing the available targets for attackers. Protecting such networks and devices against cyberattacks is still a major concern. A proposed solution to increase trust in IoT devices and networks is remote attestation. Remote attestation establishes two categories of devices, verifiers and provers. Provers must send an attestation to verifiers when requested or at regular intervals to maintain trust by proving their integrity. Remote attestation solutions exist within three categories: software, hardware and hybrid attestation. However, these solutions usually have limited use-cases. For instance, hardware mechanisms should be used but cannot be used alone, and software protocols are usually efficient in particular contexts, such as small networks or mobile networks. More recently, frameworks such as CRAFT have been proposed. Such frameworks enable the use of any attestation protocol within any network. However, as these frameworks are still recent, there is still considerable room for improvement. In this paper, we improve CRAFT’s flexibility and security by proposing ASMP (adaptative simultaneous multi-protocol) features. These features fully enable the use of multiple remote attestation protocols for any devices. They also enable devices to seamlessly switch protocols at any time depending on factors such as the environment, context, and neighboring devices. A comprehensive evaluation of these features in a real-world scenario and use-cases demonstrates that they improve CRAFT’s flexibility and security with minimal impact on performance.
... For instance, hardware virtualization extensions [9,10], SGX enclaves [11][12][13], and tagged memory architectures [14][15][16], which are commonly used in security solutions, are unsuitable for low-end embedded devices due to the additional hardware costs and power consumption. To overcome this challenge, researchers have proposed alternative methods to enhance the security of embedded systems, such as the memory isolation technique [17][18][19][20]. This technology enhances the security of embedded systems by limiting the range of accessible code and data regions. ...
... This overhead can lead to latency issues if domain switching occurs frequently. To address this limitation, several studies have proposed ways to support unprivileged domains, such as EA-MPU [18,19], ARM Trustzone-M [21]. These approaches eliminate the intervention of the privilege level during the domain-switching process, thus reducing the overhead associated with this conversion process. ...
... To improve the efficiency of MPU, some works have proposed an extended MPU called the Execution-Aware MPU (EA-MPU) [18,19]. EA-MPU proceeds further than traditional MPUs by managing the legitimate code regions that can be accessed for each memory entity. ...
Memory isolation is an essential technology for safeguarding the resources of lightweight embedded systems. This technique isolates system resources by constraining the scope of the processor's accessible memory into distinct units known as domains. Despite the security offered by this approach, the Memory Protection Unit (MPU), the most common memory isolation method provided in most lightweight systems, incurs overheads during domain switching due to the privilege level intervention. However, as IoT environments become increasingly interconnected and more resources become required for protection, the significant overhead associated with domain switching under this constraint is expected to be crucial, making it harder to operate with more granular domains. To mitigate these issues, we propose DEMIX, which supports efficient memory isolation for multiple domains. DEMIX comprises two mainelements-Domain-Enforced Memory Isolation and instruction-level domain isolation-with the primary idea of enabling granular access control for memory by validating the domain state of the processor and the executed instructions. By achieving fine-grained validation of memory regions, our technique safely extends the supported domain capabilities of existing technologies while eliminating the overhead associated with switching between domains. Our implementation of eight user domains shows that our approach yields a hardware overhead of a slight 8% in Ibex Core, a very lightweight RISC-V processor.
