Alternative Logic of 1-bit adder in [6, 7], (a) and (b) General block diagram form of AL-1 and AL-2 respectively, (c) and (d) are circuit representations of AL1 and AL-2, respectively. 

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... architectures AL-1 and AL-2 reported in [6,7], and AL-3 proposed in this paper, together classified as another (4 th ) category, herein. The AL-1 and AL- 2 architectures have been realized based on double pass logic (DPL) and CMOS transmission gate logic, resulting in mixed logic style implementation, whose block diagram and circuits are given in Fig. 1 and discussed in subsequent subsection. A variant of AL-1 and AL-2 architectures called AL-3 is proposed in this paper and discussed in section 3. The performances of all the 3 architectures are compared with respect to the delay, power, and PDP performance metrics and discussed later section 4 and ...

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... block diagrams of Fig. 1(a) and (b) shows the general architecture of 1-bit adders: AL-1 and AL-2; and Fig. 1 (c) and (d) show the circuit implementation of AL-1 and AL-2 architectures using the DPL logic, and they are 28T and 26T implementations, respectively. In AL-1 the XOR, XNOR, AND, and OR gates were implemented independently. In AL- 2 the XOR and XNOR are ...

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... block diagrams of Fig. 1(a) and (b) shows the general architecture of 1-bit adders: AL-1 and AL-2; and Fig. 1 (c) and (d) show the circuit implementation of AL-1 and AL-2 architectures using the DPL logic, and they are 28T and 26T implementations, respectively. In AL-1 the XOR, XNOR, AND, and OR gates were implemented independently. In AL- 2 the XOR and XNOR are implemented together, which saves 2 transistors, whereas the AND and OR gates ...

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... implementation of AL-1 and AL-2 architectures using the DPL logic, and they are 28T and 26T implementations, respectively. In AL-1 the XOR, XNOR, AND, and OR gates were implemented independently. In AL- 2 the XOR and XNOR are implemented together, which saves 2 transistors, whereas the AND and OR gates implemented independently, as shown in the Fig. 1(b), whereas the gates XOR and XNOR are integrated together. In Fig. 1, for better correlation between the block diagram and circuits, we have circled and labelled the corresponding ...

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... they are 28T and 26T implementations, respectively. In AL-1 the XOR, XNOR, AND, and OR gates were implemented independently. In AL- 2 the XOR and XNOR are implemented together, which saves 2 transistors, whereas the AND and OR gates implemented independently, as shown in the Fig. 1(b), whereas the gates XOR and XNOR are integrated together. In Fig. 1, for better correlation between the block diagram and circuits, we have circled and labelled the corresponding ...

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... the Fig. 1, the output bits are expressed by the following equations. ...

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... select signal, i.e., sum S i is equal to A i .B i . C i value when carry output C i+1 is equal to '1', and to A i +B i +C i value when C i+1 is equal to '0'. This approach leads to carry (C i+1 ) dependant sum (S i ) AL-3 architecture. Thus the Boolean expressions for the sum and carry output bits are expressed by the following logic expressions; Fig. 1(c)); but AL-3 circuit proves to be better in terms of power, delay and PDP parameters, over both AL-1 (28T) and AL-2 (26T), presented and discussed in section ...

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... W/L g ratios, of the N/PMOS transistors are indicated next to each transistor, in Fig. 1(c), 1(d), and Fig. 2(b). We have adopted the transistor sizing methodology as suggested in [6,8,9]. The steps of this methodology are given as ...

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... was noticed that the proposed 1-bit adder AL-3 is having less delay compared to AL-1 and AL-2 circuit when V DD is increased beyond ~0.7V. This improvement in delay for AL-3 is attributed to relatively smaller intermediate node and output node parasitic capacitances ( Fig. 1 and Fig. 2). For V DD below 0.6V, the functionality of the 3 adders becomes indeterminate. ...