Fig 3 - uploaded by N. Jeebaratnam
Content may be subject to copyright.
16-bit CSLA architecture using BEC
Source publication
This Carry select adder (CSLA) is the primary entity in the field of arithmetic processing. Every arithmetic calculation is processed mainly through the CSLA. Conventional CSLA design and implementation will adversely effects the space and power usage, eventually affecting the whole chip efficiency. Changes in the CLSA design can yield the complete...
Similar publications
World population has almost doubled during the last century increasing dramatically the need for food to support the population over 7 billion persons. Precision agriculture is a type of innovative agriculture, based on new technologies, which aims to streamline the agricultural process. Parameters such as temperature, humidity, soil characteristic...
Fall is one of the leading causes of accidental or unintentional injury deaths worldwide due to serious injuries such as head traumas and hip fractures. As life expectancy improved, the rapid increase in aging population implied the need for the development of vital sign detector such as fall detector to help elderly in seeking for medical attentio...
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and modeling digital systems. We fine-tune pre-existing LLMs on Verilog datasets compiled from GitHub and Verilog textbooks. We evaluate the functional correctness of the gener...
As large language models (LLMs) like ChatGPT exhibited unprecedented machine intelligence, it also shows great performance in assisting hardware engineers to realize higher-efficiency logic design via natural language interaction. To estimate the potential of the hardware design process assisted by LLMs, this work attempts to demonstrate an automat...
Addressing challenges regarding Hybrid Optoelectronic Network-on-Chip systems, such as congestion control, their limited adaptability, and their inability to facilitate optoelectronic co-simulation, this study introduces an adaptive hybrid optoelectronic interconnection shunt structure tailored for reconfigurable array processors. Within this frame...
