VLSI - Science topic

Dear Profs/ Scientist, if any one is interested or have plan to publish a good quality books/ book edited , I can contribute/help such type of research works . My research interest is : Integrated Circuits, Microelectronics, VLSI, Advanced Circuit Design , Low power electronics, Ferroelectric based Device and Development . My/our latest publications :

Handbook of Emerging Materials for Semiconductor Industry

https://link.springer.com/referencework/10.1007/978-981-99-6649-3

Advanced Ultra Low-Power Semiconductor Devices: Design and Applications

Interested expert can email : sbrahi@gmail.com

Details will be discuss step by step

More details about my publications are avialble:

Google scholar links:

Amazon link:

https://www.amazon.in/s?i=stripbooks&rh=p_27%3AShiromani+Balmukund+Rahi&ref=dp_byline_sr_book_3

IEEE International Conference on Omni-Layer Intelligent Systems (COINS-2024) is excited to announce a special session on the Use of Microelectronics in IoT and AI ecosystem Sustainability as part of our upcoming conference, scheduled to take place at King's College, London, 29-31 July 2024. This special session offers a unique opportunity for graduate students, researchers, scholars, supervisors, experts from diverse fields, and industrialists to present their work and engage in discussions focused on Microelectronics applications in IoT and AI ecosystem sustainability.

Special Session Theme:

We welcome original research papers, case studies, innovative practices, and work in progress that contribute to advancing knowledge and understanding within the scope of IoT and AI Ecosystem Sustainability. Submissions may explore empirical, conceptual, or practical aspects, including various perspectives, disciplines, and methodological approaches toward IoT and AI Ecosystem Sustainability. The topics of interest include but are not limited to:

➢ Semiconductor,

➢ Electronics devices,

➢ Microelectronics

➢ Nanotechnology

➢ Nanomaterials

➢ e-waste

➢ Bio-degradable in electronics

➢ VLSI/ULSI.

Kindly help me by providing the values of electronic properties (bandgap, electron and hole density of states, dielectric permittivity and electron and hole mobilities) of Niobium Nitride (NbN) at room temperature and cryogenic temperature application. It would be of great help for my study.

Greetings everyone,

Field: VLSI/Microelectronics/Solid State Electronics

I am from the VLSI field, and many times, a comment comes regarding the fabrication process flow of surrounding gate MOSFET structures. I wonder how to draw the 3D MOSFET (concentric cylinders) or the fabrication process flowchart with block diagrams. Which software do you use to draw similar things? I am attaching a picture for reference.

Any response is appreciated.

Thanks and regards

Is system operating with low frequency dissipates higher leakage power than system operating with high frequency?

Both SRAM and Flip-flop are volatile memory element. Is there any applications where both are used?

critical path analysis of digital VLSI circuit, any tools for finding it?

Hi, Looking for your kind reply.Thanks in Advance.

Like MPFP, important sampling etc.

When we measure voltage across a isolated diode, what will the voltmeter read?

1) 0 V but voltmeter shows a non zero value which is approximately equal to built-in voltage.

2) Built in voltage but if it's the case then why can't we use diode as a voltage source?

PS : I was taught in my bachelors that we get a 0V reading across diode which is the algebraic sum of built in voltage and the voltage across metal(wire)-semiconductor interface.

I found that, latches can capable to hold the correct data even the data changes slightly before the falling edge of the clock.

What is the major difference between the pre-layout and post-layout simulation?

how one can estimate the drain area?

Hey guys,

Please suggest the list of scopus list of journals for VLSI, Wireless networks and Wireless communications (Unpaid and paid)

Hi all,

Does PUF stop side channel attacks?? If so, how does PUF stop side channel analysis based on timing differences or power differences??

Thanks in advance..

How variation of Vth and Tox impact on performance of the mos circuit?

Hello everyone,

I had written two papers. One of the paper is on analog performance of GAA MOSFET and second one is on bio sensing performance of GAA MOSFET.

Both these papers are simulation based. I had sent them to various journals but unfortunately got rejected due to absence of any device physics( I am working on device physics in my current work-next paper).

I want to know if any Scopus or SCI based journal that can possibly accept these papers. I am really depressed since its been more than a year but its getting rejected. Any Scopus journal will also work but should be recognized.

Please, suggest me some journals seniors and respected people. Kindly help me.

I have made a current mode Flash ADC which works at around 100MHz. I need to design a S&H circuit for sampling the input current.

I am plotting the graphs in MS EXCEL. But after seeing IEEE papers, I noticed that the figures are small with a better clarity. I am wondering if there is any other software that may be used for the same. I know there are many free softwares but which software do you prefer.

When I try to reduce my figure size(plotted in EXCEL), it looks distorted.

Any suggestion will be appreciated.

EDIT (10/10/2022): I have used ORIGIN for the recent papers and the results are quite satisfactory.

I have been working with Floating Gate MOSFET(FGMOS) to see its performance on different parameters for different dielectrics(including stack and engineered dielectrics) I could not find any software or any particular method of simulation for getting the data. Can anyone suggest a way to do it?

CMOS is used in VLSI. Can advancement in CMOS nanoscale increase the endurance life of VLSI?

with HDL coding, we can do functional verification. what else can we do with the help of other tools may be like chipscope pro, FPGA board etc

In my design I require some transistors with high threshold voltage. At schematic level, what changes should I do so that I can get transistors with high threshold voltage.

"Self-fulfilling prophecy" is Moore's own definition, while "a convenient fiction" is somebody else's...

I have decided that, giving some excerpts from two relevant articles will be more helpful than trying to explain my personal views in detail.

A.Z.

Excerpts from the article "Was Moore’s Law Inevitable?" by Kevin Kelly:

Excerpts from the article "A Moore’s Law Mystery" by Rose Eveleth:

Recently, IBM have made the claim that they achieved the world's first 2 nm process node using nanosheet technology.

The media -as expected- jumped right into it, and some started comparing transistor size to the atom and "Fingernail" sizes!

While the research is (obviously) very remarkable and exciting, why does the industry still use such inaccurate descriptions, that even experts in the field get wrong.

Why not -at least- talk about transistor density !

How the interconnect could be handled?

What about the yield?

What does this mean for the final chip performance and pricing?

Notes: Some say that EUV is adopted at all levels of the process.

Currently, I'm working with Adiabatic Logic, I have found few quality papers, most of the papers just discussed some adiabatic logic families but haven't compared them with conventional CMOS logic. While I was simulating some adiabatic logic gates and measured power then compared with corresponding conventional CMOS logic gates, I have seen conventional logic dissipates less power. My question is, why adiabatic is then considered a good methodology for low power VLSI?

I have used 16nm PTM LP model in LTspice to run the simulation.

Hi all,

Can anyone suggest how to execute a Perl Script on windows 10 ???

I am using Strawberry 🍓 Perl for this.

When I am trying to execute as below under C drive in command prompt ,I am getting error.

C: perl hello_world.pl

Can anyone one help me out.

Thanks.

It is a general practice to introduce Ground Plane in FDSOI devices under the BoX. The Ground Planes are introduced by Ion Implantation through Top Si layer and Buried Oxide. I wanted to know that by doing this implantation, don't they harm the crystalanity of the Top Si layer in which the FDSOI MOSFET will be formed ? Since in FDSOI, they prefer very Low doped or even undoped Si channel, so by doing Ground Plane implantation, don't they affect the intrinsic/undoped/low-doped nature of top Si layer.

Digital Twin NEWS! -ISO-IEC-JTC1-SC41-IoT has launched its Digital Twin framework standardisation at its Nov. Plenary. -Edge Computing & Networking, from VLSI to AI and back, in real time when needed, is essential in this endeavour, with specifications from ETSI (ETSI-ISG-MEC: Multi-Access Edge Computing), 3GPP and One M2M supporting this goal. Cyberphysical systems benefit highly of Digital Twins for optimised fault-tolerant operation, verification and validation, simulation, in particular. -Combining functionalities tightly is a must: software, efficient/secure and sustainable data handling, computing and networking may have to be jointly managed, and possibly integrated at every node of a system using fully Digital Twins.

Speed and energy efficiency are available from VLSI chips integrating two functional layers as the IMX500 from Sony: -Data layer: interfacing to the real world (analogue to digital sampling, and digital to analogue rendering, "data I/O" layer)

-Processing layer ("logic" layer) e.g. with AI algorithms to build or prepare decisions from the data acquired, and conversely to manage and implement decisions into the physical world.

Use cases include smart city functionalities, cognitive design/manufacturing, autonomous systems/vehicles.

What is your view on Digital Twin, in what role is it best positioned? Design? Operation? Fault correction? Other?

For research purpose.

In bist(built-in-self-test) how to calculate the known good signature pattern which is used to compare with test pattern result . I am designing bist implementation for multiplier circuit using cbilbo registers in VHDL. Please help me any one .

1. Please Enlighten me if u have any idea?

2. Please could you help in sorting the same issue?

In our current design of linear binary current steering low-noise CMOS slowDAC, we converged in the use of long channel NMOS transistors. Indeed, a low noise, lower than 10pA/√Hz at 100µA, and good matching of the weights of the binary DAC leads to the use of long channel NMOS transistor in the design of binary coded current mirrors.

It seems better to increase L than W to improve the current mirror matching looking at Monte Carlo Simulations.

NMOS sized with L as long as 20 µm for a W of 8 µm is considered. Assuming that such long channel NMOS transistors are unusual (?) in VLSI design ... have you experienced the use of long-channel transistors in VLSI DAC design? Any papers, or review about the use, and justifications, of long channel MOS transistors for ASIC design?

Trends concerning research in Digital VLSI domain.

after making the layout using Electric VLSI CAD tool i am trying to find some parameters

and i have a problem finding the input capacitance using spice

Hello sir/mam

i am using Cadence virtuoso design tool

i have generated symbol of CNTFET ( n and p type) as per Standford compact veriloga code by NCFET_L3.va

then i designed inverter.

I want to ask you >>

1. there are five terminals Gate, Drain, Source, Sub and couple node.

i have shorted to Couple Node and Sub ,,>>>for nCnFet connected to ground via source and for pCnfet these terminal connected to vdc via Source

Is it correct?

2. Next i got accurate transient response but when i start to plot for power consumed of this inverter then i am getting no curve just straight line over 0 zero.

Help Me please.

Both long-channel and cascode MOS transistors are used in VLSI design to increase output impedance of current sources (for instances : AE_Lecture8_PartB_Incremental Model of FET or Bias circuit design for low-voltage cascode transistors DOI: 10.1145/1150343.1150372).

Moreover, self-cascode MOS transistors can be definitely seen as a single long-channel MOS transistor (Self-cascode composite transistor Analog and Mixed-Signal Center - ELEN 607 ESS).

HDL - VLSI Circuits

I am looking for a circuit which can generate an emf oscillating at frequency of 2.5Ghz.

My setup is in such a way that, I am passing particles (negligible mass) from a tunnel and want an emf perpendicular to the flow. The emf should have frequency of 2.5Ghz

Please tell me some research oriented books for low power VLSI and low power Semiconductor Memory technology.

A book or some set materials are not even close to enough for CMOS Layout design. But to start with, I require a good book and some relevant materials. I have done the layouts of some basic static CMOS circuits. Now it is the time to make the layout of the design I am working with (an architecture of ternary CAM with some control and gating circuitry).

Which books or materials I can refer for an optimised layout? I am going to use virtuoso layout suite for the design.     

Hi everyone, I don't under this layout figure (5.c) in pic attached .

This is a screenshot from research paper in this link:- https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7573442

My basic Curiosity is that layout are generally in shape of squares and rectangles, but in this layout what is that blot (ink drop) like thing in fig 5.c

I am trying to extract the effective channel length of a MOS transistor in 130 nm CMOS technology (Lmin = 120 nm). Or I should say the measure of lateral gate/drain (or gate/source) overlap using DC current methods described in "MOSFET modeling for VLSI simulation" by Narain Aroa. My problem is that each method yields a (vastly) different number.

Could somebody please help, shed some light or suggest some new methodology?

Lukas

What are application areas in which VLSI and MEMS work together?

How MEMS devices play vital role in VLSI industry?

Please suggest me list of scopus indexed journals with rapid publication and low publication charges in the field of electronics/VLSI/Circuit design? plz reply asap

I am trying to write my dissertation about automatic quantification of algorithms. These algorithms are written as a C function, which represents the behaviour of a VLSI circuit. The main purpose of the dissertation is to maximize the number of removed bits from the word-lengths of the signals describing a VLSI circuit, by finding a sub-optimal combination which fits a rule. The rule is that any combination must cause an error less or equals to a boundary error.

In order to find this suitable combination which is close to the error boundary and maximize the removed bits, my dissertation supervisor suggested to use local search algorithms. Due to the execution of the quantification will be made over a GPU (CUDA), I have found that the differential evolution and cellular genetic algorithm are suitable for a SIMD machine and easy to implement and execute in parallel. The constraints of the problem are: use of fixed point quantification, error produced at the outputs = fitness function and word-lengths from 1 to 22 bits (integer values). Actually, I have implemented the canonical DE (DE/rand/1/bin) and cGA (NEWS, 2D toroidal grid) over CUDA for any number of signals describing the VLSI circuit.

Before testing the algorithms with real VLSI circuits, I am testing them with a synthetic benchmark to confirm the related work and suggestions made about DE. This benchmark returns an output error (1 output circuit) based on this formula: sum in j elements of [ (element_j_of_individual_i - element_j_of_local_optimum) * 2 * factor ] with factor selected randomly for each element for 0,5 to 0,9 . Hence, if an individual of the population is an exact match of the pre-selected local optimum, the error returned by this fitness function will be 0. For an individual who has at least one element under the corresponding element of the local optimum will be discarded (and if it belongs to the initial population, will be regenerated until obtaining a valid individual).

Using this schema, the parameters of the benchmark are:

- population size of 5D, 10D, 15D and 20D (with D = number of signals describing the VLSI circuit), with each element in the population set randomly from 16 to 22 for each execution. ex: for D = 5, individual_number_0 = {14, 17, 21, 19, 20}

- randomly pre-selected local optimum from these values: {6,7,8,9,10}. ex: for D = 5, local_optimum = {7, 10, 6, 9, 6}

- ten executions trying to eliminate someway the bias caused by a pre-selected local optimum

- F = 0.5 and CR = 0.1

- the algorithm will stop when the local optimum is found or when all the generated offsprings are not valid and/or not better than their parents

For this set-up, I have found that for 50, 100 and 150 signals, the DE found the exact pre-selected local optimum for populations of 5D, 10D, 15D and 20D in the ten executions in several iterations (if requested, I could upload the iterations, timings, etc). For 200 signals the DE only found the local optimum for 10D, 15D and 20D. For 250 signals, only one execution of the ten for 20D found the local optimum; not founding it for any iteration of 5D, 10D or 15D. I have tried to relax the termination condition of the search by establishing an error boundary some way close to 0 (like 50, 70, 100 values) to find sub-optimal solutions for population sizes of 5D, 10D, 15D and 20D (D = 250). Although I have relaxed the termination condition, the algorithm stops without founding the local optimum.

I have found the Q&A from Stephen Chen: 'What is the optimal/recommended population size for differential evolution? ' but I do not know if these questions will fit my needs a priori, because I would like to use DE for VLSI circuits up to 400 signals in a first approach.

(Edit): added some examples: one randomly initialized individual in the initial population and one randomly pre-selected local optimum.

I want to know about extraction of barrier height using silvaco atlas tool for schottky barrier mosfet simulation.

In pattern-recognition applications is common the use of log-sigmoidal neurons at the output of the NN to indicate a sort of "probability" of occurrence for events. Nevertheless, in a scenario in which the possible events must be ordered to select the most probable ones, linear activation functions could reproduce the same order (in fact, any monotonic function would maintain the same order). Therefore, the difference could be the simplicity since a linear neuron is easily implementable in a VLSI circuit, as an example, rather than a log-sigmoidal. Does this mean that log-sigmoidal can be replaced in any case? I think that probably no, since back-propagation training could be performed easily when a log-sigmoidal function is used so that training is performed with log-sigmoidal but for the final application, a linear one replaces this function.

While drawing the layouts in VLSI, we use layers like HVT (High threshold voltage layer) and LVT (Low threshold voltage layer). How are they fabricated?

The main functional block of a microprocessors is the ALU (Arithmetic and Logic Unit) because of its involvement in all computing activities. The important tasks of ALU are arithmetic and logical operations. Speed of the microprocessor mainly depends on ALU’s performance. Most of the processors are included with stand alone design for arithmetic operations. In very large-scale integrated circuits (VLSI), ALUs with various bit-widths are required to perform operations efficiently.

Papers:

S.M. Swamynathan, V. Banumathi “Design and Analysis of FPGA Based 32 Bit ALU Using Reversible Gates,” International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE2017), 2017.

Mohammed F. Tolba, Ahmed H. Madian and Ahmed G. Radwan “FPGA realization of ALU for mobile GPU,” 3rd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA), 978-1-4673-8523-7/16/31.00, IEEE, 2016.

This is a question without a single answer, since there are many variables and dependencies here which are impossible to pin down, and will change according to design parameters, technology generation/features, logic/circuit design methodologies and capabilities, and (very importantly) the design of the memory hierarchy, and the workload(s) under consideration. Even the basic metrics (power, and performance) are subject to much discussion: how should one trade off power vs performance to make a "fair" comparison? Nonetheless, it would be interesting to hear folks' opinions and analysis on this topic. To start things off, let's assume that you need to meet a certain ("relatively high") performance level, measured as performance per thread in a multi-core/multi-threaded microprocessor, but you are also subject to a per-thread power constraint (typical of today's high-performance processors). Obviously, the deeper the pipeline, the higher the operating frequency. Or, frequency can be traded off for power, by lowering the operating voltage. However, lowering the design FO4 and deepening the pipeline will impact the power-performance of the design in a variety of ways:

1) Number of flops in the design increases, driving up power, especially power used for clocking. Also, the delay overhead of the flop and any clock uncertainty takes a relatively larger bite out of the cycle time.

2) "Design difficulty" increases since logic has to be divided more finely to achieve the higher cycle time. Also increased timing/device modeling accuracy is called for. Tighter signal slews will be required, and number of repeaters/buffers will increase.

3) CPI will increase, since miss penalties (measured in numbers of cycles) will increase. Also, in light of #2, the design may be pushed towards a simpler microarchitecture.

4) There may be many other costs, depending on the design, ranging from SER impacts, power/current density issues, cache design issues, etc.

I'll start by suggesting that, given where most commercial designs seem to be landing, that 10FO4 is probably well below the ideal cycle time (despite considerable literature which might suggest otherwise). Also, something like 50FO4 is probably too high. Comments anyone?

Hi All,

It is well known that Hardware Trojans known so far actually have knowledge of the algorithm and use side channel analysis to leak the keys. To prevent side channel analysis, logic obfuscation techniques are used. I just wanna know that "is there a side channel analysis known in literature which reveals the entire algorithm or IP core or HDL code?"

Thanks in advance.

A monostable circuit can be typically implemented using an EXOR Gate with delayed pulse train as inputs. This way we can generate very sharp pulses at the Leading edge and trailing edge of the leading input pulse. The output can be ANDed with either of the input Square wave to generate only the Leading edge /Trailing Edge pulse as required........

But am envisaging the implementation of ONLY Leading edge pulse without any extra circuitry such as AND gate.

Can anybody suggest!!

Thanks in Advance.

Muralidhar.M

I want to plot Transfer curve for NMOS Depletion load inverter using Cadence virtuoso tool, for that from where i can get depletion mode NMOS?

i have GPDK 45, 90 and 180nm and using Cadence virtuoso tool .

DFT related projects which can include ATPG,Scan chain technics etc.

See above

as i am searching for research problem in the combination of these two technologies.

i am working on VLSI inetrconnects and need to calculate the the crosstalk overshoot and undershoot for capacitively coupled lines using the output waveform in tanner software.for overshoot there is rising signal on aggressor and static 1 on victim. we get spikes at the output of victim line. this is crosstalk-noise. plz tell how to calculate crosstalk-noise peak and duration.

In VLSI design software such as cadence how can we calculate the delay between two different outputs and delay between input and output?

I am looking for the microchannel's most important applications between:

- Micro-electronic Thermal Management

- Solar Collectors

- Space Machines Cooling

- Drilling Devices

and etc ...

What are the available tools for spintronic device simulation?

VLSI research:

Shall i use Tanner ? What will be your recommendations.

I need to vary the transistor dimensions.

Many work in VLSI area, it is mentioned about iso-area concept. What it meant by?

Thanks in advance

Need to publish the research work in indexed VLSI journals. May I know the list. Can any one guide me.

I would like to have some knowledge sharing on power budget estimation at top level.

Basically as a block level pd engineer I have been given a power budget(say 200mW) and allowable drop threshold (say 6%). I have some rough idea on how do they arrive it, but how do they freeze those values early in the design flow for a block at top level? It would be helpful if you can share some knowledge on this.

To implement the FIR filter using VLSI techniques, we need to map the difference equation to block level representation which include delay, adder and multiplier as prime blocks, are these block a floating point operation or fixed point operation blocks. how do we optimise these blocks. is there any method to convert a floating point number to a fixed point number.

Leakage power in low power VLSI.

Any one 

I'm doing my research in VLSI floor planning. I wanted the source code for VLSI floor planning optimisation in MATLAB. 

Also, if possible the MATLAB code has to process MCNC benchmark circuits

Can any one help me with this ?

At present how many logic gates are required for half adder and full adder which consists of only AOI ( AND, OR and NOT) gates only? As i know, for full adder is required 6 AND gate,3 OR gate and 4 NOT gate. Any circuit less than 13 AOI logic gates?

our project( comes under vlsi hardware security) aims to detect trojans by measuring current signature of a process corner in different time windows for same set of state transitions..thus if a trojan is present an anomaly would be found.  we need a tool to measure this current signature.

Consider a Filter design (DSP system block), what are the different methods to implement, test and design the same. Effectiveness of such a block is determined by what all parameters ?

HI

I just found an bootstrapped sample/hold circuit from a text book. I have simulated the same. I need to calculate SNR, SNDR and ENOB for the same

Input at 5MHz, sampled at 100MHz

How can I do that on cadence?

With referring to the topic below

I have been trying to design compressors using MUX instead of XOR's. The method I tried to infer a MUX instead of XOR is using a case statement to sum up two signals. But after synthesizing the design, I found no difference in the later and the former designs (former one being with XOR's). Also, I found that in many research article, their delays differ from mine to a discernible extent. Added to it, Later I found out that some people had different results for different voltages at which the system was ran. How is this possible? What should I further do to reduce the delay of the system?

VLSI system design