VHDL Programming - Science topic

Here is a useful link that I found, with the block diagrams and Verilog codes

Dear Abdurrahman Zai̇m ,

The paper in the link contains complete FPGA design and implementation on Xilinix VIRTIX 6 development board:

This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.

There is even higher performance chips than Virtex 6 such as Verix 7.

as far as I know, there are no such tools around

Please try by applying behavioural and structural type code format, After that this basic knowledge for solving the counters and other higher level applications.

CMOS MIXED CIRCUIT DESIGN -BAKER-WILEY.

For VHDL, there is GHDL : http://ghdl.free.fr

Arnaud

There are two very different aspects in this question.

1st: Comparison with respect to the target implementation

2nd: Similarity of languages with respect to their syntax

Some thoughts on the 1st aspect:

Target system for C programming is a processor-based computer. Target system for a hardware description language (HDL) is a digital circuit (either an ASIC or an FPGA/PLD).

But there have been made several approaches to use C for targeting digital circuits (e.g. HandelC, C-to-Hardware from Altium, SystemC, Xilinx HLS and other). By "nature" C is able to model combinational circuits without any problem but lacks the ability to perform clocked processes. Latter has been solved by SystemC libraries for example. With regard to combinational logic you have to detach yourself from the idea that the C-description will be performed in a step-by-step sequence consuming machine cycles. Like in a VHDL "process", which describes combinational logic, a piece of C-code has a sequential "order" but not a "sequential" timing then! Apart from the aspect that also combinational logic takes it's time (in magnitudes of pico- and nanoseconds) a combinational logic expressed by a sequential order inside of a VHDL-process, has an idealized delay time of zero!

Conclusion for the 1st aspect: Yes, C can easily be used to model combinational logic in a sequential order. It depends on the tools you have if you can make a useful digital circuit out of it.

Some thoughts on the 2nd aspect:

I'm not very familiar with Verilog. Therefore I might be wrong in some details.

Verilog's syntax is somehow C-like. VHDL syntax has been derived from the programming language ADA.

VHDL has the possibility to express combinational and sequential logic by means of processes. The entirety of all processes inside a VHDL module will run in parallel (true parallelism). The process can be conditioned to perform continuously (combinational logic) or in time steps (clocked sequential logic). In either case the VHDL-code inside of a process is evaluated in the sequential order as it is written, but in idealized delay time of zero (see above). Delay time in the combinational mode means reaction on change of any input, in clocked mode delay time is related to the active clock edge.

The programming style inside of VHDL processes is very similar to higher software programming languages.

Kind regards

Peter

JPG format is too intricate, coding hardware to handle it is not trivial. If this is an undergrad project, you are shooting too high.

There is however a middle-ground solution. Use a softcore (e.g. microblaze) and a memory, those two fully coded in vhdl/verilog. Then write software that runs on the softcore and that software will do the actual work of parsing and understanding the JPG format.

Most IoT applications require a processor core, memory, networking chip (BLE/WiFi/Zigbee etc.) and a controller to actuate external devices. The processor core in IoT can be replaced by FPGA. FPGA could be coupled with an ARM processor to leverage higher-level software functions such as Web servers, if higher level of processing is required. For more information of FPGA in IoT, read the following article: “Sensor Systems Based on FPGAs and Their Applications: A Survey”.

Xilinx has a lot of information about image processing, but you may try to send binary images via serial port in matlab, using a serial port modeled in VHDL (a lot of them in internet) and store them in a memory (xilinx and altera, both have models to do it) xor-them and send them back to matlab.  Al you need is a little state machine to control all the elements. P.S.You can also avoid using memory.   

This amounts to information fusion, where the fusion is carried out on one of two levels:

The kind of fusion depends on your access to the detector outputs and signals at each array. Detector outputs generally require low data rates. The signals generally require high data rates. if you have free and easy access to all possible information at each array, then either approach can be used.

Contact fusion (1) is usually much easier to implement, using an AND or an OR rule for the detector outputs for instance.  Note however that you must generally readjust the detection sensitivity of the detector at each array when their outputs are fused into a single detector. Otherwise you risk making the detection performance of the  fused output worse than the detection performance of each array detector working independently.

Note that you may have target association problems: How do you know that the signals at each array come from the same target? The signals at each array must be associated with each other, so that any detection processing across both arrays is always (usually) detection of the same target. This can be very problematic in multi-target and cluttered signals.

Ronald

Xilinx System Generator and DSP builder.

By AccelDSP Synthesis Tool

On-line learning in the said project is about learning on the go. Whenever there is a new situation the neural (network) will improve its knowledge by learning the additional knowledge to handle a new situation. Offline is more about static where a model is trained in the start with all the possible/available situations of the environment and then it is deployed. 

In other words, post-deployment need-based (re)training of model during its lifetime, as the new situations arise, is termed as on-line training. The aim is to make a model adopt autonomously to cope with such cases. 

Aparna Murthy, This is really helpful. Thank you.

I do not understand what you mean by a 6:2 mux, however, the best way to do this is making a case statement on the select vector. In the case for every valid combination of you select assign the needed input bits to your output

process (sel)

begin

case sel is

when "000" =>

dout_1 <= din_1;

dout_2 <= din_2;

when "001" =>

dout_1 <= din_3;

dout_2 <= din_4;

when "010" =>

dout_1 <= din_5;

dout_2 <= din_6;

end case;

end process;

You cannot use "if" without "process" - try "when" instead!

z <= '0' when a = 1 else '1';

In this case, whether you use "process" + "if" or just "when" makes no difference.

BUT when you use processes, the code within the process works only when a signal in the process' sencitivity list changes value.

You can find a thorough example here: 

For example you have a number  36.25+j24.58. here If you are using 32-bit system then, 36.25 you have to represent in 32-bit and 24.58 in 32-bit (in total 64-bit). Again in 32-bit use 16-bit for 36 and 16-bit for 0.25

That's the 'trick' with the 2's complement format: adding of negative values is easily done. Regarding subtraction, it is just about getting the 2's complement of the subtrahend and adding :)

Regards

I have no idea

Please refer the attached code for full adder using half adder using Port Mapping. Let me know if you any query in the same.  

Hi, well the buffer will add some noise (maybe around 0.5dB at worst), but you can characterize the LNA's NF with and without buffer, since your next stage is usually a downconversion mixer and not a 50 Ohm load.

Thank you very much

Please provide complete files. Without package and signal declarations  I cannot say anything.

You feedback the output signals to input side through registers.

You can visit to "http://www.ecircuitcenter.com/".

Dear Ravikumar,

I need information about, how to write HDL code, to compare images. For example, i need to compare two 512x512 image, If i compared pixel by pixel with its value, how to do? or any other tool do this simple manner?  

You have to be careful when implementing reductions like this one. Your code is probably extensive but correct.

While your approach implies the parallel reduction which has log(n) time complexity,the approach proposed by M. Ali Cavuslu implies a structure with linear time complexity equal to n, where n is the number of inputs.

This is demonstrated on the attached schematics of the resulting circuit structures obtained using Xilinx Vivado. It may depend on a particular synthesis tool, but tree reduction (your code) always guarantee to achieve best possible performance (i.e. timing). In your case, the circuit consists of  three levels while Cavuslu's code implies a structure requiring five levels.

If you want a generic approach, you have to write a generic tree reduction algorithm. Probably the simplest code might look like:

function max_tree_reduction(a, b, c ,d ,e ,f: std_logic_vector)

return std_logic_vector is 

   type my_type is array(0 to 5) of std_logic_vector(a'range);

   variable tmp: my_type;

   variable i,j : integer;

  tmp := (a,b,c,d,e,f);

  for lvl in 0 to tmp'right/2 loop -- should be log2(tmp'right)

      for itm in 0 to tmp'right loop

           i := 2**(lvl+1) * itm;

           j := i + 2**lvl;

           next when ((i > tmp'right) or (j > tmp'right));

           if (tmp(j) > tmp(i)) then

               tmp(i) := tmp(j);

    return tmp(0);

end max_tree_reduction;

Dear Ashwini Kumar,

Check for repeatability of the measurement and reproduction at different rates of change of the gate bias. The Id-Vg curves of organic TFTs usually have peculiar behaviors. Compare to observations in

C. Feng, O. Marinov, M. J. Deen, P. Selvaganapathy, Y. Wu, "Sensitivity of the Threshold Voltage of Organic Thin-Film Transistors to Light and Water", Journal of Applied Physics, 117(18), 185501-1 to -9, 2015;  DOI:http://dx.doi.org/10.1063/1.4919829

Your response formula is valid at condition for reproducible static characteristics without temporal variations. If so, and as Mentioned by Maarten Swanenbrg, you have to find change dVT of threshold voltage induced by the gas, then to find the charge induced by the gas as dVT*Cox, and then to relate this charge sheet concentration to volume concentration of the gas. Note the other detail mentioned by Maarten Swanenbrg, that your formula should give different values at different gate biases.

However, all the above is valid at quasi-equilibrium, both "electrical" and "chemical". Thus, check the repeatability and reproduction of the measurements. There are some guidelines in the reference above to evaluate differential sensitivity when the static equilibrium is not present.

Sincerely,

Dr. O. Marinov 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec24 is

port(

a : in STD_LOGIC_VECTOR (1 downto 0);

E : in STD_LOGIC;

d : out STD_LOGIC_VECTOR(3 downto 0)

);

end dec24;

architecture behavioral of dec24 is

begin

process (a)

begin

case a is

when "00"=> d<="0001";

when "01"=> d<="0010";

when "10"=> d<="0100";

when others=> d<="1000";

end case;

end process;

end behavioral;

see these

file:///C:/Documents%20and%20Settings/home/My%20Documents/Downloads/White%20Paper%20for%20Low%20Density%20Parity%20Check%20(LDPC)%20Codes%20(1).pdf

I researched this problem in the article "The failure risk analysis of digital circuits".

I found this book useful:

Fundamentals of Digital Logic with Verilog Design

by: Stephen Brown and Zvonko Vranesic

The major points for Blue-Spec is

1. Designer can save time (almost 40% of time you can save)

2. Module integration is easy and control signal handling has been taken by Blue-Spec tool itself

3. After completing the design you will get a 70-80 % verified code

4. The synthesized frequency is almost same for the VHDL and Blue-Spec designs

6. Blue-Spec support team is very good. 

As far as I remember there is a paper that covers how to obtain the netlist from the bitstream: "From the bitstream to the netlist"  by Jean-Baptiste Note and Éric Rannaud (http://dl.acm.org/citation.cfm?id=1344729) or https://www.researchgate.net/publication/200065272_From_the_bitstream_to_the_netlist

Another paper is "BIL: A tool-chain for bitstream reverse-engineering" by Florian Benz et al. (http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6339165). You can get the open source of the project in the following URL: https://github.com/florianbenz/bil/

Hope this helps

The question is pretty vague ("very large" is subjective), but I'm assuming based on the "RSA Cryptography" tag that you mean 1024 to 8192 bits and are interested in good probable prime tests rather than proofs.  Quick answer for RSA: multiple Miller-Rabin tests with random bases followed by a single strong Lucas test, using the FIPS 186-4 tables to decide how many to use.  Quick answer for non-RSA: BPSW for non-proofs, APR-CL or ECPP for proofs.

Typically we first add a pretest looking for small factors, as this returns very quickly for composites.  This can be done by trial division or a big gcd, for example.

Easiest:  multiple Miller-Rabin tests with random bases.  See FIPS 186-4 for a suggested number of tests for given sizes and security levels, if this is for cryptographic use.  There are deterministic base sets for 64-bit numbers.

Better: Add a Lucas test, preferably the strong test.  This is anti-correlated to the M-R tests, and runs in about the speed of 2 M-R tests, so gives better results in practice.  FIPS 186-4 also gives numbers for how many M-R tests to run in combination with a Lucas test.   For non-crypto work, a single base-2 M-R test plus a strong Lucas test makes the BPSW primality test, which is quite popular for general probable prime testing.  It runs quickly, is deterministic, is shown correct for all 64-bit numbers, and even the weakest variants have no known counterexamples for larger inputs (though we expect them to exist).

For primality proofs, there are various methods for special input forms that are fast, such as the Lucas-Lehmer test for Mersenne numbers.  For tiny 64-bit numbers we can just use BPSW.  For somewhat larger numbers, the BLS75 methods work well if you have integer factoring code.  APR-CL and ECPP are recommended methods for large inputs, with ECPP having done a few numbers in the 18k to 25k digit range.  ECPP generates a certificate, unlike APR-CL or AKS.  AKS is far too slow to be useful at any size.

Dear Pierre,

CAD tools such as Quartus-II by Altera or Xilinx IDE support conversion in both directions. You can find a free versions of these tools on the manufacturer's web-pages. For instance,

Hi Sumathi Gokulanathan,

Let me first tell you the simple procedure of using the Xilinx XPower Analyzer (for understanding) and then some information on that.

Implement the top module using the Xilinx ISE

Open the XPower Analyzer listed in the Place and Route tab of the Design sub window

After the design gets loaded 100%, in the 'Report Navigator' sub window of the XPower Analyzer, click on the 'By Clock Domain' listed in the 'Details' tab.

A list of the clock signals and the clock driven synchronous signals appears in the window pane, by the side if the 'Report Navigator'.

If your design uses clock, change the value of the Frequency of the clock, in the concerned field. (The default value given is 0 MHz)

After changing the clock frequency to the desired value, click on the 'Update Power Analysis' icon in the Toolbar.

After the update gets finished, click on the summary, listed in the 'Report Navigator', to get the updated power values.

NOTE: To measure the power values at different frequencies, restart the XPower Analyzer to get correct values. If you change the frequency many times at a single run, the power values get added up as the algorithm (according to my knowledge) preserves the previous values of power to add them in calculating the power values of next frequency.

All the best,

Regards

NP.

Hi

the descreption of algorithm Cordic implemented by the logic element as Adder and substractor divice.

 http://airccj.org/CSCP/vol2/csit2243.pdf 

this file for the shifting regiter 

Internet of Things is an application domain for semiconductors. Microprocessors, microcontrollers, DSP, analog ICs, RFICs, ... all of these will be employed in an IoT application. So, a simple answer to your question is, yes - companies have a large number of solutions for IoT.  Example - Feel free to look at the CC3000 series of semiconductors - http://www.ti.com/product/cc3000

Port map is only used for physical signals and while process is a virtual operations that use variables which requires zero time to execute ( concurrent statements)

solution is

we can divide any bit random number by using Box muller technique.

As far as know there are no proved solutions yet to perform ab initio calculation. It is not an easy task since it needs accurate analog knowledge of the circuit and its digital activity. But of course it can be estimated: you may proceed performing accurate analog simulations on your digital gates to estimate power consumption per glitch and how it depend on loading capacitance. If possible make analog montecarlo simulations to estimate average values. Once you know average power consumption per glitch, you should estimate the rate of glitches per second on the specific circuit by providing custom or random stimuli in digital simulation of the concrete circuit.

MicroBlaze is a soft processor that gets implemented in the FPGA fabric. You can implement as many MicroBlaze cores as you can in every Xilinx FPGA.

In the Spartan3 200 you only have 4300 logic cells, which will be just enough for one core plus some peripherals but not more.

The Microblaze reference Guide is the UG081:

Hope that will help you.

Regards

Olivier

I second Nicholas commend. VHDL has both fixed- and floating-point types for synthesis since the 2008 revision. You can download the relevant packages from here: http://www.eda.org/fphdl/ . They are also available as a free download since 2013 from the IEEE themselves (search for machine readable codes for IEEE 1076-2008).

You do not need to write "(NOT(x1(0)))". Just check whether " x1(0) = '0'; "

You could use something like:

if (s(0) = c(0) and x1(0) = '0') then

I:= (others => '0');

end if;

Hi..

There is no such a tool to convert matlab code into VHDL code.. Eventhough, if it is, it will produce inefficient code.. not all the matlab generated VHDL codes are efficient. its better to try it in vhdl itself, instead of conversion.

Let's assume your algorithm is right

(http://en.wikipedia.org/wiki/Miller%E2%80%93Rabin_primality_test)

That is, you've got the one you've implemented in VHDL working in one of Scilab, Matlab, Octave, Python, C/C++, etc.. Now use that to generate input/output golden"test vectors" for different parts of your VHDL model. Usually I try and skip this part, but invariably when using an HDL like VHDL, I need to come back and "test" the intermediate values produced by the high-level language model against the HDL model I'm trying to get to work.

Given that, then you are trying to debug your VHDL implementation.

If by "functions" above, you mean VHDL functions, please understand their limitations.

They are not like C/C++ functions, and are a fairly advanced concept in the VHDL scheme of things. Look at http://www.eda.org/fphdl/ for examples of functions that are also synthesizable(I'm assuming that you want your VHDL model to be synthesizable, but are currently stuck on getting the simulation (perhaps using the ModelSim simulator) working correctly.

I'd recommend that if you are looking for speed from your VHDL model that you use the Entity-Architecture Register Transfer Level(RTL) methodology to design your parallel components, Embrace the clock, pipelining and their semantics, as that is is where your parallel speed will come from. I only use functions and procedures as semantic sugar until I'm comfortable that my basic design works with memory, logic, pipe lining, and clocks.

alan

If you are using Altera, there is a tool named SignalTap - it can be embedded on the same FPGA and can serve you as a logic analyzer that can help you see internal signals that are not I/Os. In Xilinx there is a tool named ChipScope that serves the same purpose. You should check with your product version which tool is suitable for you. Also, if you have a testbench and are using ModelSim, then you can delve in the internal signals no matter that they are not inputs or outputs of the top module. I do not remember quite well, but maybe the same thing is possible with the Xilinx's ISim as well.

Good luck!

You can achieve m x n multiplications by adding m , n times. That is what this circuit doing.

check this great resource for all FPGA projects, they have various image\video processing projects

or maybe you prefer to shift to matlab hdl coder (check key features) http://www.mathworks.es/products/hdl-coder/

There are two problems with USB cameras when you try to connect them to FPGAs:

- you need an USB IP (hardware driver): you have to be an expert to develop your own IP, alternatively you can buy a commercial IP but they are expensive.

- once your FPGA receives the USB packets you have to extract the image data, but usually there is no information about how the data are packaged. You need to do inverse engineering to find the data structure.

A realistic way is to use a soft-micro or hard-micro, integrated in the FPGA, able to support a OS like Linux. There are several reference designs where webcam is connected to Zynq devices (zedboard and microzed).

Good luck

This is really important for me, so please contribute to this question with useful and straight forward answer

Power can be measured by measuring the voltage drop of a shunt (low value) resistor in series with the voltage source of the FPGA. Some commercial kits provide a jumper in the power supply to allow inserting a current mesurement circuit (like an amperimeter). You can also find kits that include the power mesurement circuit on board (like Terasic DE4).

If you are using a kit that has not these features you could cut the power line in the PCB to build a similar thing yourself. I wouldn't do it, but I know people that have done it.

Then, you have indirect techniques, like implementing ring oscillators on the FPGA and measure their oscillating frequency. The oscillating frequency depends on temperature, and temperature depends of thermal power dissipation, so I think you could build up an empirical model to get some power estimation with this technique.

E Boemo, et al "Thermal monitoring on FPGAs using ring-oscillators"

I guess it would not be very accurate, though

You need Xilinx system generator support in your Matlab toolbox. Then only it is quite easy to design in simulink & convert to vhdl code completely. Refer:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_3/sysgen_gs.pdf for more details.

Otherwise, target support packages based code conversion is possible but one cannot expect everything is taken care by the software tool itself. It depends on your design problem. Steps to convert it into vhdl in this mode is available in help menu.

As the other members have commented, the coding language should be the least of your worries. You have to work on getting the implementation into the code. If I were to pick a language for any design, I would go with VHDL, since it is quite structured and the debugger can catch some errors which you may not see in simulation. Verilog on the other hand, is awesome for testbenches.

I solved my problem, thanks to all