Science topic

VHDL - Science topic

Explore the latest questions and answers in VHDL, and find VHDL experts.
Questions related to VHDL
  • asked a question related to VHDL
Question
4 answers
According to the number of Input and outputs ports of the FPGA chip we have, can we add (implement) any number of ethernet (100base) RJ45 and Fibre LC connector to the FPGA? What is the way to do that?
Also how can I also implement the following protocol into the FPGA; DNP3 , GOOSE and MODBUS?
which tools or libraries are using for these protocols on FPGA?
and what is best affordable cheap FPGA development board to buy with Ethernet Rj45 and Fibre LC connector SFP
Relevant answer
Answer
The paper in the link contains complete FPGA design and implementation on Xilinix VIRTIX 6 development board:
This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.
There is even higher performance chips than Virtex 6 such as Verix 7.
  • asked a question related to VHDL
Question
11 answers
Dear Researchers,
does any one have ever used AccelFPGA compiler to generate VHDL codes from MATLAB codes, please?
I appreciate your responses
Relevant answer
Answer
I agree with the idea by Dr Abdelhalim abdelnaby Zekry , I did the same sometimes back and it worked perfectly well.
  • asked a question related to VHDL
Question
4 answers
In my research, i need to incorporate exact dot product accumulator in verilog or VHDL to perform accumulation of 32-bit IEEE 754 floating point multiplication output...total 15 multipliers are there...
Relevant answer
Answer
You can implement the accumulation process sequentially as the accumulator used in the arithmetic logic unit in the central processing unit.
You can also process them in parallel by using 16 full adders followed by 8 full adders followed 4 , then followed by two then followed by the final accumulator.
Then you will need five stages. So, in this implementation the time will be reduced to five periods instead of 32 periods for the single accumulator.
There may be more higher speed implementation that may cost more hardware but less time!
Best wishes
  • asked a question related to VHDL
Question
1 answer
Field programmable gate arrays (FPGAs) have been constantly used for embedded systems in various applications, such as inverters, medical appliances, etc. The reverse engineering in the FPGA is a way of re-configurating the netlist inside the FPGA in various ways. There are some known tools such as Debit, BIL, and Bit2ncd that could be especially used for Xilinx products. However, these are still under developmental phase. Are there more such products available for stable use? What if non-Xilinx products such as from Intel Altera FPGA's are adopted for use?
Relevant answer
Answer
as far as I know, there are no such tools around
  • asked a question related to VHDL
Question
3 answers
RSA Cryptography
Relevant answer
Primality Test Formula
We can determinate if one number is prime with the modulo operation.
  • asked a question related to VHDL
Question
3 answers
In bist(built-in-self-test) how to calculate the known good signature pattern which is used to compare with test pattern result . I am designing bist implementation for multiplier circuit using cbilbo registers in VHDL. Please help me any one .
Relevant answer
Answer
i generated signature by using LFSR as misr and prpg. Now I want to compare it with known good signature .So I wanted to know how to calculate known good signature
  • asked a question related to VHDL
Question
9 answers
Hello Friends,
Am developing flight control system completely in VHDL. for PID implementation, i have developed algorithm in arduino and tested for single axis, it works fine. while tuning Kd,Kp,Ki values, it responds accordingly. the same algorithm i developed in VHDL. i used modelsim for simulation. but after inserting into FPGA keeping all other setup same, while testing it is not functioning as expected. while increasing Kd value, instead of reduce oscillation, it increases oscillation. i have checked orientation of motors and other hardware. everything fine. am not sure where am missing. requesting suggestions.
Thanks
edit: Thank you for your valuable replies. Based on all of your inputs, currently am checking step by step, comparing arduino output with FPGA output. I have one doubt to clear. arduino gives PWM signal with 5V output which is connected to Simonk ESC to drive BLDC motor.But FPGA gives gives 3.3V PWM output. will it be the problem? need i put 3.3V to 5V logic level shifter, to give control input to ESC?
Relevant answer
Answer
Perhaps you can duplicate the input to both Arduino and FPGA and compare the output..
  • asked a question related to VHDL
Question
3 answers
I started my program by writing subprograms as functions in VHDL. Then I have tested them separately, and all of those subprograms worked fine. Fortunately, when I combined them and started my primality testing, I found that my program was performing well, but for certain number, the program began to output all the results as composite. I was just wondering what problems might cause this bug. By the way, my program was designed to be 32-bit primality testing. However, the program work fine until I test the numbers above 46399. Then all prime and composite numbers outputted the same result as "composite". This really confused me. Please, need your help.
Relevant answer
Primality test and easy factorization
This is an algorithm that test if one number is prime and if the number it´s not prime returns the biggest factor of that number.
  • asked a question related to VHDL
Question
8 answers
High-end APIs of python, Tensorflow and Keras dramatically reduce the time and effort put into experimenting and deploying DL/ML models for various tasks. but I can't seem to find a High- level framework that quickly implements these algorithms on FPGAs.
What is the reason behind this? Is there any framework which helps me quickly experiment on FPGA?
Relevant answer
As a design platform you can use Simulink/matalb. You can design the system in Simulink building blocks and the you can compile it into VHDL using the XILINIX SYSTEM GENERATOR.
As an example we designed the the acquisition and tracking phases of the GPS receivers on FPGA using such suite.
For details please follow the link:
and the link:
Best wishes
  • asked a question related to VHDL
Question
6 answers
FPGA boards can be used to implement signal processing algorithms. However, SVD needs many matrix multiplications and inversions. Can it be implemented using FPGA libraries or VHDL code or it is difficult?
Relevant answer
Dear Mohamed,
In addition to the colleagues, conceptually every computation algorithm that you implement it using a general purpose computing machine based on microprocessors can be implemented using FPGA as a computing platform with much higher speed because the implementation on FPGA is hardware implementation rather than software implementation on a single processor.
This is from the basic point of view. So, one can use FPGA for real time implementation of the singular value decomposition where one can exploit the high speed and the larger size of the advanced PFPGA chips.
I would like to read the paper in the link:
Best wishes
  • asked a question related to VHDL
Question
3 answers
I have a hardware IP written in Verilog that I synthesized using Design Compiler for a given technology. The IP is basically an ALU, and I want to measure the power consumption or energy values associated with each operation performed inside the ALU (addition, multiplication, ...).
So I did a post-synthesis simulation on the synthesized design and I fed that into PrimeTime (PrimePower) in order to take in consideration the node acitivities. At the end I get reports showing power consumption. What I need is actually to get a graph representing the power consumtion vs. time, as shown in the attached example.
Is this possible in PrimePower? or should I use some other tool? Any ideas?
Thanks.
Relevant answer
Answer
you can use Mentor Graphics ..tanner eda tool
  • asked a question related to VHDL
Question
4 answers
This question belongs to electronics field. FPGA stands for field programmable gate array. Researcher who has done his PhD in Electronics and has interest area in the field of VLSI and VHDL can easily guide me.
Relevant answer
Dear Zainab,
Every FPGA chip is composed of look up tables, Flip Flops, Memory block ram all implemented in CMOS technology. From the principle point of view all the logic functions can be thought to be build of CMOS transistors and pass transistor logic.
I could not understand what do mean by floating. The meaning of electrically floating means that it is not grounded. This is not true for the internal CMOS logic. Inverter based logic is not floating. The output is referenced also to ground.
I would like that you refer to the data sheet of XILINIX SPARTAN 6: https://www.xilinx.com/support/documentation/data_sheets/ds160.pdf
Best wishes
  • asked a question related to VHDL
Question
5 answers
Hi experts,
I have been tasked with programming in VHDL this kind of robot. A kind of vacumm cleaner robot (ie roomba) that will be able to avoid collisions and move in another direction when needed. I'd appreciate your help guys, as always.
Thanks in advance
Regards,
Alejandro
Relevant answer
Answer
thanks all. I have somethign in mind but I am struggling with the VHDL code. Enclosed is a state machine draft I created. Any ideas?
  • asked a question related to VHDL
Question
4 answers
With all the hype about high-level synthesis tools, I am interested to know how much do you use HLS in actual commercial projects compared to traditional Verilog/VHDL flows? Is HLS still marginal or is it a competitive option?
Relevant answer
Answer
Hi,
Regarding this matter, you could start checking about HLS, in order to gain better knowledge about its potentials. I hope that the following works hill help you in that:
  • asked a question related to VHDL
Question
13 answers
Hello Everyone,
I started learning VHDL and FPGA Programming. I have watched tutorials regarding this, but that were just basic concepts.
Can someone please suggest me some good books for that?
I shall be very thankful for that.
Thank you!
Relevant answer
Answer
Interesting -following .
  • asked a question related to VHDL
Question
19 answers
Which HDL programming language is considered to be better that the other form the industrial point of view and not form the academic one? and why?
Relevant answer
You will get a comparison between the two languages.
The two languages are use equally well in academia and industry environment. Every language is supported by their FPGA chip makers.
Best wishes
  • asked a question related to VHDL
Question
3 answers
I am looking for the optimized methodology that can do the max operation which is applicable in VHDL
Relevant answer
Answer
Sorry, i guess i solved this issue.
  • asked a question related to VHDL
Question
15 answers
Today we are aware of VHDL and Verilog. What about the HDLs before these. Please help in compiling a history. It would be better if we discuss critically merits and demerits of those HDLs including VHDL and Verilog.
Relevant answer
Answer
There are so many HDLs before and after the invention of Verilog and VHDL. I will focus in the past of HDLs, because it is much easier to check newer versions of HDLs or even HVLs (Hardware Verification Languages). Some useful links and references for sharing the history of HDLs would be:
5) "Fundamentals and Standards in Hardware Description Languages", by Mermet, J., Springer, 1993
  • asked a question related to VHDL
Question
3 answers
I have already learnt Verilog HDL. Please suggest a book that will be easier for VHDL.
Relevant answer
Answer
Hi,
Use the following link to search on available books related to VHDL:
  • asked a question related to VHDL
Question
6 answers
VHDL and verilog are both hardware description languages. They are different in syntax. If you are targetting VHDL only, I think, you might be having some advantages of VHDL on Verilog in your mind. Please educate, if there are some reasons of choosing VHDL only?
Relevant answer
Answer
@johannes hiltscher
You are right. For a beginner, i would also recommend VHDL.
  • asked a question related to VHDL
Question
3 answers
I want jpg to bmp converter module in my vhdl project.
How can i write this? and where should i started?
Relevant answer
Answer
JPG format is too intricate, coding hardware to handle it is not trivial. If this is an undergrad project, you are shooting too high.
There is however a middle-ground solution. Use a softcore (e.g. microblaze) and a memory, those two fully coded in vhdl/verilog. Then write software that runs on the softcore and that software will do the actual work of parsing and understanding the JPG format.
  • asked a question related to VHDL
Question
9 answers
Anyone know how to get a GDS ii files from a VHDL file using Synopsys tools ?
I mean the steps, and it is preferable to be using the GUI not commands
Relevant answer
Answer
Check your installation folder. Look for /doc or similar. In my installation folder the path is ICC/doc/syn/html/
It is confidential, sharing it here would not be legal.
  • asked a question related to VHDL
Question
7 answers
How to VHDL IMPLEMENTATION of Unipolar, RZ, AMI, NRZ and other line coding scheme using modelsim
Relevant answer
Answer
Thanks a lot
  • asked a question related to VHDL
Question
4 answers
Hello and good time
I want to call Benchmark Circuits to VHDL and Verlog format in MATLAB, I wanted to know how to link these formats to MATLAB and how to do it.
The link below shows the Benchmark circuits in different formats.
Relevant answer
Answer
Following
  • asked a question related to VHDL
Question
6 answers
Dear all
what is the best way to find Throughput of Transceiver design using FPGA and VHDL CODE????
I have see many way in different paper but which one is the best and simple way??????
thanks
Relevant answer
Answer
Dear Aparna Sathya Murthy
I think you are right in the real life to find throughput but in case of simulation FPGA using Spatan 3E the method depend on the maximum operating frequency which can be used to calculate the throughput
thanks you
  • asked a question related to VHDL
Question
4 answers
Hi dear , I need one Algoritm for implemantion Am demodulator via FPGA AND VHDL code . tnx for help me
Relevant answer
Meisam,
Yes you need an algorithm describing the steps of AM demodulation.
One algorithm according to the modem theory may be as follows:
For synchronous demodulator, you have to regenerate the carrier from the demodulated signal by a phase looked loop, then multiply this regenerated carrier by the modulated signal by the regenerated carrier after shifting it by 90 degree. The output of the multiplier must be low pass filtered to extract the base band signal. The cut off frequency of the low pass filter must be equal to the highest frequency in the base band or the modulating signal.
Since you process your signal digitally you have to convert to into suitable digital form using A/D converter as said by John.
There is other less complex algorithm but which are not synchronous.
As an example:
You can sample your am modulated signal by a sampling frequency with double the bandwidth. Then you low pass filter it as before to extract the base band.
You need to consult the books of the digital communications for more information. For example digital communications for Glover and Grant.
Best wishes
  • asked a question related to VHDL
Question
12 answers
Relevant answer
Answer
Most IoT applications require a processor core, memory, networking chip (BLE/WiFi/Zigbee etc.) and a controller to actuate external devices. The processor core in IoT can be replaced by FPGA. FPGA could be coupled with an ARM processor to leverage higher-level software functions such as Web servers, if higher level of processing is required. For more information of FPGA in IoT, read the following article: “Sensor Systems Based on FPGAs and Their Applications: A Survey”.
  • asked a question related to VHDL
Question
7 answers
Verilog or VHDL
Relevant answer
Answer
Actually, I have the same trouble as yours. such source like xilinx or Intel FPGA are used their Macro, and it is difficult to modify. Now I am preparing the RTL by myself
  • asked a question related to VHDL
Question
9 answers
I'm working with images and so,the input data is a text file obtained from Matlab .The text file has binary data (convert form image ... 256x256x8).I tried to read the data from the file into a 2D array. The data has to be in the form of a matrix (2D array),as I need to perform block processing on it. how can i divide the 2D matrix into block.
Relevant answer
Answer
You can convert data into single column in matlab itself, then you can read that text file in VHDL, after capturing the data into VHDL environment you can convert into 2D data set. I have attached all supporting files. This may help you...
  • asked a question related to VHDL
Question
4 answers
Hi dear
i need help if any one can help me
I have design SRRC polyphase filter using VHDL with choose roll off = 0. 5 , it work as i have attache figure but when I have fixed roll off =0.55 or 0.6 or 0.4 it not work
any one please can help me to design SRRC filter using VHDL
Thanks
Relevant answer
Answer
I have implemented used fixed point
  • asked a question related to VHDL
Question
2 answers
my program is reading and writing text file or image in vhdl/quartus prime, but i have problem in reading text file. when i read the text, the reading delayed by on clock and the writing also delayed by another clock so as result the output delayed by two clock.
how can i solve this problem?
Relevant answer
Answer
Thanks for your fast responding
I increase the grid size to 10 ns, but the problem still the same.
  • asked a question related to VHDL
Question
4 answers
Dear
I want to convert build matlab function to VHDL ?
notes: matlab code is build in matlab as function
Relevant answer
Answer
You can convert the code by using the HDLCoder in Matlab
  • asked a question related to VHDL
Question
4 answers
any one can tell me how to solve this error...
code and simulation is OK and output of simulation is ok without any error but when i try to implemented the design the error come to me(open attached file)
Relevant answer
Answer
thanks to all
I have found the problem after 14 days search for it
It was a license issue because i have last version of VHDL simulation(2017 version) and it need full license to implemented new technology like 5G .
Finally i have get
thanks thanks
  • asked a question related to VHDL
Question
9 answers
I want to download a free VHDL simulator to implement image encryption . what is the best simulator for VHDL ?
Relevant answer
Answer
It depends on your circuit. If the circuit is simple, such as the one in classroom, the waveform fashion may be easy to use; otherwise, if the circuit is complex, a professional simulator may be proper, such as ModelSim.
  • asked a question related to VHDL
Question
7 answers
can i convert matlab code directly to VHDL? using Xilinx or ALTERA FPGA System 
Relevant answer
Answer
I've only used Xilinx FPGA, so my answer will cover just Xilinx technologies:
Yes, you can convert directly. As Krishna stated, Simulink has its own HDL coder (a C coder is also available). But I believe the most appropiate tool for your question is Xilinx System Generator. Unfortunately is only included in some suites of Vivado (WebPack does not include it) and needs a specific version of MATLAB; usually a range of versions is given for it.
  • asked a question related to VHDL
Question
6 answers
I designed a 16 bit multiplier using 4-2 compressor and adder. I wrote the verilog test bench code in Xilinx to verify the functionality. My simulation runs quite long time also I am unware of the total simulation time. Can some one suggest me how long it takes for completing the test bench simulation since it takes the combination of 2 power 16. Thanks in advance.
Relevant answer
Answer
Before starting, I'd like to say that there is nothing as fuzzy and ambigious as 'quite' in engineering. Define quite; hours, days, weeks?
I also see that question as an erroneous one. The run time depends on so many factors other than your RTL, testbench and input vectors. And you want other people to make an estimation for you? 
A better approach would be changing your testing style. I think you don't necessarily have to exhaust every single input combination. You can define which input vectors might be more critical and then set your testbench accordingly. The criticality will depend on the type of multiplier you implement.
Lastly, if you want to roughly estimate how long it might take for you to run an exhaustive simulation, you can try running multiple simulations with various number of input vector scenarios. Thereon, you can roughly extrapolate the amount of time needed for your simulation.
  • asked a question related to VHDL
Question
3 answers
Thank you sir. I use only simulation tool ie. Isim. From simulation waveform one clock cycle was 20ns but i find that during synthesis xilinx gives timing summary as Minimum period: 6.842ns (Maximum Frequency: 146.149MHz).  There is a contradiction of which one to use to calculate latency.
Relevant answer
Answer
Behavioral simulation can be performed at the frequency you prefer, simulation results are good even if you use the clock at  2 GHz.
During synthesis, the tool performs a first estimation of the maximum clock frequency (the best estimation is the one after the place & Route). These estimations show you the maximum frequency you can use in your design that is completely unrelated with behavioral simulation. If you wanna simulate the system considering also the latency introduced by propagation time of clb and interconnect you must perform a Post P&R simulation
  • asked a question related to VHDL
Question
13 answers
to enhance an image matrix, it is to be multiplied with another matrix. this is to syntheized
Relevant answer
Answer
When you use hdl languages you are describing Hardware. So  you could not think about the code but first about the circuit you want to implement and after you can use the code to implement that circuit
  • asked a question related to VHDL
Question
2 answers
Text file (LUT) Input/Output to FPGA Virtex 6 (ML605 board) 
I have an ML605 evaluation kit (Virtex 6 FPGA). I want to do the following: 
-Store/copy (binary) data from .txt file in BRAM (or preferably an external memory on the board).
-Read that data from BRAM, that will input for our module (e.g. input_1 and input_2).
-Store/write the output of module (e.g. sum) in BRAM.
-Export that data to .txt or any other file format from where we can fetch the binary values.
Relevant answer
Answer
Dear Wissam Marouche,
1. Do you have a processor in your design? If yes you can connect to a serial port (usb) to your system. In this way your processor cen receive/transmit data and read/write to BRAM with the processor.
2. Using JTAG I suppose you can do paratial reconfiguration and in this way you can change the BRAM contents.
Regards,
Jozsef Vasarhelyi
  • asked a question related to VHDL
Question
3 answers
Grid connected Five level H Bridge Invert er
Relevant answer
Answer
Mithun, 
Spend some time on Google Scholar looking at published work in the area. You will get the help you need to move forward. Your question is very specific, which means this may be a project you have been assigned to. It is unlikely that someone will provide the exact help you are looking for. There are many aspects to your project, such as PLL, VHDL, and Grid-connected inverter. You will find books and online tutorials on all these topics. It is up to you to apply the knowledge and carry out the project. 
Best wishes
  • asked a question related to VHDL
Question
3 answers
In Xpower 7.1i, when I calculated power of a 2-input AND gate, it gave me the total power as 120mW. For a 32bit carry skip adder, it is 124mW, which is totally wrong in my opinion as a 32 bit adder will have many transistors when compared to AND gate. What might be the problem in this. Can anyone, suggest me the correct way of calculating power in Xpower from Xilinx ISE 7.1i
Relevant answer
Answer
power consumed in individual circuit cant be calculated in xilinx it always gives power consumed  by whole chip . better to go for full custom design in order to get optimum power consumption result
thanks
  • asked a question related to VHDL
Question
5 answers
I need to learn VHDL code for pulse generation using FPGA. Thanks in advance!
Relevant answer
Answer
For learning VHDL Bhasker and D Perry both are good to start. Pulse generation on FPGA you can use any hardware Description language like Verilog or VHDL.
These languages are easier then c but one should have complete understanding for the design that you are going to implement.
  • asked a question related to VHDL
Question
3 answers
Attached is a hexadecimal multiplication table.If I look closely,I see the numbers in unit places or decimal places are following a pattern(sometime obscure) ,a 'period of oscillation' kind of thing.Can anyone please explain why this is happening and whether it may help me to remember this table?
Relevant answer
Answer
OK - this is the 101 in hex. No real need to remember if you are fit in dividing in mind: convert hex to decimal, multiply and convert back to hex: dividing by 16 gives the tens, the remainder the last digit. Do the transcoding for any value > 9 and you are ready.
The only thing to be memorized (if you prefer) the decimal values for the letters.
To be honest: I'm 29 years in the software business - still using a calculator for these things (most of the time). Some calculations are easy - these you will memorize over time. The remaining ones: calculator.
Regards
  • asked a question related to VHDL
Question
17 answers
Hi,
A part of my project in Signal Processing is to generate a sine signal with the cordic algorithm in VHDL and put the VHDL Code on a board and test it. Do somebody have an idea for a VHDL code example?
Thanks a lot
  • asked a question related to VHDL
Question
2 answers
RSA Cryptography
  • asked a question related to VHDL
Question
7 answers
What is the best pseudo random number generator (PRNG) for designing RSA cryptosystems. I need it in simulating my program in ModelSim + Quartus. However, if you know how to use the built-in command in VHDL it would be appreciated. Even if it works with only 32-bit.
Relevant answer
Answer
For more details please see following book
  • asked a question related to VHDL
Question
5 answers
i am working on project of FPGA based model predictive controller.
Relevant answer
Answer
by AccelDSP Synthesis Tool
  • asked a question related to VHDL
Question
5 answers
Basically, exactly what the question says. Which program of Orcad do I need to implement VHDL in my circuit?
  • asked a question related to VHDL
Question
7 answers
I tried one simple 4 tap FIR filter implementing on Nexys-4 board. The designed was directly based on the block architecture of a trasposed form 4 tap FIR. Using Vivado i got the simulation correctly but the on the FPGA I am not getting the correct results. What could be the reasons?
  • asked a question related to VHDL
Question
6 answers
Hi everybody,
I would like to perform a hardware implementation on FPGA of LDCP decoding algorithm. if you have any documents or papers (I prefer thesis or any axpanded documents) about this area.
Thanks to you.
Relevant answer
Answer
thanks
  • asked a question related to VHDL
Question
4 answers
Hi, 
I'm used to use global variable in Matlab. 
Right now, i'm having issues with VHDL when using variables. I want something which lets me use variables declared in packages within the main program. 
Thank you. 
Relevant answer
Answer
  • asked a question related to VHDL
Question
5 answers
I am working towards the robust mapping of a hardware piece to a DSP FPGA. I have developed a C program to obtain the inverse of a 4x4 matrix using the QR decomposition technique. my next step is to port the C program to VHDL using 16 bit fixed point arithmetic (Qn.m) format. Can any one be of assistance to me?
Relevant answer
Answer
You can use vendor specific IP blocks from Xilinx or Altera i think both support 16 bit fixed point. Otherwise there is a synthesizble  library with fixed and floating point types in vhdl. You can see the float and fixed types that you can use if you look source file fixed_float_types.vhdl in the standard ieee library folder from Modelsim
  • asked a question related to VHDL
Question
3 answers
HI
I just found an bootstrapped sample/hold circuit from a text book. I have simulated the same. I need to calculate SNR, SNDR and ENOB for the same
Input at 5MHz, sampled at 100MHz
How can I do that on cadence?
Relevant answer
Answer
Dear Anush,
I would like to add to  the Vladimir answer, that the error due to sampling is considered as a noise and distortion. To be more clear the sample and hold circuit outputs at a sampling time instant  nTs a value y(nTs) while the inpu is x(nTs) . As clear from you waveform the two values are different. They are only approximately equal.
So, the noise and distortion is the difference y(nTs) )=y(nTs) - x(nTs) ,
So building a difference time sequence extending a number of complete cycles of the input wave form can be used to evaluate the noise and distortion simply by by squaring and averaging the difference function along the observation time T=MTs.
That is N+D= sum y(nTs) ^2 over all Msamples /M,
The signal to noise and distortion can be determined by dividing the signal power to the noise and distortion power as defined by the above equation. That is,
SNAD RATIO=  sum x(nTs) ^2 over Msamples/M / N+D,
In order to separate the noise from distortion you need only to transform the output sampled sequence to frequency domain using the discrete fourier transform or the fast Fourier transform. The input tone and its harmonics will be apparent in this domain in addition to the noise floor. One can then determine the mean square value of the fundamental and the mean square value of the harmonies and the  mean square value of the noise floor. One can get also the spurious free difference
which represents the ENOB. However, the effective number of bits has only meaning for a complete A/D converter.
Wish you success
  • asked a question related to VHDL
Question
7 answers
I am trying to Implement the design to detect the pulse and according to that measure the frequency of that signal. But I am just in learning phase of VHDL coding, So I am having trouble in this. Any answers related to the topic are Welcomed. Thank you.
Relevant answer
Answer
Aparna Murthy, This is really helpful. Thank you.
  • asked a question related to VHDL
Question
1 answer
I'm using 6:2 multiplier in my project. I know about 2:1 mux but i don't have any idea about 6:2 mux. so can any one help me for this?
Relevant answer
Answer
I do not understand what you mean by a 6:2 mux, however, the best way to do this is making a case statement on the select vector. In the case for every valid combination of you select assign the needed input bits to your output
process (sel)
begin
case sel is
when "000" =>
dout_1 <= din_1;
dout_2 <= din_2;
when "001" =>
dout_1 <= din_3;
dout_2 <= din_4;
when "010" =>
dout_1 <= din_5;
dout_2 <= din_6;
end case;
end process;
  • asked a question related to VHDL
Question
4 answers
I would like to enter the field of heterogenous computing and would like to do simulations with different architectures. I know that one can make some VHDL code and run a test bench to see how that kind of simulation works, but I would like to know what other tools, researchers are using today? Maybe to simulate things like power, time delays etc. I also have seen instances where FPGA's are used for quickly emulating processor architectures, but I would like to know further. 
Update/Edit: I am specifically looking for opensource or free tools (ex: Modelsim free version) .
Relevant answer
Answer
I am new to this field and I am finding there are some C++ based tools like GEM 5, GARNET, RSIM etc which are used
  • asked a question related to VHDL
Question
5 answers
Dear Researchers,
I need some material such as Books, Articles and so on for how can I write the image processing using VHDL?
I know how can I convert code but I need some material to write image processing using VHDL by own.
Thanks
Relevant answer
Answer
Dear researcher
please refer to this attachment if it is helpful for you.
  • asked a question related to VHDL
Question
5 answers
If implementation of the basic modular addition, multiplication or exponentiation is done from scratch (eg. implementation of Carry Save adders or Montgomery's multiplier), one might not be sure of its efficiency in terms of throughput or area of chip. One the other hand, if standard packages exist, then it would be a lot easier to implement.
Relevant answer
Answer
Depending on what you want to achieve with an efficient hardware architecture in terms of resource utilization, speed, power, etc., you should first divide and conquer the whole crypto algorithm into the sub-modules and write HDL code for each sub-module. As far as I know, there is no existing library in VHDL which supports crypto primitives (possible sub-modules). You may check OpenCores http://opencores.org/ website where you can find some HDL code that may help you. I highly suggest you to read these papers [1,2] in which they show you an efficient way to implement a crypto algorithm in FPGA. 
[1] At, Nuray, et al. "A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function Grøstl." IACR Cryptology ePrint Archive 2012 (2012): 535. https://eprint.iacr.org/2012/535.pdf
[2] At, Nuray, et al. "Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 2, pp. 485-498, Feb. 2014.
  • asked a question related to VHDL
Question
17 answers
Sir,
I have written the image transformation code in matlab now i like to convert it into VHDL coding , is there any possibility to convert the image related coding into  VHDL. if so pl. guide me 
Relevant answer
Answer
Hi,
From matlab code to VHDL conversion you must follow some steps:
1) If your matlab code is floating point code the must convert in to the fixed point code. because FPGA needs the fixed point code. by using the fixed-point converter MATLAB Apps, during this conversion u must focus on the fractional length and word length.these two are very important parameters.
2) Then used HDL coder APPs on the fixed point matlab code to generate the HDL code.
If u have further confusion ask me....i used lots in my projects....
  • asked a question related to VHDL
Question
7 answers
i have a block in vhdl that produces an output of 8 bits (from 00 to FF) 00 represents value of -.125 and FF represents value of .125 
i want to add this value for another block as duty cycle step however the block has 16 bit duty values where 0000 represents 0 and FFFF represents 1
how can i interface both blocks 
Relevant answer
Answer
That's the 'trick' with the 2's complement format: adding of negative values is easily done. Regarding subtraction, it is just about getting the 2's complement of the subtrahend and adding :)
Regards
  • asked a question related to VHDL
Question
2 answers
I have a data for a material including its n(refractive index) and k(extinction coefficient) values in an .xslx file. I need SILVACO to pick those nk values while it is simulating. But when i try to use this file in SILVACO it says that "Error: Read error in index file Optical_Properties_Of_InP.xlsx. Check format."
Any help.
Relevant answer
Answer
I have no idea
  • asked a question related to VHDL
Question
6 answers
Hi, Can some one please help out.Thanks. I am trying to convert below code to VHDL using HDL Coder but getting error. The HDL Coder Block file is also attached .Please can you have a look on it and see whats the mistake in block diagram.
x1=[1 2 3 4 5 6 7 8 9];
x2=[3 4 5 6 7 8 9 2 1];
n=length(x1);
xc=zeros(2*n-1,1);
for i=1:2*n-1
if(i>n)
j1=1;
k1=2*n-i;
j2=i-n+1;
k2=n;
else
j1=n-i+1;
k1=n;
j2=1;
k2=i;
end
xc(i)=sum(conj(x1(j1:k1)).*x2(j2:k2));
end
xc=flipud(xc);
Error:
Cannot connect to model 'prc4'; please try Update Diagram (Ctrl-D).
Error due to multiple causes.
Errors occurred during parsing of MATLAB function 'MATLAB Function'(#24)
Error in port widths or dimensions. Output port 1 of 'prc4/MATLAB Function/u' is a one dimensional vector with 1 elements.
Can some please help me out what could be the reason of this error.
Relevant answer
Answer
From my best knowledge and experienced, you must have a test bench in order to verify your code.
  • asked a question related to VHDL
Question
10 answers
Dear all,
  I have designed my circuit in VHDL in Xilinx tool.Can any one help in Area and Delay analysis of the design please.How to do?what is the procedure?
Relevant answer
Answer
First of all you have to run "Synthesis" and "Implementation". After that, you will see what resources your design needs to be implemented in "Design Summary".
You have to look at the Post-PAR (Place and Route) Report, this is where ISE explains whether the timing constraints of your design are met, what the critical path of your design is and up to what clock frequency your design can run! It will also let you know of how many slices, FF, IOBs have been used etc. 
Keep in mind that the numbers you get after Synthesis are only ISE's estimations - only PAR (part of "Implementation") results in accurate numbers!
  • asked a question related to VHDL
Question
2 answers
I tried to estimate total variable space (T) for i-vector estimation, in speaker recognition, but if i select the factor number to more than 100 it gave wrong results but with 100 or less it provided good result. So how to decide that we need as much number of factor (t dimension) for total variablity space? 
Relevant answer
Answer
@Hamid: Thanks, (otherwise I was always using 512 Gauss and 400 TV space. Although I don't have the access to NIST database, I just need to test with smallar databases, so atleast I can have running system. 
  • asked a question related to VHDL
Question
3 answers
i have worked on small program on VHDL but have problem in designing 64 bit pipeline FFT processor in VHDL. Can anybody give me help on this design as coding?
Relevant answer
Answer
Thanks for valuable information Melnyk Anatoliy and sayed
  • asked a question related to VHDL
Question
5 answers
Today’s students, more than ever, often find course-based learning to be boring and meaningless.
In PBL, students are active, not passive; a project engages their hearts and minds, and provides real-world relevance for learning.
After completing a project, students remember what they learn and retain it longer than is often the case with traditional instruction.
 Because of this, students who gain content knowledge with PBL are better able to apply what they know and can do to new situations.
What do you think about established this type of center in your country?
Relevant answer
Answer
in IRAN, I established this type of research and training center in field of Engineering and training students to improve student's research factors. for more information please follow this link
  • asked a question related to VHDL
Question
4 answers
I am trying to design a Wallace tree using VHDL programing in Xilinx 13.4 software. I have completed my structural type VHDL programing. When we implement this programing on XILINX 13.4 design suit software then we saw the RTL view and there is no error in programing. But in this programing we used half adder and full adder as a PORTMAP. In XILINX 13.4 design suit software this half adder and full adder is not added so we not get the simulation result (Wave form).
Relevant answer
Answer
Please refer the attached code for full adder using half adder using Port Mapping. Let me know if you any query in the same.  
  • asked a question related to VHDL
Question
11 answers
I didn't find a lot articles with making artificial neural network on FPGA, only just reviews. So my question: is it possible? If it is - is it hard? why there is a few articles about it - may be it is too easy?
thank you for responces
Relevant answer
Answer
Not only it is possible, but probably using FPGAs for ANNs is the best way because of their extremely high level of parallelism which may outperform any MCU/DSP on the market.
I vote for what was recommended by Mohamad Hanif Md Saad - he pointed to a valuable resources.
Regards.
  • asked a question related to VHDL
Question
4 answers
VHDl code for UART is somewhat lengthy using state machine ,so i am thinking to implement it without state machine .is it best??
Relevant answer
Answer
State diagrams have always been the easiest way to implement all sequential problems and so is the one.
  • asked a question related to VHDL
Question
3 answers
I have decimal numbers ( lets say 8.432, 5.256 etc) in my MATLAB as input for arithmetic operations ,I convert my code to vhdl using HDL Coder. The data type i chose for input and output blocks in Simulink is int32. The code is converted to vhdl but when I see the binary output I only have the non decimal part i.e 8 and 5 in above example .How I could get the binary output for the decimal part too.May be  its simple question but being very new in this field dnt know how to do this.
Relevant answer
Answer
You can try to use the data type fixdt if this type is available. Two years ago i generate some HDL code with the HDL-Coder and i use this type.For example, with fixdt(0,16,0)  you can create a register which represents a 16bit In- or Output. Maybe this would help you with your problem. 
  • asked a question related to VHDL
Question
5 answers
sir, I am trying to do following -
I am giving a signal x(t) as input which has 1000 samples.(i have taken one signal and samples it using the matlab and got the points in form of integars)
Now i have extracted the local maxima and minima of that signal.
By using local maxima i have calculated the upper envelope by using linear interpolation and same i have done with local minima to calculate the lower envelope and then i have taken the average of the upper and lower envelope and have got a signal m(t)
now i have to calculate a new signal h(t) which will be
h(t) = x(t) - m(t)
I have to repeat all above three times, means now again h(t) will be the input signal,
x(t) = h(t)
How to repeat the steps? I have written the code separately for each step. Should i use FSm? If i am going to use FSMs then how can i instantiate the modules in FSMs? Please suggest. I ma in big trouble
Relevant answer
The best way to solve your problem is using Mealy FSMachines, becouse the change of the state depends of the imput values. In this case the imput values (true/false) can be the convergence criterion and the termination criterion.
  • asked a question related to VHDL
Question
6 answers
I am developing a kit where i have generated a square wave of 4mhz but i am not able to fig out how to vary the on time of signal as i want to calculate duty cycle of signal
Relevant answer
Answer
Hello Omkar
In VHDL, you can easily generate square waves with almost any duty cycle feeding the output of a counter into a comparator. The only limiting factor is the maximal frequency of your logic circuit.
By using clocking circuits integrated into the FPGA, as @Sivanandam_Kaliannan suggest, you can achieve even higher frequencies.
Cheers
  • asked a question related to VHDL
Question
10 answers
I want to implement a neural network in the Sum of Products form and thus have chosen the VHDL coding approach instead of the MATLAB VHDL Coder. Can someone help me with using decimal values in VHDL and subsequently, FPGA?
Relevant answer
Answer
You can convert your inputs and all values to binary and implement your system with binary values. You can use (dec2bin(x)) in MATLAB to convert values to binary. I implemented a large neural network on an FPGA using binary numbers. 
  • asked a question related to VHDL
Question
11 answers
For control of power electronic conversion processes employing Spartan-3A dsp, will it be better to lean vhdl coding or will it be better if I learn how to use system generator. I have generated more that 15 PWM signals as I am working on multi-phase system.
Relevant answer
Answer
Dear Mohammad Ali,
In my opinion, it is better to learn Verilog or VHDL. You would have more efficient system if you design it yourself. Both of them are easy to learn.
  • asked a question related to VHDL
Question
10 answers
HI,
Good Day to all...
In digital design, i want to insert control logic or lock mechanism at internal nets. As far as i know, inserting control logic or lock mechanism at High fan-out nets is the best solution in which less no. of locks will have controllability on more no. of internal nodes.
I want to know is there any other net (means any other digital parameter to decide in which net i can insert) if i insert will impact more no. of logic, especially my concern is to increase controllability of output ports. But, fan-in will not help me for this purpose i hope...
Thank you in advance....
Regards,
SUMATHI G.
Relevant answer
Answer
In my view, capacitance and resistance parameter of the net also play major role in digital design. So, you may think about RC value in you design
  • asked a question related to VHDL
Question
4 answers
I need to compare received image with stored image using FPGA kit. For that need HDL coding.How can code to compare two images in HDL. Any other way is available to compare images?
Relevant answer
Answer
Dear Ravikumar,
I need information about, how to write HDL code, to compare images. For example, i need to compare two 512x512 image, If i compared pixel by pixel with its value, how to do? or any other tool do this simple manner?  
  • asked a question related to VHDL
Question
4 answers
I want to measure the frequency of ring oscillator circuit I inserted in my design. I made circuit schematic using xilinx ISE. During behavioral simulation, my circuit is switching its output, but I could not see its waveform. Hence I could not measure its delay i.e. frequency.
When I select the mode of simulation as post-route, it shows my design is not yet instantiated (question mark near design), when I try to instantiate, its not doing so. Finally I could not measure ring oscillator frequency.
Relevant answer
Answer
The following page might be helpful