Science topic

# VHDL - Science topic

Explore the latest questions and answers in VHDL, and find VHDL experts.

Questions related to VHDL

According to the number of Input and outputs ports of the FPGA chip we have, can we add (implement) any number of ethernet (100base) RJ45 and Fibre LC connector to the FPGA? What is the way to do that?

Also how can I also implement the following protocol into the FPGA; DNP3 , GOOSE and MODBUS?

which tools or libraries are using for these protocols on FPGA?

and what is best affordable cheap FPGA development board to buy with Ethernet Rj45 and Fibre LC connector SFP

Dear Researchers,

does any one have ever used AccelFPGA compiler to generate VHDL codes from MATLAB codes, please?

I appreciate your responses

In my research, i need to incorporate exact dot product accumulator in verilog or VHDL to perform accumulation of 32-bit IEEE 754 floating point multiplication output...total 15 multipliers are there...

Field programmable gate arrays (FPGAs) have been constantly used for embedded systems in various applications, such as inverters, medical appliances, etc. The reverse engineering in the FPGA is a way of re-configurating the netlist inside the FPGA in various ways. There are some known tools such as Debit, BIL, and Bit2ncd that could be especially used for Xilinx products. However, these are still under developmental phase. Are there more such products available for stable use? What if non-Xilinx products such as from Intel Altera FPGA's are adopted for use?

In bist(built-in-self-test) how to calculate the known good signature pattern which is used to compare with test pattern result . I am designing bist implementation for multiplier circuit using cbilbo registers in VHDL. Please help me any one .

Hello Friends,

Am developing flight control system completely in VHDL. for PID implementation, i have developed algorithm in arduino and tested for single axis, it works fine. while tuning Kd,Kp,Ki values, it responds accordingly. the same algorithm i developed in VHDL. i used modelsim for simulation. but after inserting into FPGA keeping all other setup same, while testing it is not functioning as expected. while increasing Kd value, instead of reduce oscillation, it increases oscillation. i have checked orientation of motors and other hardware. everything fine. am not sure where am missing. requesting suggestions.

Thanks

edit: Thank you for your valuable replies. Based on all of your inputs, currently am checking step by step, comparing arduino output with FPGA output. I have one doubt to clear. arduino gives PWM signal with 5V output which is connected to Simonk ESC to drive BLDC motor.But FPGA gives gives 3.3V PWM output. will it be the problem? need i put 3.3V to 5V logic level shifter, to give control input to ESC?

I started my program by writing subprograms as functions in VHDL. Then I have tested them separately, and all of those subprograms worked fine. Fortunately, when I combined them and started my primality testing, I found that my program was performing well, but for certain number, the program began to output all the results as composite. I was just wondering what problems might cause this bug. By the way, my program was designed to be 32-bit primality testing. However, the program work fine until I test the numbers above 46399. Then all prime and composite numbers outputted the same result as "composite". This really confused me. Please, need your help.

High-end APIs of python, Tensorflow and Keras dramatically reduce the time and effort put into experimenting and deploying DL/ML models for various tasks. but I can't seem to find a High- level framework that quickly implements these algorithms on FPGAs.

What is the reason behind this? Is there any framework which helps me quickly experiment on FPGA?

FPGA boards can be used to implement signal processing algorithms. However, SVD needs many matrix multiplications and inversions. Can it be implemented using FPGA libraries or VHDL code or it is difficult?

I have a hardware IP written in Verilog that I synthesized using Design Compiler for a given technology. The IP is basically an ALU, and I want to measure the power consumption or energy values associated with each operation performed inside the ALU (addition, multiplication, ...).

So I did a post-synthesis simulation on the synthesized design and I fed that into PrimeTime (PrimePower) in order to take in consideration the node acitivities. At the end I get reports showing power consumption. What I need is actually to get a graph representing the power consumtion vs. time, as shown in the attached example.

Is this possible in PrimePower? or should I use some other tool? Any ideas?

Thanks.

This question belongs to electronics field. FPGA stands for field programmable gate array. Researcher who has done his PhD in Electronics and has interest area in the field of VLSI and VHDL can easily guide me.

Hi experts,

I have been tasked with programming in VHDL this kind of robot. A kind of vacumm cleaner robot (ie roomba) that will be able to avoid collisions and move in another direction when needed. I'd appreciate your help guys, as always.

Thanks in advance

Regards,

Alejandro

With all the hype about high-level synthesis tools, I am interested to know how much do you use HLS in actual commercial projects compared to traditional Verilog/VHDL flows? Is HLS still marginal or is it a competitive option?

Hello Everyone,

I started learning VHDL and FPGA Programming. I have watched tutorials regarding this, but that were just basic concepts.

Can someone please suggest me some good books for that?

I shall be very thankful for that.

Thank you!

Which HDL programming language is considered to be better that the other form the industrial point of view and not form the academic one? and why?

I am looking for the optimized methodology that can do the max operation which is applicable in VHDL

Today we are aware of VHDL and Verilog. What about the HDLs before these. Please help in compiling a history. It would be better if we discuss critically merits and demerits of those HDLs including VHDL and Verilog.

I have already learnt Verilog HDL. Please suggest a book that will be easier for VHDL.

VHDL and verilog are both hardware description languages. They are different in syntax. If you are targetting VHDL only, I think, you might be having some advantages of VHDL on Verilog in your mind. Please educate, if there are some reasons of choosing VHDL only?

I want jpg to bmp converter module in my vhdl project.

How can i write this? and where should i started?

Anyone know how to get a GDS ii files from a VHDL file using Synopsys tools ?

I mean the steps, and it is preferable to be using the GUI not commands

How to VHDL IMPLEMENTATION of Unipolar, RZ, AMI, NRZ and other line coding scheme using modelsim

Hello and good time

I want to call Benchmark Circuits to VHDL and Verlog format in MATLAB, I wanted to know how to link these formats to MATLAB and how to do it.

The link below shows the Benchmark circuits in different formats.

Dear all

what is the best way to find Throughput of Transceiver design using FPGA and VHDL CODE????

I have see many way in different paper but which one is the best and simple way??????

thanks

Hi dear , I need one Algoritm for implemantion Am demodulator via FPGA AND VHDL code . tnx for help me

I came across this idea via this blogsite

I'm working with images and so,the input data is a
text file obtained from Matlab .The text file has binary data (convert form image ... 256x256x8).I tried to read the data from the file into a 2D array. The data has to be in the form of a matrix (2D array),as I need to perform block processing on it. how can i divide the 2D matrix into block.

Hi dear

i need help if any one can help me

I have design SRRC polyphase filter using VHDL with choose roll off = 0. 5 , it work as i have attache figure but when I have fixed roll off =0.55 or 0.6 or 0.4 it not work

any one please can help me to design SRRC filter using VHDL

Thanks

my program is reading and writing text file or image in vhdl/quartus prime, but i have problem in reading text file. when i read the text, the reading delayed by on clock and the writing also delayed by another clock so as result the output delayed by two clock.

how can i solve this problem?

Dear

I want to convert build matlab function to VHDL ?

notes: matlab code is build in matlab as function

any one can tell me how to solve this error...

code and simulation is OK and output of simulation is ok without any error but when i try to implemented the design the error come to me(open attached file)

I want to download a free VHDL simulator to implement image encryption . what is the best simulator for VHDL ?

can i convert matlab code directly to VHDL? using Xilinx or ALTERA FPGA System

I designed a 16 bit multiplier using 4-2 compressor and adder. I wrote the verilog test bench code in Xilinx to verify the functionality. My simulation runs quite long time also I am unware of the total simulation time. Can some one suggest me how long it takes for completing the test bench simulation since it takes the combination of 2 power 16. Thanks in advance.

Thank you sir. I use only simulation tool ie. Isim. From simulation waveform one clock cycle was 20ns but i find that during synthesis xilinx gives timing summary as Minimum period: 6.842ns (Maximum Frequency: 146.149MHz). There is a contradiction of which one to use to calculate latency.

to enhance an image matrix, it is to be multiplied with another matrix. this is to syntheized

**Text file (LUT) Input/Output to FPGA Virtex 6 (ML605 board)**

I have an ML605 evaluation kit (Virtex 6 FPGA). I want to do the following:

-Store/copy (binary) data from .txt file in BRAM (or preferably an external memory on the board).

-Read that data from BRAM, that will input for our module (e.g. input_1 and input_2).

-Store/write the output of module (e.g. sum) in BRAM.

-Export that data to .txt or any other file format from where we can fetch the binary values.

Grid connected Five level H Bridge Invert er

In Xpower 7.1i, when I calculated power of a 2-input AND gate, it gave me the total power as 120mW. For a 32bit carry skip adder, it is 124mW, which is totally wrong in my opinion as a 32 bit adder will have many transistors when compared to AND gate. What might be the problem in this. Can anyone, suggest me the correct way of calculating power in Xpower from Xilinx ISE 7.1i

I need to learn VHDL code for pulse generation using FPGA. Thanks in advance!

Attached is a hexadecimal multiplication table.If I look closely,I see the numbers in unit places or decimal places are following a pattern(sometime obscure) ,a 'period of oscillation' kind of thing.Can anyone please explain why this is happening and whether it may help me to remember this table?

Hi,

A part of my project in Signal Processing is to generate a sine signal with the cordic algorithm in VHDL and put the VHDL Code on a board and test it. Do somebody have an idea for a VHDL code example?

Thanks a lot

What is the best pseudo random number generator (PRNG) for designing RSA cryptosystems. I need it in simulating my program in ModelSim + Quartus. However, if you know how to use the built-in command in VHDL it would be appreciated. Even if it works with only 32-bit.

i am working on project of FPGA based model predictive controller.

Basically, exactly what the question says. Which program of Orcad do I need to implement VHDL in my circuit?

I tried one simple 4 tap FIR filter implementing on Nexys-4 board. The designed was directly based on the block architecture of a trasposed form 4 tap FIR. Using Vivado i got the simulation correctly but the on the FPGA I am not getting the correct results. What could be the reasons?

Hi everybody,

I would like to perform a hardware implementation on FPGA of LDCP decoding algorithm. if you have any documents or papers (I prefer thesis or any axpanded documents) about this area.

Thanks to you.

Hi,

I'm used to use global variable in Matlab.

Right now, i'm having issues with VHDL when using variables. I want something which lets me use variables declared in packages within the main program.

Thank you.

I am working towards the robust mapping of a hardware piece to a DSP FPGA. I have developed a C program to obtain the inverse of a 4x4 matrix using the QR decomposition technique. my next step is to port the C program to VHDL using 16 bit fixed point arithmetic (Qn.m) format. Can any one be of assistance to me?

HI

I just found an bootstrapped sample/hold circuit from a text book. I have simulated the same. I need to calculate SNR, SNDR and ENOB for the same

Input at 5MHz, sampled at 100MHz

How can I do that on cadence?

I am trying to Implement the design to detect the pulse and according to that measure the frequency of that signal. But I am just in learning phase of VHDL coding, So I am having trouble in this. Any answers related to the topic are Welcomed. Thank you.

I'm using 6:2 multiplier in my project. I know about 2:1 mux but i don't have any idea about 6:2 mux. so can any one help me for this?

I would like to enter the field of heterogenous computing and would like to do simulations with different architectures. I know that one can make some VHDL code and run a test bench to see how that kind of simulation works, but I would like to know what other tools, researchers are using today? Maybe to simulate things like power, time delays etc. I also have seen instances where FPGA's are used for quickly emulating processor architectures, but I would like to know further.

*Update/Edit*: I am specifically looking for opensource or free tools (ex: Modelsim free version) .

Dear Researchers,

I need some material such as Books, Articles and so on for how can I write the image processing using VHDL?

I know how can I convert code but I need some material to write image processing using VHDL by own.

Thanks

If implementation of the basic modular addition, multiplication or exponentiation is done from scratch (eg. implementation of Carry Save adders or Montgomery's multiplier), one might not be sure of its efficiency in terms of throughput or area of chip. One the other hand, if standard packages exist, then it would be a lot easier to implement.

Sir,

I have written the image transformation code in matlab now i like to convert it into VHDL coding , is there any possibility to convert the image related coding into VHDL. if so pl. guide me

i have a block in vhdl that produces an output of 8 bits (from 00 to FF) 00 represents value of -.125 and FF represents value of .125

i want to add this value for another block as duty cycle step however the block has 16 bit duty values where 0000 represents 0 and FFFF represents 1

how can i interface both blocks

I have a data for a material including its n(refractive index) and k(extinction coefficient) values in an .xslx file. I need SILVACO to pick those nk values while it is simulating. But when i try to use this file in SILVACO it says that "Error: Read error in index file Optical_Properties_Of_InP.xlsx. Check format."

Any help.

Hi, Can some one please help out.Thanks. I am trying to convert below code to VHDL using HDL Coder but getting error. The HDL Coder Block file is also attached .Please can you have a look on it and see whats the mistake in block diagram.

x1=[1 2 3 4 5 6 7 8 9];

x2=[3 4 5 6 7 8 9 2 1];

n=length(x1);

xc=zeros(2*n-1,1);

for i=1:2*n-1

if(i>n)

j1=1;

k1=2*n-i;

j2=i-n+1;

k2=n;

else

j1=n-i+1;

k1=n;

j2=1;

k2=i;

end

xc(i)=sum(conj(x1(j1:k1)).*x2(j2:k2));

end

xc=flipud(xc);

Error:

Cannot connect to model 'prc4'; please try Update Diagram (Ctrl-D).

Error due to multiple causes.

Errors occurred during parsing of MATLAB function 'MATLAB Function'(#24)

Error in port widths or dimensions. Output port 1 of 'prc4/MATLAB Function/u' is a one dimensional vector with 1 elements.

Can some please help me out what could be the reason of this error.

Dear all,

I have designed my circuit in VHDL in Xilinx tool.Can any one help in Area and Delay analysis of the design please.How to do?what is the procedure?

I tried to estimate total variable space (T) for i-vector estimation, in speaker recognition, but if i select the factor number to more than 100 it gave wrong results but with 100 or less it provided good result. So how to decide that we need as much number of factor (t dimension) for total variablity space?

i have worked on small program on VHDL but have problem in designing 64 bit pipeline FFT processor in VHDL. Can anybody give me help on this design as coding?

Today’s students, more than ever, often find course-based learning to be boring and meaningless.

In PBL, students are active, not passive; a project engages their hearts and minds, and provides real-world relevance for learning.

After completing a project, students remember what they learn and retain it longer than is often the case with traditional instruction.

Because of this, students who gain content knowledge with PBL are better able to apply what they know and can do to new situations.

What do you think about established this type of center in your country?

I am trying to design a Wallace tree using VHDL programing in Xilinx 13.4 software. I have completed my structural type VHDL programing. When we implement this programing on XILINX 13.4 design suit software then we saw the RTL view and there is no error in programing. But in this programing we used half adder and full adder as a PORTMAP. In XILINX 13.4 design suit software this half adder and full adder is not added so we not get the simulation result (Wave form).

I didn't find a lot articles with making artificial neural network on FPGA, only just reviews. So my question: is it possible? If it is - is it hard? why there is a few articles about it - may be it is too easy?

thank you for responces

VHDl code for UART is somewhat lengthy using state machine ,so i am thinking to implement it without state machine .is it best??

I have decimal numbers ( lets say 8.432, 5.256 etc) in my MATLAB as input for arithmetic operations ,I convert my code to vhdl using HDL Coder. The data type i chose for input and output blocks in Simulink is int32. The code is converted to vhdl but when I see the binary output I only have the non decimal part i.e 8 and 5 in above example .How I could get the binary output for the decimal part too.May be its simple question but being very new in this field dnt know how to do this.

sir, I am trying to do following -

I am giving a signal x(t) as input which has 1000 samples.(i have taken one signal and samples it using the matlab and got the points in form of integars)

Now i have extracted the local maxima and minima of that signal.

By using local maxima i have calculated the upper envelope by using linear interpolation and same i have done with local minima to calculate the lower envelope and then i have taken the average of the upper and lower envelope and have got a signal m(t)

now i have to calculate a new signal h(t) which will be

h(t) = x(t) - m(t)

I have to repeat all above three times, means now again h(t) will be the input signal,

x(t) = h(t)

How to repeat the steps? I have written the code separately for each step. Should i use FSm? If i am going to use FSMs then how can i instantiate the modules in FSMs? Please suggest. I ma in big trouble

I am developing a kit where i have generated a square wave of 4mhz but i am not able to fig out how to vary the on time of signal as i want to calculate duty cycle of signal

I want to implement a neural network in the Sum of Products form and thus have chosen the VHDL coding approach instead of the MATLAB VHDL Coder. Can someone help me with using decimal values in VHDL and subsequently, FPGA?

For control of power electronic conversion processes employing Spartan-3A dsp, will it be better to lean vhdl coding or will it be better if I learn how to use system generator. I have generated more that 15 PWM signals as I am working on multi-phase system.

HI,

Good Day to all...

In digital design, i want to insert control logic or lock mechanism at internal nets. As far as i know, inserting control logic or lock mechanism at High fan-out nets is the best solution in which less no. of locks will have controllability on more no. of internal nodes.

I want to know is there any other net (means any other digital parameter to decide in which net i can insert) if i insert will impact more no. of logic, especially my concern is to increase controllability of output ports. But, fan-in will not help me for this purpose i hope...

Thank you in advance....

Regards,

SUMATHI G.

I need to compare received image with stored image using FPGA kit. For that need HDL coding.How can code to compare two images in HDL. Any other way is available to compare images?

I want to measure the frequency of ring oscillator circuit I inserted in my design. I made circuit schematic using xilinx ISE. During behavioral simulation, my circuit is switching its output, but I could not see its waveform. Hence I could not measure its delay i.e. frequency.

When I select the mode of simulation as post-route, it shows my design is not yet instantiated (question mark near design), when I try to instantiate, its not doing so. Finally I could not measure ring oscillator frequency.