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# Microelectronics and Semiconductor Engineering - Science topic

Microelectronics Circuits and Systems
Questions related to Microelectronics and Semiconductor Engineering
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I plan to divide my long research article(simulation + mathematical) into two parts, but I am clueless about how to do this. (I can not separate the simulation and mathematical analysis)
I have a few questions regarding the same
1) Do I need to show the common mathematics in both parts?
2) Can the introduction be the same?
3) Can some explanations remain the same in both parts?
Can someone give me the reference of any article divided into two parts?
Dear Amit Das,
See my comment precede by >>
I plan to divide my long research article(simulation + mathematical) into two parts, but I am clueless about how to do this. (I can not separate the simulation and mathematical analysis)
>> If the mathematical model is highly original and valuable by itself - you can publish it either separately or along with key simulation results. If the model is quite standard, just briefly refer to it and focus on simulation results. Either way, splitting it on two articles hardly makes sense.
I have a few questions regarding the same
1) Do I need to show the common mathematics in both parts?
2) Can the introduction be the same?
3) Can some explanations remain the same in both parts?
Can someone give me the reference of any article divided into two parts?
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Are they both different or same in case of small channel devices.
Dear Amit Das ,
The depletion layer depth is comprises the region where the doping ion concentration is greater than the majority carrier concentration. Where the inversion region as I defined it before in one of your questions is the width of the region from the surface of the substrate till inversion minority concentration reaches the intrinsic concentration. Consequently, the inversion layer thickness is appreciably less than the depletion region width.
Best wishes
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If we have a diode with p-type (Germanium) and n-type ( Silicon), then what will be the formula to find the built in potential?
Dear Amit Das ,
There is a general formulation for the contact difference of potential between two any two semiconductors or even two materials. Such junctions are called heterojunctions.
The contact difference of potential phi= The work function difference of the two contacted materials. Assume that the work function of the two materials are phi1 and phi2, then phi= Ph1-ph1
The work function of a material is the difference between the vacuum level and the Fermi-level= Ev-Ef
Best wishes
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At schematic level design i need to add bitline capacitances in HSPICE Simulation. preferred model card is PTM.
The bit line capacitance can be first estimated by making the lay out of memory cell array. It is determined by how many cells can be connected to this line which conveys the memory cell signal to the sense amplifier. The length of this line must be limited such that its charging must be sufficient to read the logic values of the memory by the sense amplifier without destructing them.
Best wishes
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How can I extract this particular parameter in TCAD?
Any help or suggestion will be appreciated, thanks!
Dear Amit Das ,Adding to the colleagues above the inversion charge is distributed across the inversion layer with its highest concentration at the surface. Assuming the bulk is p-type with a a hole concentration p0 and minority electron concentration n0. So because of the inversion as a consequence of the influence of the electric field resulting form the applied voltage at the gate the surface region becomes an n-type at sufficient gate voltage. Then the type of the material conduction will become n-type. Between the two types there will be an intrinsic type material with p=n=ni. This is the boundary between the p-type and n-type material and therefore it bounds the inversion layer from the side of the substrate. The other boundary is the surface of the substrate which is interfaced to above oxide layer.
You can the get the thickness of the inversion layer by plotting the electron concentration vertically from the surface of the substrate the point at which n=ni determines the boundary of the inversion layer.
You can also plot the energy level diagram including the Fermi level and the intrinsic Fermi level. The point at which both levels intercept will be the intrinsic
point.
Best wishes
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I-V Characterization of thin-film memristor and Interpretation of Pinched Hysteresis Loop
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I'm trying to model a SiC Schottky diode, but I have two metals above the semiconductor surface. In this case is not an alloy, but a sandwich. When I measure the electrical behavior from the device containing only the Ti film, I've got the curve with the knee (turn-on voltage or rectifier behavior). But when I deposited Al above Ti and do the electrical test, the result shows a linear curve. My question is: Could Sentaurus provide a measurement with 2 or more metals for Schottky contact or just 1 metal? Have you ever performed a model like that? As you can see in the image attached, I designed two devices to compare the situation. The second device did show diode curve behavior.
welcome!
It seems that the layer of the Titanium contains many pinholes then the top aluminum layer will penetrate the the titanium layer reaching the surface of the SiC. At the same time aluminum forms ohmic contact with the SiC.
In this way yo can resolve your observations.
You can verify my prognosis by depositing aluminum directly on SiC and measuring its I-V curve. You can also inspect your Titanium layer after the deposition under the microscope to fix the pinholes.
Please tell us what will you find!
Best wishes
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I am plotting the graphs on MS EXCEL. But after seeing IEEE papers, I noticed that figures are small with a better clarity. I am wondering if there is any other software that may be used for the same. I know there are many free softwares but which software do you prefer.
When I try to reduce my figure size(plotted on EXCEL), it looks distorted.
PS: I need to plot graphs with loads of data (related to MOSFET and TFET).
Any suggestion will be appreciated.
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I am not been able to differentiate between two quantities in the context of BJT.
These two quantities are: Is and Icbo.
According to Sedra Smith, Icbo is the collector base reverse current. Whereas Is is the saturation or scale current.
I have been wondering are these two quantities same or share some relation between them because I find the name for both these quantities being used inter-changeably at many places which is quite confusing and I believe they are not the same.
Also, I am confused which current is being referred to when on Internet I find the term "reverse saturation current". Searching on Internet the term "reverse saturation current" gives two kinds of sources: one referring it as Is and the other referring it as Icbo. Another similar quantity is Iceo.
Please see attached images for equations.
Reverse saturation current terminology is generally used in diode whereas leakage current is used in BJT. But both are more or less indicates the same quantity, i.e leakage current and reverse saturation current is flowing due to the minority carriers.
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Dear Researchers,
Can you kindly share your opinion on practical feasibility on creating a bandgap in graphene for its application in semi-conducting industry and optoelectronics devices.
Does low energy ion-implantation of other atoms in graphene create the required band-gap? Please share related studies if you know.
Sincerely,
Samit
Dear Samit Karmakar, several strategies have been implemented in recent years in order to open up the graphene's band gap for nanoelectronic applications. One of the well-known approaches is the synthesis of graphene nanomesh through etching of graphene basal plane using nanolithography techniques or chemical oxidation. Creation of such nanoholes on the graphene basal plane opens up the band gap and yields a holey nanosheet a suitable semiconductor for construction of transistors. To the best of my knowledge, most of the reported nanolithographic techniques are capable of controling the pits' sizes and in turn tailoring the graphene's band gap for a desired purpose. Furthermore, introduction of different heteroatoms such as nitrogen, oxygen and etc. to the chemical structure of graphene can engender a wider band gap as well. This intriguing topic is quite controversial and entails multitude of delicate details that cannot be brought up here. Below you can find a few papers which can help you to acquire a good insight on this area.
Best,
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The total slurry contained 50 wt% Alumina (D50 = 0.5 um, 11 m2/g surface area), 50 wt% DI water. Powder was dispersed using NH4PMA aqueous solution. PVA aqueous solution was used as binder (20 wt% active matter w.r.t Al2O3), PEG-300 was used as plasticizer (20 wt% w.r.t Al2O3, 1:1 binder to plasticizer ratio). After mixing and debubbling, the slurry seemed good, and a good tape (~450 um thickness) without cracks was obtained after tape casting.
Debinding of single tape (40 mm x 40 mm x 450 um) at 1 C/min, 600 C, 2 h holding gave debinded tape without cracks, which could be sintered too without cracks.
Problem:
I did lamination of 9 tapes via thermocompression using uniaxial warm-press. The temp. used was 80 C, and 15 MPa was the maximum pressure that could be applied.
I also tried with increasing number of tapes up to 15, and for those i used temp of 100 C so that a higher pressure could be applied, and the max. pressure that could be applied was 40 MPa, with change in dimesnions of the pressed tapes. I even tried only two layers pressed at 100 C, 40 MPa.
But: Every time debinding of laminated samples resulted in cracks. I tried with 1 C/min, 0.5 C/min, and 0.3 C/min heating rates up to 600 C. I also tried with giving steps, for example using 0.3 C/min heating rate and holding at 100 C for 2 h, at 300 C for 6 h, at 500 C for 4 h. But the samples always cracked. Please find attached the TG/DTA data of a single tape.
Please guide me how to achieve debinding without cracks. I'll appreciate your kind help.
Thank you.
the reason for your problem is quite clear: lamination creates obstacles to the removal of the evaporated binder. When PVA evaporates, pressure builds up that ruptures the material.
To begin with, you can try replacing the aqueous solution of PVA with an aqueous solution of methylcellulose, the evaporation of which occurs in a wider temperature range and does not create such a high vapor pressure.
If replacing PVA with methylcellulose does not help, then I see no other solution to the problem other than replacing the water-soluble binder with a water-insoluble binder. The new binder must not evaporate, but must be removed by another mechanism, such as melting or oxidation with atmospheric oxygen.
In ceramics, wax-based binders are often used, the removal of which does not cause an increase in pressure in the material. There is also an old technology in which a solution of rubber in gasoline is used as a binder. Rubber does not evaporate as intensely as PVA and does not generate such high vapor pressure. Of course, the use of paraffins or rubber as binders completely changes and complicates the technology of forming a ceramic tape, but there may simply not be another solution.
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I am applying top gate voltage using Al2O3 (100nm) dielectric. I would like to calculate effective elecrtic field applied using this top gate. I can apply top gate voltage of 1V (say). how much effective electric field can be obtained by 1V top gate.
The electric filed in the dielectric is E= V/d = 1 V /(10^-7) m = 10^7 V/m
Because you apply the voltage with a metalic electrode on top of the gate the electric field in the dielectric is less than 10^7 V/m with the Schottky barrier
1V- (50 -100 mV) for Al2O3
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What are the advantages and disadvantages of polysilicon gate over metallic gate?
Dear Amit Das ,
In case of metal gate, one has to produce at firs the source and drain regions by ion implantation through silicon oxide mask and then produce the gate by thin oxide followed by metal deposition. Here one needs another mask to pattern the gate oxide and then a mask to pattern the metal. These are three masks.
In case of polysilicon gate one produce the gate as well as source and drain windows with one mask. Then one can make the ion implantation to produce the source and drain regions. After which one deposit metal and pattern it to define metallization layer. As you see one needs only two masks instead of 3 in case of metal gate.
Then one saves one mask to produce the transistor.
You can review this information in the book of vlsi technology by S M Sze.
or any similar book.
Best wishes
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Is there any relation existing between gate oxide capacitance and off-current in GAA- MOSFET?
Dear Amit Das
The expression may not be very precise. May be more precise expression is that at any capacitance value the MOSFET will be weakly inverted before it reaches the condition of strong inversion assumed to occur at the on set of conduction at the cut off point. Therefore the the cut off is some imposed condition which is not true since the transistor must pass through the weak and medium inversion before it reaches to the start of the strong inversion. Therefore there will be subthreshold current in any value of the capacitance.
But increasing the capacitance will increase the inversion charges at any inversion level. And therefore the transistor current will increases at any inversion level because of increasing the capacitance. In my previous statement they may may be overlap in the effects.
Iy motivated me to precise my answer.
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I want to use Al2O3 or HfO2 as the gate oxide material for GAA MOSFET in the SILVACO TCAD script . How can I do that?
Can I use them directly with just changing the dielectric constant value in the material portion written in my script or do I have to define it explicitly somewhere else?
It will be a great help.
Thanks Khuraijam Nelson sir.
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How do I measure gate leakage current for MOS device using TCAD sentaurus?
Dear Vidya Naidu mam,
Off current could be easily find out for any device but I don't think there is a provision to find out the leakage current directly. There is a difference between off current and leakage current in MOSFET.
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I want to work on the following topics with the following specifications :
Channel Length = 30 nm , R Channel = 10 nm , Doping of source/drain ~ 1016-1020 , Channel Doping ~ 1010 - 1016
1. I want to work on Gate All Around MOSFET
2. I want to work on Gate All Around MOSFET biosensor
Which models must be included in the ATLAS script in first and second part? Kindly suggest if someone have worked on it.
With different models, result comes out to be different and in different papers, a variety of model have been used. So, I am bit confused.
Dear Amit Das ,
If you are making research I think you can yourself choose the most appropriate model either by trial and error or by by developing a rigorous theory for the device.
From the engineering view, you start with the simplest model then you superimpose on it the second order effects.
For example one can use the drift diffusion model to solve for the electronic devices till quantum effects appear in the small size devices, then one has tunneling into consideration.
As a student I would like to detect the boundary by my self or by consulting the literature.
Best wishes
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What techniques are used to make anisotropic SiO2, HfO2, and TiN thin films? (If possible)
The SiO2, HfO2, and TiN are used for the gate stack in certain MOSFETs. There are many studies were isotropic layers were created.
In the particular process that I am studying making anisotropic layers of SiO2, HfO2, and TiN , of only few nanometers each, will make the process a lot easier. However, I am not sure of its feasibility and repeatability.
thank you, much appreciated.
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Dear all,
Here I am simulating TIPS-pentacene based bottom-gate top-contact organic thin film transistor (OTFT) using Synopsys TCAD. I am using Poole-Frenkel mobility model for TIPS-pentacene OTFT simulation. For linear reion, I got similar output current characteristics in experiment as well as in simulation  however, in saturation region simulated output characteristics and  experimental output characteristics differs.
How to mitigate this difference? Do I need to define mobility model for saturation region?
I am having an issue using Poole-Frenkel model in sdevice file when i run sdevice it comes up with an error of stating convergence error, but when i remove Pool-Frenkel model from the sdevice file sdevice runs successfully,
Kindly please suggest me how to use properly the Poole-Frenkel model in sdevice file.
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It is a general practice to introduce Ground Plane in FDSOI devices under the BoX. The Ground Planes are introduced by Ion Implantation through Top Si layer and Buried Oxide. I wanted to know that by doing this implantation, don't they harm the crystalanity of the Top Si layer in which the FDSOI MOSFET will be formed ? Since in FDSOI, they prefer very Low doped or even undoped Si channel, so by doing Ground Plane implantation, don't they affect the intrinsic/undoped/low-doped nature of top Si layer.
Now every thing is very clear and I can answer your question.
Yes you can produce the p+ GP layer by Boron ion implantation.
All what you consider is that you must adjust the range of the implantation to be below the BOX by about three times the deviation of the ion implantation range.
In this way the top silicon layer will not be doped.
After the implantation you need to make rapid thermal annealing only to heal the damage by the ion implantation.
Best wishes
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How long SiH4 will remain stable in the air in ppm-ppb concentrations and how the humidity affects its stability?
I realize this is anecdotal but this is my experience: I've created silane in air mixtures on the order of 2-3 ppm, at pressure up to 2000 psig in steel cylinders, and have tracked them for extended periods of time (I believe my first candidate was produced early 2019). So far, they have remained stable within analytical error of my FTIR analyses.
I think people often neglect to consider is the very nature of oxidation in the context of carbon compounds when they think of "combustion." In its own right, combustion of hydrocarbons is a spin-forbidden reaction. The ground state of O2 (famously paramagnetic that student mistake when they attempt to use Lewis structure theory) does not inherently want to react with diamagnetic hydrocarbons. As such, an ignition or even sufficient pressure (collisions with inert molecules like N2 via the Lindemann-Hinshelwood consideration) could create a sufficient quantity of diamagnetic oxygen to facilitate wholesale chemical interactions.
Silicon is one below carbon on the periodic table. As a starting point for consideration, I will look to methane as a template to consider silane.
Please don't construe my answer as an "expert" answer on this; I am only sharing my experience. I consider my work with my silane in air samples to be "on going."
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In this forum it is required to discuss the effect of the n emitter layer parameters on the the conversion efficiency of the Si np solar cells. These parameters are the junction depth, the doping concentration,the minority carrier life time and the surface recombination of the minority carriers.
Dear Jayakumar,
welcome!
Hope you are well!
The heavy doping concentration has the followings benefits:
- It reduces the reverse saturation current of the solar cell n-p junction and thereby leads to an increase in the opencircuit voltage Voc. This improves the photo conversion efficiency.
- It decreases the resistance of this layer and thereby contribute to the reduction of the series resistance. It leads then to an increase in the fill factor and the PCE.
- The metal silicon contact will be ohmic and its resistance will be smaller leading to higher PCE.
Best wishes
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Dear all
when I simulated VLC system, I used Rayleigh fading channel by calling the function "comm.MIMOChannel". However, I think the correct channel type should be Rician fading channel for VLC.
I would like to know, can i just replace ''Rayleigh'' in parameter "FadingDistribution" with Rician ? Or could someone tell me how to model the Rician channel, namely the main parameters in Rician ?
Thanks
I think it is not easy to determine the fading distribution of VLC channel as it totally depends on the scenario. For example the indoor scenario is totally different about vehicular ones. Also, other parameters might affect this like frequency, existing of blockage and shadowing, etc.
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I have ferroelectric materials in powder form, in solid pellets form and as thin films . How to use Ultraviolet photoelectron spectroscopy (UPS) measurement for band gap calculation in ferroelectric thin films / bulk materials (capacitor) ?
Will it provide right information for Ag/FE/Ag , Where FE is in pellet form ?
Will it provide right information for Ag/FE thin film/FTO ?
Coupling UPS with LEIPS spectroscopies together you should be able to measure the band gap, ionization energy, and electron affinity. This is a low energy inverse photoemission process that bombards your sample with low energy electrons. Electrons fill unoccupied conduction band states and emit photons which you then detect.
UPS will give you a cutoff at the Fermi energy, which I‘d guess you can extrapolate to find the bandgap if you’re confident in the slope. Personally, I wouldn’t use it for anything but the valence band minimum. If you have an Auger system you can also use REELS to do a more accurate approximation.
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Can anybody give details about how NIR spectra is related to glucose absorption in the sense of wavelength?
Infrared radiation induces molecular vibrations as a result of which different bonds absorb light at different frequencies. Glucose for example is a hydrocarbon which consists of C-H, O-H, C-C, C=O functional groups which absorb photons with the right energy to excite overtone and combinations of fundamental molecular vibrations. Therefore, glucose is capable of absorbing NIR light. However, NIR absorption features are low in magnitude and highly overlapping in nature.
References
Hope that helps. Best of luck!!
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According to this article, they compared COVID-9 with 9/11 of USA and says, after the attacks, air travel was severely disrupted. The International Air Transport Association estimated air travel demand was down by over 31% in the five months following the attacks. Much of the money people would have spent on air travel and other vacation expenses was spent on consumer goods. So thereby there will not be much effect on the semiconductor industry. Is it suitable to compare COVID-19 with 9/11? What do you think about this?
All industries will be affected due new measures introduced to control Covid-19. Economic aspects in the production is directly affected by the sick workers!.
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Hello,
Can anyone comment on the carrier mobility of SOI wafers?
I would presume that given the right process, e.g. wafer bonding, it shouldn't differ much from the mobility of bulk Si.
However, I haven't work with such wafers before and I'd appreciate experts' input before we purchase some.
Thanks,
Lior
Thank you Aparna, the first one is link is most useful
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I made a cut 60 degree to the primary flat {0-11) and made a sample of 4X8 mm with primary flat as the base. The shape of the sample is a parallelogram and I made scratch parallel to the primary flat (for the initiation of cleave), clamped it in a special sample holder for X-STM analysis and then tried to cleave it inside the STM chamber in UHV.
The cleave isn't atomically flat (110) but it has a lot of step edges as shown in the figure. I tried to cleave around 15 samples. Most of them look exactly the same way.
Any suggestions or ideas to cleave it properly are welcome.
Mattias Hammar Thanks for the suggestion. I always cleave only after cooling with LN2. Thinning down further is my next option to try.
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most capacitance varies with frequency at low frequency it has high value  in comparasion to high frequency
There are a lot of arguments, one of them the higher frequency has high resistivity, which inactive the minority carriers rapidly at the interface between oxide and semiconductor.
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The functionality of the coating would be a gas barrier, on plastic substrate.
1. Has anyone had experience using Hexamethyldisilazane as precursor in PECVD?
2. Do I need a vaporizer to use this precursor?
3. What gas should I use as a carrier?
4. What precautions should I take when using it?
Any help would be appreciated, thanks.
Hello
-The boiling point of HMDS is 126 °C but since you are working under vacuum, you should heat your precursor up to 50-60 °C
-As a carrier gas, you can use pure argon (and then add your reactive gases into the chamber)
-With HMDS, unlike some sensible precursors, you do not need a glove box. You can fill it normally. Also check the precursor color (it should be the clearest possible otherwise the chemical properties change and the precursor would not be able to vaporize properly).
Regards
Loraine
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I want to to do my research on designing side. My interest are to work on SILVACO TCAD or any other Designing too. If there have someone with whom i cant get idea or can work together in collebration. Your kind support would highly appreciate. Please let me know.
Dear Mr.Ali,
welcome,
There is real problem arising when solving the power electronic circuits using circuit models in SPICE or spice based circuit simulator. There are may times nonconvergence problems. I think the solution of this problem could be solved by using cosimulation between device simulator and circuit simulator. That is with device simulator one can get circuit models that can be solved with convergence using the circuit simulator. The major device is the large area thyristors.
Best wishes
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Although, CMOS transistor performs well up to 28nm node, the short channel effects become uncontrollable in CMOS transistor if scaled below 28 nm. In response to this issue, VLSI Industry replaced CMOS with FINFET and SOI transistor for 14 nm and 7nm technology node.However, as per research conducted, it is estimated that FINFET can be scaled up to 5 nm. Now, question arises what transistor technology industry might adopt to scale transistors below 5nm? I have listed several possible transistor topology below. Which one of the following transistor technology might bring about massive technological change in the near future?
1. Carbon Nano-Tube based FET (CNFET)
2. Gate All Around FET (GAAFET)
3. Compound semiconductor such as Gallium-Arsedine (GaAs), Gallium -Indium-Arsenide (GaInAs), Indium-Arsenide (InAs) based FINFET and GAAFET.
4. Graphene based Tetra-Hz transistors
5. Atomic Transistor
6.Light controlled Transistor or Optical Transistor
7. Mermistor
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Propagation delay means the time difference between input and output.
1. Minimize no. of transistors through the propagation path.
2. Minimize Capacitive ('C') effect through propagation path, since Cap. 'C' makes delay= R*C. This 'RC' delay slows down /degrades the signal propagated through the path.
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Can anyone explain me the significance of ''dark spectral response'' or " Dark EQE" of solar cell and how it will help to improve the efficiency of solar cell?
Another viewpoint. The spectral response (QE) is usually measured with low intensity probe light using chopped light from a monochrometer, and a lock-in amplifier. This gives a "dark" spectral response. The same measurement can also be done under constant auxiliary bias illumination (e.g. AM1.5) in which case the trap occupation and the Fermi levels will be different, and the QE will be different. The differences between light and dark SR are generally larger for cells with more complex recombination pathways (e.g., CdTe-based or a-Si:H) than for single-crystal Si devices. Also there may be time dependent phenomena.
In simulations (AMPS, SCAPS, etc.) one has the option of setting the spectrum and intensity of the bias light (as well as the intensity of the QE measurement light) and one sees substantial differences between light and dark SR.
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Sometimes researchers getting new results out from the similar experiments done by other researchers. But, if they propose some new phenomena against the existing one, the scientific community is not easily accepting. So far I observed, people, trusting, following and try to prove the scientific phenomena (physics) proposed by well-known persons in scientific society. If those results not accepted by any high impact journal community, still, it get accepted by a low impact journal community which infer proposed phenomena were not studied properly.
Would you mind to tell what is real science then? What's exact factor decides the quality of scientific phenomena?
The impact factor of a journal is not always related to the quality of the research published on it. IF is just a librarian's number to assess the number of citations of the journal against their number of papers. Good science and papers will always be found, even in low IF journals (probably up to some threshold level). IF is not a measure of the quality of the paper.
"Real science" as you name it, should always be reproducible, and possible to explain through the simplest explanation (Occam's razor).
Scientific community should never be "easily accepting", that is the main idea of peer review, letters and comments on paper. Scientific community should be all the opposite of easily accepting; and good science should pass the test of the peer review of scientific community.
If I submit a paper, I want it tested under the highest degree of scrutiny. If the paper and its explanations are correct, it must pass all the tests from the scientific community.
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I am trying to extract Threshold Voltage of MOSFET by using extraction.
extract name="vt" (xintercept(maxslope(curve(v."gate",abs(i."drain")))) + abs(ave(v."drain"))/2.0)
But, the Vgs intercepting point by using the maximum slope method is coming very small ( nearly ZERO). That's why I'm getting Vt=Vds/2.
On the other side if I use the CONSTANT DRAIN CURRENT METHOD, then the value is not found in the graph. If I forcefully change the drain current value then the new value is not again found for some other channel Length.
extract name="vt" x.val from curve (abs(v."gate"),abs(i."drain")) where y.val=1e-6
What is right procedure or method and how to solve this problem?
Dear Nelson,
Find the find the transconductance. The voltage is the voltage at which the trasconductance is maximum. This is one way of finding threshold voltage.
Otherwise, you can ask like this " At what drain current, the threshold voltage is measured? Right now I don't know at what drain current it is measured. You please compare drain current of standard article and find how they taking vth.
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Hello dear researchers, I have Tio2 nanowires, what will be possible effects on scattering spectra if we anneal them at 700C and 800C.
Thanks
Dear Kaleem,
As for the answer, if the annealing at such temperature changes the geometry of the nanowires such that large nano wires can soak the small wires or the wires change their orientation then the reflection coefficient of incident waves can be changed. Bu after my expectation at such temperature, there will be no change occurring in the TiO2.
If you speak from radio frequencies then the wavelength of such waves are much larger than the wires so, i think waves will not be affected by annealing even if the wires changed their shapes
Any how the simulation or the experimentation can decisively answer this question.
Best wishes
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It is said that: '' Physical properties of one-dimensional (1D) materials are quite different from those of bulk materials because of their distinct features such as high surface-to-volume ratio''
Is there any review paper or a source to read more about it. What does it really mena and what kind of Physical properties are changed and how do they change.
Going from 3D to 2D and 1D changes many properties in materials. For example, a biological example for the shape of the long is much similar to a physical example of a catalytic convertor used in cars; which is both leverage increase in surface to volume ratio to improve surface reactions. A simple example discussing the impact on dimension on the diffusion can be seen in the following link: https://www.reference.com/science/relationship-between-cell-size-diffusion-2d032974adc9b43b. In electronics application for example, the mobility of careers will be improved in 1D materials compared to bulk materials, much like the mobility of air molecule may improve if the air is passed through a narrow 1D tube vs. air molecule randomly moving in a 3D such as in a room. The strengths of materials such as carbon based materials depends on the bond direction among carbon atoms that leads to differences in carbon nanotubes, graphite, and diamond (e.g., see https://www.scientificamerican.com/article/how-can-graphite-and-diam/). Moreover, variety of simple example for the materials properties as a function of the dimension can be found at NNIN website (https://www.nnin.org/education-training/k-12-teachers/nanotechnology-curriculum-materials/surface-area-volume-ratio).
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I am trying to draw the band diagram of quiternary material which will be used as a quantum well with quaternary barrier. Does anyone know any software that helps to draw this kind of band diagram?
I suggest that consider "mesh" and "plotyy" commands in MATLAB. Using them, the desired graph can be plotted.
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If silicon or germanium or any of the semiconducting material for function using the same material, what will happen when P-type is silicon and N-type is germanium combine together? Due to the cut off point they may not conduct properly, what are other characteristic will vary in this type of combination?
In fact your question is a bit confusing. Generally if you consider pure semiconductor in ideal situation, where [e-]=[h+], then you are right it is confusing to know if it is n-type or p-type. But as we know, there exist NO ideal case, so at some stage [e-]>[h+] OR [e-]<[h+], then you might get n-type or p-type. This happens naturally due to the fact that our raw-material used for fabrication is not 100% pure and even small amount of impurity may change the neutrality condition to n- or p-type semiconducting behavior. For example, if we consider TiO2, then it might also show p-type behavior at some stage based on measurement conditions.
See the new published paper in SNB: https://authors.elsevier.com/a/1XTnA3IQMPAqJy
Article Cost-effective fabrication of polycrystalline TiO 2 with tun...
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I am trying to get ohmic contact between Aluminum and p-type silicon (resistivity 1 to 10 ohm.cm). I did check IV with two separated Al contacts on top and it is showing ohmic nature. Also,  showing ohmic if taking two separate contacts on bottom of silicon.
But, if i am taking one bottom and one top contacts, it is showing schottky. Here, bottom is instrument chuck ground. According to band diagram of Al/Si/Al, one junction will always give schottky behaviour in forward or reverse bias as i understood.
My goal to have bottom Al/silicon contact ohmic.
I am confused how do people check contact nature. Is it ok to check ohmic nature by taking two contacts on one side of wafer !.
Dear Shaimaa,
welcome,
In integrated circuit the most used metallization metal is Aluminum where it is used for metal contact of both n and p type silicon. To form an ohmic contact irrespective of the type of semicondcutor, it must be interfaced to the metal by heavily doped layer that is / Al/n+/n 0r Al/p+/p.
In this way you can use aluminum for both n and p-type silicon.
Best wishes
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I am looking for a p-type metal oxide semiconductor suitable for use at high temperatures (up to 600 C). Any suggestions?
Copper oxide with delafossite structure meets the requirements.
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There are great ideas in circuitry that make us marvel and admire the incredible human imagination of their inventors... Such a great idea is the so-called "dynamic load" in amplifier stages...
Unfortunately, as a rule, this brilliant circuit idea is presented in a formal and sterile way in textbooks and company manuals... and, as a result, it remains misunderstood.
Seeing this paradox, I dedicated years of my life to figure out what it really is... and I still keep thinking about it...
Five years ago, I put this idea for a discussion in the RG forum with a little "provocative" question:
I expected that well-known and experienced circuit designers would be involved in the discussion... and by joint efforts we would reveal the "philosophy" of this technique... but, contrary to my expectations, I did not get any reaction.
One year later, in the hot discussion about the exotic CFA...
... I showed the common in seemingly different circuit topologies of various dynamic load amplifiers (copied in the first my comments below).
I had lost interest in this discussion when, one day ago, on the eve of the New Year, a short insertion of Josef Punčochář to the question below...
Thus a new idea arose in my head - that in fact, in these circuit configurations, the "dynamic load" is something conditional... and we can not say exactly what is the dynamic load and what - the amplifying stage... because, in practice, they are the same thing...
Once again dear colleagues,
So, one can bias the npn amplifying transistor and the pnp transistor load such that their currents are equal and also their DC voltage drops are equal by adjusting their base to emitter voltages.
In case of DC tapping of a current from the common collector point of the two transistors as is case with a second stage connected to the output of the amplifier, this current will be say the input base current IB2. In this case one can increase the load transistor current to be equal to the that current delivered to the amplifying transistor and the base biasing current IB2.
in case of current mirrors.
The other point is that current mirrors can not only deliver an equal collector current but also one can fix certain ratio between them by the adjusting the area ratio of the two transistors. This solution is available for the IC designer.
May be one important point is that using active load in the constant current mode needs some form of current tracking between the two collector currents of the amplifying device and of the load. The current mirror is responsible for this tracking, since it senses the image of the current in the amplifying device which is flowing in the other branch of the differential amplifier, converts it to voltage by the diode connected transistor, this voltages biases the active load. This is a current tracking mechanism. This aids in stabilizing the DC operating point.
This my understanding to the operation of active load of the differential amplifier.
Best wishes
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According to some papers, SF6 could be added to Reactive Ion Etching plasma to avoid micromasking effect. How does it work?
Hi Anton,
there is 2 types of micromasking: 1-micro-masking due to surface residues, 2- self-polluted micromasking (called grass or black silicon in DRIE).
For problem #1, SF6 adding will do little, other than undercutting the residues for lifting them off. It will leave rough surface and it is genreally not pretty. Clean your residues at the surface first. Or some times it is under etching of the hard mask. So add over etching to the hard mask etching prior to etch the main layer.
For problem #2. If you are etching silicon, or material that is getting etched by fluorine plasma, and you get micromasking due to self pollution. First ask the question, is it the large cavities or the tiniest trenches that get micromasking? Large cavities: this is a problem of loading. There is not enough etching species to etch the available silicon. So yes, adding more SF6 will solve the problem. Tiniest trenches? Are they well resolved? Is the Bosch polymer removal step is transmitting enough energy? Etc, is not as straight forward.
Contact me if you need help in deeper details.
Richard
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Consider the following semiconductors with the zinc blende (tetrahedral) crystal structure: BN, InP, InSb, with band-gaps of 6.10, 1.27, and 0.18 eV, respectively; and lattice constants of 0.362, 0.567, and 0.647 nm respectively.
Dear Samares, and colleagues:
welcome,
I would like to add my comment on the answer of the question:
It is so as the lattice constant decreases the interatomic distance will be reduced. As a consequence binding forces between the valence electrons and  and the parent atoms will increase. These valence electrons will occupy the valence band. Since the valence electrons are bound, they have to be supplied with energy to make them moving free inside the material and become conduction electrons. The minimum energy that must be given to valence electrons to become a conduction electron is the energy gap.
So, as the valence electrons get more bound by decreasing the interatomic distance, the more energy required to make them free in the conduction band.
So, A direct consequence of decreasing the lattice constant is the increase in the energy gap. As a rule of thumb the energy gap is inversely proportional to the interatomic distance.
An other factor affecting the energy gap is the dielectric constant, which depends on the density of atoms and their polarizability. The dielectric constant is proportional to N the density of atoms per cm^3 and the alpha the polarizability. The polarizability depends on the electronic structure of the atom.  It is so that the energy gap is inversely proportional to  the dielectric constant which in  turn is inversely proportional to the inter-atomic distance.
Therefore, there are to competing effects to the lattice constant on the energy gap.
the binding energy and the dielectric screening.
Best wishes
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Dear Mitra,
welcome,
May i cam very late to this forum. However as it is a basic question i will give an answer to it that may be useful.
It is so as the lattice constant decreases the interatomic distance will be reduced. As a consequence binding forces between the valence electrons and  and the parent atoms will increase. These valence electrons will occupy the valence band. Since the valence electrons are bound, they have to be supplied with energy to make them moving free inside the material and become conduction electrons. The minimum energy that must be given to valence electrons to become a conduction electron is the energy gap.
So, as the valence electrons get more bound by decreasing the interatomic distance, the more energy required to make them free in the conduction band.
So, A direct consequence of decreasing the lattice constant is the increase in the energy gap. As a rule of thumb the energy gap is inversely proportional to the interatomic distance.
An other factor affecting the energy gap is the dielectric constant, which depends on the density of atoms and their polarizability. The dielectric constant is proportional to N the density of atoms per cm^3 and the alpha the polarizability. The polarizability depends on the electronic structure of the atom.  It is so that the energy gap is inversely proportional to  the dielectric constant which in  turn is inversely proportional to the inter-atomic distance.
Therefore, there are to competing effects to the lattice constant on the energy gap.
the binding energy and the dielectric screening.
Best wishes
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I was studying about  Crystal defects in crystals and came to know that it has huge effect on band diagram.I don't know about their specific impact on band diagram.So what are main impacts of crystal defects on band diagram.?
crystallographic defects produce electronic state in the energy gap of the material. If the defects lies near the conduction band and it are normally filled with electrons they will give their electrons to the conduction band and the material will be n-type. And if they are empty and near the valence band they will accept electrons from the valence band creating holes and the material may become p-type. If the electronic state are lying near the middle of the band gap they will act as effective recombination centers reducing the minority carrier life time.
So, crystallographic defects may cause the material to be n-type, or p-type and may affect the recombination rate in the material.
With the intentional introduction of crystallographic defects with specific concentrations, one can control the electrical properties of the materials.
On the other side if the concentration of the defects becomes large in the order of the effective density of state, the material will behave metal like.
The story of the crystallographic defects is the story of the controlling the conductivity and recombination rate in semiconductors and hence making useful electronic devices.
Best wishes
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In the diploma thesis of my graduate Erol Kerim, I noticed an interesting circuit of a modified current mirror (in the attached picture). It made me think again about this strange circuit solution named "current mirror".
And so:
1. In the classical current mirror the emitters of the transistors are grounded (no emitter resistors).
2. In the Widlar current mirror there is a resistor only in the emitter of the output transistor.
3. Similarly, maybe it makes sense to include a resistor only in the emitter of the input transistor?
4. And finally, does it make any sense to include resistors in the emitters of both transistors?
It would be interesting to discuss and compare the properties of these four configurations by answering the following questions:
What are the effects of including emitter resistors? Are they positive or negative?
Are there any negative feedback(s) in these circuits? If so, what kind are they? How many are they? What is the effect of them?
Obviously in such embarrassing situations everyone has to deal with his/her problems (forums create an illusion of empathy but in practice we are alone in this world)...
I think I made the right decision by first registering in Analog Devices Wiki thus becoming a wiki editor. Then I edited the source of the page and quoted the Wikibooks material at the beginning.
Now I only have to wait for the editor's reaction...
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I am trying to fabricate free standing PMMA micro structures on Silicon substrate, which requires isotropic, selective silicon etching leaving large undercut. I've tried wet etching with KOH, however the selectivity was poor. Reactive ion etching with SF6+C4H8 yields better results, but longer etching time towards desired undercut (~20um) partially destroys PMMA.
Could someone please suggest different recipe with RIE or an alternate approach? (XeF2 would have been promising option, unfortunately we don't have it)
Thank you very much.
I propose you to add a protective layering on PMMA wich will be etched away when the required silicon undercut is reached. "SOG" Spin on Glass should be easily applied on PMMA and removed by wet etching in BHF after finishing undercut process.
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Hi,
I tried doing the CE BJT VI characteristics in the laboratory. However, I could not get the curves (both input and output chara). The following are the problems faced:
1) Input Chara - The base current keeps on increasing (even before the base emitter voltage reached 0.7V, base emitter current flows) - typical diode curve behaviour is not seen
2) Output Chara - The collector current is not flowing in the circuit (with increase in the collector voltage)
The BJT is working fine, so do the meters to measure current.
Please suggest a practical laboratory circuit to obtain the CE BJT VI chara.
Regards,
Raghu
Dear all,
Please find the attached circuit which I tried.
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In order to perform a Solid Phase Epitaxial Regrowth of silicon after ionic implantation, I'd like to perform a Rapid Thermal Annealing under N2 ambient as stated in litterature. But I can't find the N2 pressure used. Is there any critical pressure or any pressure is OK?
Check this paper:
The Effect of N2 Gas Pressure during the Rapid Thermal Process on the Structural and Morphological Properties of CIGS Films
- for silicon ~ 1 torr
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we want measure a degree of metal contamination on si wafer by very short time.
Contamination monitoring and analysis in semiconductor manufacturing
Baltzinger Jean-Luc and Delahaye Bruno
Altis Semiconductor
France
Many analysis are well explained
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I simulated a CMOS design in 45 nm technology by varying the temperature. The power and delay is affected by temperature. why it happens? what is the reason behind it.
Dear Sir,
1. Why does the power go up with temperature ?.
- The power is basically 2 parts:
- The Dynamic part, ie the part of the power that is due to the circuit switching, and
is proportional to the clock the circuit is running on. This is more or less flat, does
not depend on temperature.
- The static part, also called the leakage power. This is due to the current that keeps flowing through the MOS transistors when they are in the off state. For the MOS, the off state more or less proportional to:
exp( kappa * (-VT)/Vt) with
VT : the threshold voltage. Of the order of 0.5 Volt for some transistors (low leakage
transistors), of the order of 0.2 Volt for fast transistors
Vt  = kT/q, with k: bolzmanns constant, T absolute temperature, and q the charge of the electron
kappa: The ratio of gate capacitance to total capacitance.(about 0.8).
The leakage increases with temperature, because of the temperature dependency of Vt. As there is an exponential function involved, the effect can be very pronounced.
2. Why does the MOS become slower with temperature ?.
This is because the electron mobility reduces with temperature. As a result, the current carrying capability of the transistors reduces, and this leads to the circuit becoming slower.
Henri.
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Recently, I am in need of calculating the Richardson constant for Co3O4. Can anyone tell me the effective mass of electron and hole in Co3O4?
I think so
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Now i'm researching the size of photon....The silicon atoms size typical is 1.2 angstrom. is it possible can replaced the hardware by transfer current within transistor using photon instead of silicon atoms, If the photon size much smaller than silicon atom, it can minimize the IC feature size.
Hi Ting Ting Chong,
A photon has size but probably not in the rigid sense that we think about with macroscopic objects. Although photons exhibit properties of particles (and we know the size and mass of subatomic particles such as protons etc.), they also exist as a wave. This is known as wave particle duality.
A 2-d surface can´t have volume so it´s meaningless in such a space, but area isn´t. The radius for photons in this (mathematical) space is never more than the same constant value (but the two components vary sinusoidally about a zero point, so that the area is also cycled this way, from zero to a constant value, and the cycle time, or frequency, determines the energy of a particular photon), this (maximum constant amplitude) appears to be related to its apparent velocity, somehow.
The energy is not related to the distance traveled, unless the photon interacts with another photon (or an electrical or magnetic field, or collides with an electron or other charged bit of matter). In other words you could say that the energy in a photon is bounded by (integrable over) a single period of its cycle (or something similar), like a packetised bit of energy, rather than the integral of all the periods it has cycled through on its journey."
So although the photon appears to exist without physical volume or geometrical size, we can measure the region where the wave's magnitude is non-negligible. This happens at about half a fermi, or roughly 0.5x10-15m.
Thankyou
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Dear Ting,
Martin is okay. I would like to add to his answer: Electrons in atoms or materials have potential and kinetic energy. The potential energy is because they are existing in the electrostatic field of the nuclei. The potential energy needs a reference to measure it.
This reference is the free electron level with zero kinetic energy which is termed  also  the vacuum level. To free an electron from a material or an atom one has to has to transfer it from its stationary level where it is bound and have negative potential energy to the free electron level in vacuum with a zero reference potential energy. This energy spent for this process is the ionization energy for the atoms or the work function for the metals when the electron occupies the Fermi level. While the electron affinity is the energy required to raise the electron from the conduction band edge to the vacuum levels. These specific energies are  characteristics of materials and atoms.
These energies are measured by photoelectric effect where the material is used as a photocathode in a vacuum diode. The cathode is subjected to photons with variable energies. When the photon energy becomes equal or greater than work function of the material electrons will be emitted from the material to the vacuum causing the passage of electric current in the diode.
Best wishes
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In orthogonal cutting operation, why thickness of chip after cut is greater than that of the before cut?
During cutting, the cutting edge of the tool is positioned a certain distance below the original work surface. This corresponds to the thickness of the chip prior to chip formation, to. As the chip is formed along the shear plane, its thickness increases to tc. The ratio of to to tc is called the chip thickness ratio (or simply the chip ratio) r. {r= to/tc}. The chip ratio is always less than one.
Why the chip thickness after cutting is always greater than the corresponding thickness before cutting?
The chip thickness increases as it slides at the shear plane
It becomes shorter  such that the cut volume= the uncut volume
The width b emains unchanged. Then
loxto= lcxtc
The rate  of removal vxtoxb=vfxtcxb
The chip ratio=to/tc = vf/v= <1
Vf is the chip sliding speed at tool face
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Hi,
I'm currently doing sentaurus device simulation on single photon avalanche diode. In order to bias the diode into geiger mode operation, the applied voltage must be above breakdown point. However, normally the simulation can't be continued beyond the breakdown point since avalanche has already been triggered there and the diode would carry a large amount of current. Can anyone help me on how can we solve this problem? Thanks!
Dear Wendi,
welcome!
the dark current of the avalanche photodiode diode is due to the revrse saturation curent which will be multiplied in the space charge region. One of the ways to suppress this current is to reduce the simulation temperature such that reverse saturation current gets smaller than the rate of the single photon incidence rate.
You can also decrease the diode area. In conclusion you must reduce the reverse saturation current to be much less than the photo generation rate.
wish you success
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There is an interesting phenomenon in our MOS C-V curves: when the MOS is biased into depletion, the capacitance of 1MHz (C1M) is higher than that of 100kHz (C100kHz) i.e. C1M > C100kHz, just as the figure shows.
Mr.Peng,
At first i would like to greet you and the colleagues before i add my answer.
The metal oxide silicon capacitor was investigated intensively and showed alawys the the same C-V behavior with the frequency as you pointed out. It is so that the capacitance decreases with the frequency and so the behavior here is deserving interpretation.
I have doubt about some parasitic element acting with the tested capacitor to cause this increase rather than decrease. My doubt is strong because the value of he capacitance you measure is very small . As an example it may be a parasitic inductance added because of the measuring circuit and or probes. As a example coupling capacitor may have self inductance.
A test that may predict the parasitic inductance is to increase the the frequency further if  the deviation  increases this will point out the presence of parasitic inductor.
You can plot the measured capacitance as a function of frequency at a given applied DC voltage to see how the measured capacitance varies with frequency and from that one can determine the reactance with the frequency.
Best wishes.
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can anybody please tell me the value for curie temperature of CeY2Fe5O12, Ce doped YIG (Ce:YIG)
Please use google. It is a thesis from a German university. Searching for 'curie temperature CeY2Fe5O12 551' should bring up a thesis 'about the origin of the seebeck effect'.
Regards
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I'm working on a metrology solution to work at cryogenic temperatures (80 K - 100 K). Ordinary photodiodes often have epoxy encapsulating the die wire bonds. At cryo temperatures, this epoxy shrinks, cracks, and breaks the wire. So I'm looking for a manufacturer that does not do wire bond encapsulation.
A second requirement is that the photodiode not have a window cover (or, at least, that it is easily removable).
Other specs - Si photodiodes, 10x10 mm active area, ceramic housing, NIR-sensitive (some have NIR-suppressed response, do not want that).
Any anyone suggest a supplier?
Dear Boris,
May be one of the solutions is to use Si photo diode chips and mount them your self such that the mount can withstand the required low temperature 80-100 K.
In an experiment to measure the transistor chip  we mounted the chip on a PCB cupper clad board with silver epoxy and bonded gold wires between the pcb bond pads and the bond pads on the chip to access the diode electrically. Then wires are soldered to the terminals of the diode at the PCB boards.
You can get the photo diode chips following the link:http://www.vishay.com/photo-detectors/pin-photo
or any other vendor
Best wishes
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I m working on deposition of zno in silicon for ohmic contact I deposit aluminum on zno , the design is done in atlas,,, bt the problem I face is that I m not able to etch the aluminum .. plz suggest solution
Hello Mr. Kamil Zubair,
Atlas is nothing but device simulator. It is not a process simulator. if you want etch the deposited material you have to use Athena.
In atlas no need to use etch statement. Here you can directly put your structure in stack form.
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I couldn't find out the sensitivity of the sensor using amplitude modulation technique. Please help me with some.
Dimpi,
welcome which sensor you have? By definition the sensetivity of a sensor is defined by the output electrical quantity y as a function of the physical quantity x. This relation ship is mostly linear. That is y= S x, with S the sensitivity. An example is the resistive temperature sensor where R= S T where R is the resistance of the sensor and T is the temperature .
wish you success
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Hello, honorable researchers, I need your expertise advice. For GFET, at zero gate voltage, if positive voltage is applied across drain and source, what would play vital role as majority charge carrier: electrons or holes?
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Semiconductor Physics, Basic Electronics
Dear Vimal,
The Early voltage is a parameter describing the variation of the transistor collector or drain current in the active or the saturation region of operation with the VCE or VDS , respectively. An ideal transistor would operate as an ideal current source in this mode of operation where the the transistor is capable to amplify the signals applied on its inputs when it is biased to operate in the active region of operation.
Real transistors show a small increase of the their collector/drain current with the VCE OR VDS. This is due to the widening of the space charge region in the base of the bipolar transistor or the channel of the MOSFET transistor. In case of the bipolar transistor the gradient of the diffusion current increases leading to an increase in the collector current. While the the channel length becomes smaller as consequence of the drain space charge widening leading to smaller channel resistance and higher drain current.
In case of bipolar transistor it follows that:
IC =Icsat ( 1 + VCE/ VA) where VA is the Early voltage,
Differentiating IC with respect  to VCE one obtains the large signal collector to emitter resistance rCA,
rCA=  VA/ ICSAT,
It is clear that the early voltage physically is one of the determinants of the collector to emitter resistance of the transistor.
Similarly for MOSFET transistor,
r DS= VA/ IDsat,
Where rDS is the large signal drain to source resistance, IDsat is the drain saturation current and VA is the Early voltage of the MOSFET transistor.
wish you sucess
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I am a new user in Labview, currently I want to use the Labview to control my PCB board via USB 6251 for standard semiconductor I-V measurement. Does anyone has the example of the program for me to start with?
Thank you very much
hello,
Your requirements are not clear. USB 6251 is a DAQ. So use DAQ assistant to configure the inputs in labview and wire them accordingly.
Regards,
Ravi Kumar
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Is it possible the holes in a ring be placed in periodic manner? Like if its a linear waveguide, we can simply use PBG crystal structure and put no. of rows and columns according to our need. But this is not the same in case of a ring..
Depends on which simulator you are using to do so. If you are using optiFDTD then I hope you cannot do so but if its some other simulator then you can.
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I am trying to improve the conductivity of SnS films by doping Ag and In doping, annealing. Unfortunately I am not able to achieve highly conductive films. Can anyone suggest me how to enhance the conductivity of these films?
Growth techniques: Thermal evaporation and chemical bath deposition
Annealed: Vacuum 10-5 torr
I would like that you see see this paper, it may be of help to you:Structual and thermoelectric properties of undoped IV-VI epitaxial films alloyed with tin,
The concept of doping is by alloying. You can add Pb. to substitute a fraction of Sn.
wish you success
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I am confused by these two terms: "damping" and "inertia".
It's seems to me that both two terms describe that virtual synchronous generator (VSG) control using the swap-equation to reduce the response speed of "w", which makes the system more stable.
So is any there differences between them? or I've misunderstood something in the concept of VSG?
Hi Liang,
These concepts are very fundamental to the real synchronous generator, and have to do with its synchronous speed w which is a very slow variable in comparison to some others (say the currents in the generator, for example).
When there is a difference between the turbine torque (driving torque or input torque) and the electromechanical torque (consumed torque) on the generator shaft, the difference dT is "shared out" between the inertial acceleration (term with parameter M) and damping (term with parameter D) as follows:
dT = M.dw/dt + D.w
So the two together contribute a slow time constant to the generator (M/D) that contributes by slowing down changes in w thereby stabilizing generator operation.
Coming to the VSG, the same effect is replicated by the two terms (though physically the phenomenon may be absent !). So the two terms are in a way complementary, but not identical !
Hope this helps...
With best wishes.
-Sanjay
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I have fabricated hole conductor free perovskite solar cells (FTO/TiO2/MAPbBr3/Ag). The I-V characteristic show diodic in nature (Dark). But I am not getting Jsc under illumination. What could be the reason?
When you have diode characteristics and have no short circuit current means that the structure has a field region but not able to collect the generated electron hole pairs because they most probable recombine in the material or at the interfaces of the active material because the presence of too many defects. another explanation is that , It is so that there exists many pinholes in the perovskite  such that the junction may be formed by contacting silver and TiO2. The second cause my be more probable if the perovskite is relatively thin and not uniform.
wish you success
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Dear all, I wonder why MIM is keep leaking and if I miss something here. My process is deposit 100nm Al in a pre-clean intrinsic Si ;  then deposit Al2O3 by ALD ; then use shadow mask to deposit another Al as my final step.
When I doing electrical measurement, I use one tip to probe the first Al metal (which is whole sample), and using another probe to just probe the shadow mask in measuring my MIM structure. But everything device is leakage and the characteristic is like there is no Al2O3 at all.
I've also deposit Al2O3 on bare Si to fabricate MIS structure, and all the devices act normal with my electrical measurement.
So it seems not the problem of my ALD. Do I miss consider something when fabricating the MIM structure ?
Thanks !!
I think you would change the metal to be relatively inert against oxygen. I expect that fresh aluminum would extract oxygen from the deposited thin aluminum oxide layer and changes its composition to Al2Ox which may have different properties than the Al2O3. In case of silicon the silicon surface has its native oxide and therefore it is not hungry in the opposite of fresh aluminum surface which is hungry to oxygen and therefore you have increase the thickness of the deposited oxide layer in order to compensate for the extraction of oxygen by the fresh aluminum layer.
This is my prognosis for the leakage.
wish you success
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Dear All,
The gain of the transistors falls at higher frequency due to the parasitic capacitance.Why is it so?
Dear Manoj,
Welcome!
Adding to Aparna, any transistor in active mode of operation acts as a current source at the output which is equal to  Io= gm Vi,where gm is the transconductance and Vi is the input signal.
At the input the transistor is equivalent to an input impedance Zi which is normally a parallel combination of an input capacitance Ci and Resistance ri.
Then the input current Ii = Vi/Zi. It follows that the current gain of the transistor Gi = Io/ii = gm Zi, For the gain magnitude mag Gi= gm xmagnitude of Zi.
Since Zi is a parallel combination of a resistor and a capacitor the magnitude of iys impedance  decreases with the increase in frequency leading to the decrease of the current gain of the transistor with frequency.
Every transistor is characterized by a figure of merit called the gain band width product Gx BW = gm/ 2 pi C, where C is total parasitic capacitance of the transistor.
For bipolar transistors C= Cbe + Cbc,
and for MOS transistor C= Cgs+ Cgd,
wish you success
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