High Level Synthesis - Science topic

Recent Large Language Models (LLMs) such as OpenAI o3-mini and DeepSeek-R1 use enhanced reasoning through Chain-of-Thought (CoT). Their potential in hardware design, which relies on expert-driven iterative optimization, remains unexplored. This paper investigates whether reasoning LLMs can address challenges in High-Level Synthesis (HLS) design spa...

Aiming at the problem of low defect detection rate of PCB images captured by cameras in industrial scenarios under low-light environments, an MGIE (Mean–Gamma Image Enhancement) image brightness enhancement algorithm and the corresponding FPGA design scheme are proposed. Firstly, the RGB image is converted into the YCrCb color space, and the illumi...

Simultaneous Localization and Mapping is intended for robotic and autonomous vehicle applications. These targets require an optimal embedded implementation that respects real-time constraints, limited hardware resources, and energy consumption. SLAM algorithms are computationally intensive to run on embedded targets, and often, the algorithms are d...

APEIRON is a framework encompassing the general architecture of a distributed heterogeneous processing platform and the corresponding software stack, from the low level device drivers up to the high level programming model. Developers can define scalable applications that can be deployed on a multi-FPGA system coding at high level: the APEIRON comm...

Brain-inspired algorithms are attractive and emerging alternatives to classical deep learning methods for use in various machine learning applications. Brain-inspired systems can feature local learning rules, both unsupervised/semi-supervised learning and different types of plasticity (structural/synaptic), allowing them to potentially be faster an...

This paper investigates the use of High-Level Synthesis (HLS) for designing parallel hardware architectures on FPGAs. HLS compilers, like the one used in Vitis HLS, extract the available parallelism so the HLS languages should be thought as inherently parallel and should be programmed with the target parallel architecture in mind. We discuss how HL...

Tensor decomposition algorithms are essential for extracting meaningful latent variables and uncovering hidden structures in real-world data tensors. Unlike conventional deterministic tensor decomposition algorithms, randomized methods offer higher efficiency by reducing memory requirements and computational complexity. This paper proposes an effic...

Nowadays, cardiovascular diseases are prevalent, real-time arrhythmia detection through electrocardiogram (ECG) is a vital aspect of health monitoring. Consequently, there has been growing interest in wearable edge devices capable of real-time ECG classification. Current convolutional neural networks (CNN) for arrhythmia classification often involv...

Deploying deeply quantized neural networks on FPGA devices can be a time-consuming task. This has led to research on tools to automate this procedure, specifically for the case of fast machine learning. This is a specialized field concerned with the very low latency processing of machine learning algorithms as opposed to the more usual task where t...

Ecosystem functioning is a central concept in ecology, describing the array of processes that sustain ecological communities and their environment. This article provides a high-level synthesis of the conceptual foundations, empirical patterns, and practical applications related to the functioning of ecosystems. We first review the historical and th...

Conventional heart rate (HR) monitoring typically relies on contact sensors, but recent advancements demonstrate the potential of non-contact methods using RGB cameras for photoplethysmography (PPG)-based HR analysis. This study presents a real-time, non-contact HR monitoring system that applies signal processing techniques to accurately derive HR...

Ecosystem functioning is a central concept in ecology, describing the array of processes that sustain ecological communities and their environment. This article provides a high-level synthesis of the conceptual foundations, empirical patterns, and practical applications related to the functioning of ecosystems. We first review the historical and th...

Voice disorders pose significant challenges to an individual’s communication abilities and quality of life. Traditional methods for detecting these disorders rely on subjective assessments and manual analysis. Recent works have concentrated on using machine learning algorithms to classify voice disorders. Since these algorithms rely on extensive tr...

We show how to use field‐programmable gate arrays (FPGAs) and their associated high‐level synthesis (HLS) compilers to solve heterogeneous agent models with incomplete markets and aggregate uncertainty (Krusell and Smith (1998)). We document that the acceleration delivered by one single FPGA is comparable to that provided by using 69 CPU cores in a...

Convolutional Neural Networks (CNNs) have demonstrated high accuracy in applications such as object detection, classification, and image processing. However, convolutional layers account for the majority of computations within CNNs. Typically, these layers are executed on GPUs, resulting in higher-power consumption and hindering lightweight deploym...

In this study, we present a novel FPGA-powered hybrid deep learning system for efficient drowsiness recognition based on electroencephalogram (EEG) signals. The proposed system integrates convolutional neural networks (CNNs) and long short-term memory (LSTM) networks, leveraging the strengths of each model to classify EEG signals effectively. To ad...

Real-time image processing is a critical component of vision-based robotic systems, enabling rapid and efficient decision-making in dynamic environments. Field-Programmable Gate Arrays (FPGAs) have emerged as a powerful hardware platform for such applications due to their parallel processing capabilities, low latency, and high computational efficie...

Dynamic High-Level Synthesis (HLS) uses additional hardware to perform memory disambiguation at runtime, increasing loop throughput in irregular codes compared to static HLS. However, most irregular codes consist of multiple sibling loops, which currently have to be executed sequentially by all HLS tools. Static HLS performs loop fusion only on reg...

Implementing machine learning (ML) models on field-programmable gate arrays (FPGAs) is becoming increasingly popular across various domains as a low-latency and low-power solution that helps manage large data rates generated by continuously improving detectors. However, developing ML models for FPGAs is time-consuming, as optimization requires synt...

High-level synthesis (HLS) has enabled the rapid development of custom hardware circuits for many software applications. However, developing high-performance hardware circuits using HLS is still a non-trivial task requiring expertise in hardware design. Further, the hardware design space, especially for multi-kernel applications, grows exponentiall...

Tiny machine learning (TinyML) demands the development of edge solutions that are both low-latency and power-efficient. To achieve these on System-on-Chip (SoC) FPGAs, co-design methodologies, such as hls4ml, have emerged aiming to speed up the design process. In this context, fast estimation of FPGA’s utilized resources is needed to rapidly assess...

The rapid evolution of artificial intelligence and machine learning has intensified the demand for efficient computing solutions, leading to the emergence of Application-Specific Integrated Circuits (ASICs) as a transformative technology. These custom-designed chips offer unprecedented performance improvements and energy efficiency gains compared t...

The rapid evolution of artificial intelligence and machine learning has intensified the demand for efficient computing solutions, leading to the emergence of Application-Specific Integrated Circuits (ASICs) as a transformative technology. These custom-designed chips offer unprecedented performance improvements and energy efficiency gains compared t...

This R\&D project, initiated by the DOE Nuclear Physics AI-Machine Learning initiative in 2022, leverages AI to address data processing challenges in high-energy nuclear experiments (RHIC, LHC, and future EIC). Our focus is on developing a demonstrator for real-time processing of high-rate data streams from sPHENIX experiment tracking detectors. Th...

The rapid evolution of artificial intelligence and machine learning has intensified the demand for efficient computing solutions, leading to the emergence of Application-Specific Integrated Circuits (ASICs) as a transformative technology. These custom-designed chips offer unprecedented performance improvements and energy efficiency gains compared t...

At the Large Hadron Collider, the vast amount of data from experiments demands not only sophisticated algorithms but also substantial computational power for efficient processing. This paper introduces hardware acceleration as an essential advancement for high-energy physics data analysis, focusing specifically on the application of High-Level Synt...

This work designs and implements a custom hard- ware accelerator for single object classification from drone im- agery, for surveillance applications. A lightweight attention-based convolutional neural network (CNN) is developed and translated into hardware implementation as an IP/core. This accelerator is implemented as programmable logic (PL) and...

With the growing popularity of FPGA-based accelerators in HPC applications, new challenges have emerged, particularly in terms of programming and portability. This paper provides an overview of the current state of FPGA tools and their limitations. This study evaluates the performance and portability of two frameworks, SYCL and OpenCL, for developi...

Modern AI applications contain computationally expensive sections. Accelerator cards and tools like AMD Vitis HLS leverage high-level synthesis and hardware (HW) optimizations to create custom HW designs to accelerate them.Nevertheless, the learning curve is steep, even for those with previous knowledge of HW design, due to the complexity of the op...

The recent decades have witnessed unprecedented advances in the complexity of digital hardware systems, yet their design methods are still mostly based on manual register-transfer level (mRTL) languages such as VHDL and Verilog, introduced in the 1980s. While allowing exact system description, these languages have low productivity and require speci...

The ITER International Fusion Experiment Organization is implementing the Real-Time Framework (RTF) to facilitate the development, deployment, and execution of instrumentation and control (I&C) applications optimized for real-time performance using the GNU/Linux-based ITER CODAC Core System software distribution. This contribution examines the feas...

Customized processors are attractive solutions for vast domain-specific applications due to their high energy efficiency. However, designing a processor in traditional flows is time-consuming and expensive. To address this, researchers have explored methods including the use of agile development tools like Chisel or SpinalHDL, high-level synthesis...

Graph-based neural networks have proven to be useful in molecular property prediction, a critical component of computer-aided drug discovery. In this application, in response to the growing demand for improved computational efficiency and localized edge processing, this paper introduces a novel approach that leverages specialized accelerators on a...

Reconfigurable processor-based acceleration of deep convolutional neural network (DCNN) algorithms has emerged as a widely adopted technique, with particular attention on sparse neural network acceleration as an active research area. However, many computing devices that claim high computational power still struggle to execute neural network algorit...

This paper proposes efficient implementations of robot audition systems, specifically focusing on deployments using HARK, an open-source software (OSS) platform designed for robot audition. Although robot audition systems are versatile and suitable for various scenarios, efficiently deploying them can be challenging due to their high computational...

The FPGA environment is traditionally exotic to high-level software developers, mainly due to the large difference in the development methodologies. This can be mitigated through High-Level Synthesis (HLS) tools. By incorporating complex models and code analyses, these tools allow the use of software languages as input for FPGA designs. This paper...

Matrix multiplication is a fundamental operation in various scientific and engineering applications, often demanding high computational resources. With the growing complexity of data-intensive tasks, optimizing this operation to run efficiently on hardware accelerators like FPGAs has become crucial. However, the challenge lies in balancing the reso...

The slowing of CMOS technology scaling mismatches the ever-increasing demand for computational power, leading to a rise in the use of heterogeneous systems, which pair scalar processors such as CPUs with specialized accelerators like FPGAs and GPUs. These systems enable continued performance and efficiency scaling for specialized tasks while retain...

Camera Pose Estimation (CPE) is vital in augmented reality, virtual reality, and assisted living applications (AAL). While many software solutions exist, hardware-based solutions are more complex due to resource constraints (like memory, timing, etc.) This work uses a Field Programmable Gate Array (FPGA) based hardware accelerator to detect square...

Our aim for the ML Contest for Chip Design with HLS 2024 was to predict the validity, running latency in the form of cycle counts, utilization rate of BRAM (util-BRAM), utilization rate of lookup tables (uti-LUT), utilization rate of flip flops (util-FF), and the utilization rate of digital signal processors (util-DSP). We used Chain-of-thought tec...

Computational Fluid Dynamics (CFD) simulations are essential for analyzing and optimizing fluid flows in a wide range of real-world applications. These simulations involve approximating the solutions of the Navier-Stokes differential equations using numerical methods, which are highly compute- and memory-intensive due to their need for high-precisi...

Matrix multiplication is a fundamental operation in various scientific and engineering applications, often demanding high computational resources. With the growing complexity of data-intensive tasks, optimizing this operation to run efficiently on hardware accelerators like FPGAs has become crucial. However, the challenge lies in balancing the reso...

High-level synthesis (HLS) aims at democratizing custom hardware acceleration with highly abstracted software-like descriptions. However, efficient accelerators still require substantial low-level hardware optimizations, defeating the HLS intent. In the context of field-programmable gate arrays, digital signal processors (DSPs) are a crucial resour...

This paper explores advanced techniques in high-level synthesis (HLS) utilizing metamodel structures. Metamodels act as models of hardware models, generating internal hardware models based on parameter inputs and exploring the solution space to find optimal configurations. The focus is on enhancing HLS processes through metamodeling, enabling more...

Background Quality maternity care is known to improve a range of maternal and neonatal outcomes. The Lancet Series on Midwifery's Quality Maternal and Newborn Care (QMNC) Framework is a high‐level synthesis of the global evidence on quality maternity care. Initial qualitative work demonstrated the Framework's adaptability in evaluating service user...

Dynamic programming (DP) based algorithms are essential yet compute-intensive parts of numerous bioinformatics pipelines, which typically involve populating a 2-D scoring matrix based on a recursive formula, optionally followed by a traceback step to get the optimal alignment path. DP algorithms are used in a wide spectrum of bioinformatics tasks,...

In recent years, field programmable gate array (FPGA) have been used in many internet of things (IoT) devices and are equipped with cryptographic circuits to ensure security. However, they are exposed to the risk of cryptographic keys being stolen by side-channel attacks. Countermeasures against side-channel attacks have been developed, but they ar...

Microwave Kinetic Inductance Detectors (MKIDs) are superconducting detectors capable of single-photon counting with energy resolution across the ultraviolet, optical, and infrared (UVOIR) spectrum with microsecond timing precision. MKIDs are also multiplexable, providing a feasible way to create large-format, cryogenic arrays for sensitive imaging...

Diverse computing paradigms have emerged to meet the growing needs for intelligent energy-efficient systems. The Margin Propagation (MP) framework, being one such initiative in the analog computing domain, stands out due to its scalability across biasing conditions, temperatures, and diminishing process technology nodes. However, the lack of digita...

In recent years, studies on artificial intelligence and high-performance computing have accelerated computations using field programmable gate arrays (FPGAs). High-Level Synthesis (HLS) is beneficial for implementing algorithms from these fields onto FPGAs as circuits. However, because the circuits generated by HLS are generally larger than those d...

Workshop on Fully Programmable Systems-on-Chip for Scientific Applications | (smr 3983) The Workshop aims at providing key know-how to effectively take advantage of fully programmable Systems-On-Chip (SoC) and their applications to advanced scientific instrumentation. This novel technology combines multicore processors with traditional FPGAs in a...

High-level synthesis (HLS) is a widely used tool in designing Field Programmable Gate Array (FPGA). HLS enables FPGA design with software programming languages by compiling the source code into an FPGA circuit. The source code includes a program (called ``kernel'') and several pragmas that instruct hardware synthesis, such as parallelization, pipel...

The increasing complexity of large-scale FPGA accelerators poses significant challenges in achieving high performance while maintaining design productivity. High-level synthesis (HLS) has been adopted as a solution, but the mismatch between the high-level description and the physical layout often leads to suboptimal operating frequency. Although ex...

Field-Programmable Gate Arrays (FPGAs) are becoming an interesting component for heterogeneous computing systems in the post-Moore era thanks to their reconfigurable nature. The current generation of FPGAs includes specialized hard blocks for floating point operations, making them attractive for scientific computing. FPGA programming has historical...

FPGAs are popular in many fields but have yet to gain wide acceptance for accelerating HPC codes. A major cause is that whilst the growth of High-Level Synthesis (HLS), enabling the use of C or C++, has increased accessibility, without widespread algorithmic changes these tools only provide correct-by-construction rather than fast-by-construction p...

FPGA programming is more complex as compared to Central Processing Units (CPUs) and Graphics Processing Units (GPUs). The coding languages to define the abstraction of Register Transfer Level (RTL) in High Level Synthesis (HLS) for FPGA platforms have emerged due to the laborious complexity of Hardware Description Languages (HDL). The HDL and High...

The multifaceted, multivendor-based global design supply chain induces hardware threats of intellectual property (IP) piracy for modern computing and electronic systems. Current hardware watermarking techniques fall short either in terms of watermark strength (size of covert constraints generated) or number of security layers/variables involved in...

High-level synthesis (HLS) is an automated design process that transforms high-level code into hardware designs, enabling the rapid development of hardware accelerators. HLS relies on pragmas, which are directives inserted into the source code to guide the synthesis process, and pragmas have various settings and values that significantly impact the...

In this paper, we address the challenge of a real-time solution for the critical detection step in a LTE-advanced (LTE-A) cognitive radio (CR) network implemented using limited computing resources. The detection step is required to identify a free radio channel that can be used to transmit data. We first present two new detectors and their naive im...

Field Programmable Gate Arrays (FPGAs) play a significant role in computationally intensive network processing due to their flexibility and efficiency. Particularly with the high-level abstraction of the P4 network programming model, FPGA shows a powerful potential for packet processing. By supporting the P4 language with FPGA processing, network r...

In this paper, we introduce an efficient algorithm for automating the direct transformation of a control flow graph (CFG) into a synthesizable finite-state machine with implicit datapath (FSMD). In our opinion, this transformation has not received sufficient attention: although the passage of a CFG to FSMD is mentioned in many textbooks on digital...

In recent years, security monitoring of public places and critical infrastructure has heavily relied on the widespread use of cameras, raising concerns about personal privacy violations. To balance the need for effective security monitoring with the protection of personal privacy, we explore the potential of optical fiber sensors for this applicati...

In this paper we discuss the algorithmic aspects of uncertainty driven scheduling which is a new design paradigm. Slack oriented design flow could be used to address the uncertainty problem in high level synthesis. We formalize the concept of slack and discuss d ifferent variations of the slack driven scheduling problem.

The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS process, leveraging their ability to understand natural language specifications and refactor code. We s...

Three-dimensional(3D) shape measurement using point clouds has recently gained significant attention. Phase measuring profilometry (PMP) is widely preferred for its robustness against external lighting changes and high-precision results. However, PMP suffers from long computation times due to complex calculations and its high memory usage. It also...

Many modern embedded systems have end-to-end (EtoE) latency constraints that necessitate precise timing to ensure high reliability and functional correctness. The combination of High-Level Synthesis (HLS) and Design Space Exploration (DSE) enables the rapid generation of embedded systems using various constraints/directives to find Pareto-optimal c...

Dynamically scheduled hardware enables high-level synthesis (HLS) for applications with irregular control flow and latencies, which perform poorly with conventional statically scheduled approaches. Since dynamically scheduled hardware is inherently data flow based, it is beneficial to have an intermediate representation (IR) that captures the globa...

Scenario planning is a tool used to explore a set of plausible futures shaped by specific trajectories. When applied in participatory contexts, it is known as participatory scenario planning (PSP), which has grown in its usage for planning, policy, and decision-making within the context of climate change. There has been no high-level synthesis of s...

Large language models (LLMs) have catalyzed an upsurge in automatic code generation, garnering significant attention for register transfer level (RTL) code generation. Despite the potential of RTL code generation with natural language, it remains error-prone and limited to relatively small modules because of the substantial semantic gap between nat...

Implementing Machine Learning (ML) models on Field-Programmable Gate Arrays (FPGAs) is becoming increasingly popular across various domains as a low-latency and low-power solution that helps manage large data rates generated by continuously improving detectors. However, developing ML models for FPGAs is time-consuming, as optimization requires synt...

As Field Programmable Gate Arrays (FPGAs) computing capabilities continue to grow, also does the interest on building scientific accelerators around them. Tools like Xilinx's High-Level Synthesis (HLS) help to bridge the gap between traditional high-level languages such as C and C++, and low-level hardware description languages such as VHDL and Ver...

This letter introduces a framework for the automatic generation of hardware cores for Artificial Neural Network (ANN)-based chaotic oscillators. The framework trains the model to approximate a chaotic system, then performs design space exploration yielding potential hardware architectures for its implementation. The framework then generates the cor...

Kolmogorov-Arnold Networks (KANs), a novel type of neural network, have recently gained popularity and attention due to the ability to substitute multi-layer perceptions (MLPs) in artificial intelligence (AI) with higher accuracy and interoperability. However, KAN assessment is still limited and cannot provide an in-depth analysis of a specific dom...

High-Level Synthesis (HLS) tools have revolutionized FPGA application development by providing a more efficient and streamlined approach, significantly impacting digital design methodologies. Despite the capability of FPGAs to customize numerical representations in data paths, most HLS projects have focused on fixed-point precision, while floating-...

The design and synthesis of masked cryptographic hardware implementations that are secure against power side-channel attacks (PSCAs) in the presence of glitches is a challenging task. High-Level Synthesis (HLS) is a promising technique for generating masked hardware directly from masked software, offering opportunities for design space exploration....

Modern Field Programmable Gate Arrays (FPGAs) offer a solution to several issues related to real-time on-board systems, such as guaranteed execution time. They are currently considered as target platforms for space applications. However , the complexity of producing circuits on these components poses a challenge to their widespread adoption. To add...

High-level synthesis (HLS) has significantly advanced the automation of digital circuits design, yet the need for expertise and time in pragma tuning remains challenging. Existing solutions for the design space exploration (DSE) adopt either heuristic methods, lacking essential information for further optimization potential, or predictive models, m...

Many components, including software/hardware CPUs, hardware description language (HDL) modules, high-level synthesis (HLS) entities, and embedded Linux / bare-metal applications, are used in the development of modern FPGA firmware. This is due to the usage of custom modules, tools from various vendors, and hierarchical designs from various manufact...

In High-Level Synthesis (HLS), converting a regular C/C++ program into its HLS-compatible counterpart (HLS-C) still requires tremendous manual effort. Various program scripts have been introduced to automate this process. But the resulting codes usually contain many issues that should be manually repaired by developers. Since Large Language Models...

The object of the study is the procedures for automated design and analysis of digital signal processing algorithms on the SoC technology platform. The subject of the study is models, methods and procedures for designing and optimal selection of SoC components for the implementation of digital signal processing algorithms for audio spectrum. The ai...

Reconfigurable hardware circuits, such as field-programmable gate arrays, have gained popularity in the high-performance computing (HPC) community in recent years. Nevertheless, their real contribution to accelerating HPC workloads is unclear in both potential and extent.

Recently, every aspect of human existence has been affected by modern technologies including agriculture. The broad range of crops has witnessed setbacks in different capacities due to climate change among other factors, hence leading to diseases and infections; thereby leading to negatively impacted nutrition. This work uses a deep learning algori...

Canny edge detection is a widely employed technique in image processing known for its effectiveness in identifying and highlighting edges within digital images. Because of its excellent performance, the Canny Edge Detector is one of the most used edge detection algorithms. For several image processing techniques, including image enhancement, image...