Questions related to Hardware Design
As a student who wants to design a chip for processing CNN algorithms, I ask my question. If we want to design a NN accelerator architecture with RISC V for a custom ASIC or FPGA, what problems or algorithms do we aim to accelerate? It is clear to accelerate the MAC (Multiply - Accumulate) procedures with parallelism and other methods, but aiming for MLPs or CNNs makes a considerable difference in the architecture.
As I read and searched, CNN are mostly for image processing. So anything about an image is usually related to CNN. Is it an acceptable idea if I design architecture to accelerate MLP networks? For MLP acceleration which hw's should I work on additionally? Or is it better to focus on CNN's and understand it and work on it more?
In classical biotechnology, three stages are distinguished: pre-fermentation, fermentation, post-fermentation. Typical equipment used in biotechnological industries is known. Are there any features in the hardware design of biopolymer production, such as proteins (enzymes), polysaccharides (starch, cellulose), lipids (lipids of microalgae)?
Looking for good information sources, both academic sources and practical examples.
Informed opinions, comments and other types of answers are very much appreciated.
I am working with DC compiler. My design has some sequential elements (D-FF) which reset's on negative edge of reset signal input to the design. Is there a way to tell compiler that on power-on, initially my circuit will go through the reset?
Due to this all the FF's may be having different initial states, and I do not get the expected synthesis results in terms of the logic elements.
I have a hardware IP written in Verilog that I synthesized using Design Compiler for a given technology. The IP is basically an ALU, and I want to measure the power consumption or energy values associated with each operation performed inside the ALU (addition, multiplication, ...).
So I did a post-synthesis simulation on the synthesized design and I fed that into PrimeTime (PrimePower) in order to take in consideration the node acitivities. At the end I get reports showing power consumption. What I need is actually to get a graph representing the power consumtion vs. time, as shown in the attached example.
Is this possible in PrimePower? or should I use some other tool? Any ideas?
Currently in my project, I am making a hardware controller which can modify the incoming PWM signal and vary the EV A.C charging. To start of with, does anyone know which exact chapters of IEC 61851 standards to buy ? I find that there are many chapters. Basically this hardware will modify the incoming charging current from EVSE to EV according to our inputs. Any literature/material regarding this will be useful. Thanks
I am doing my master thesis on model predictive control. I am controlling the quadruple tank system using the model predictive control. I have done with the hardware design by using arduino and stuffs like that and the MPC design has done as well. But the problem is, how to implement the hardware system with MPC design. Looking for the solutions for my issue. Thanks in advance
Dear RG Colleagues,
I have large number of music and pictures in CD-ROMs. I need to build LAN network accessed storage using of-the-shelf components.
What are the needed components for hardware and software?
I am good in Linux and I think It is easier and cheaper for me.
Your help please.
As per the definition of logic obfuscation, obfuscated circuit stays in obfuscated mode upon global reset (i.e. initial state) and generates incorrect output; upon receiving correct initialization sequence it enters into functional mode and generates intended outputs.
This is fine with respect to the design that does not connected with any further critical systems. If at all, the obfuscated logic needs to be connected to further safety critical systems, won't incorrect value generated in obfuscated mode affects the critical systems??
In such case, how to apply logic obfuscation??
Thanks in advance.
Since most user research or often called UX research deals with software design, I am wondering where I can find information on methods (e.g., interviews, card sorting), tools (e.g., eye tracking), and best practices (e.g., A/B testing) especially in the area of hardware design.
Thank you very much for any advice,
Can any one suggest me some Tips for Hardware Design of DC-DC Converters for high and low power Applications
boost converter, Buck & buck-boost Converter
1. Mosfet ( how Can I choose a mosfet for high &lower power applications ???? )
2. Diode ( which type of Diode should I use for high & lower power? )
3. Inductor ( for L I use Kg Method to design it by myself but I just do it upto calculation but not hardware. How can I design L on hardware??)
For Control I prefer I UC3843 IC but I want to use high Power do I need to change the this IC (UC3843) for should I use this same IC for its control ??
I am required to build a optical VLC OFDM system and i understood the theoretical part well, how to start the implementation and hardware designs ? ,, I need to know how to build the hardware and the steps needed ? .. thanks in advance
For HDD, as per my understanding,
access time (approx) = seek time+ rotational latency + transfer time.
Now when data is contiguous then there is single seek time, single rotational time but for dispersed data it will take multiple seek and latency time. Even transfer time for contiguous data is less than or equal to transfer time of dispersed data since the data has a unit of reading data (called block) so for dispersed data it might need more block reads than contiguous data.
Please correct if my understanding about the HDD (Hard Disk Drive) is not correct.
I am not sure about the difference in access time for SSD (Solid State Disk) as I don't much about its working and the minimum unit of reading data.
Please throw some light.
Text file (LUT) Input/Output to FPGA Virtex 6 (ML605 board)
I have an ML605 evaluation kit (Virtex 6 FPGA). I want to do the following:
-Store/copy (binary) data from .txt file in BRAM (or preferably an external memory on the board).
-Read that data from BRAM, that will input for our module (e.g. input_1 and input_2).
-Store/write the output of module (e.g. sum) in BRAM.
-Export that data to .txt or any other file format from where we can fetch the binary values.
Recently, the Hardware Profiles for my TQ4500 in Analyst 1.6.2 disappeared. I could not get them back. I could not save new profiles without reinstalling Analyst after which everything was fine until changing the Project Folder from default at which point Analyst crashed. Every time the program was opened the sotware crashed immediately after this. After reinstalling a second time the same occured. I'm stumped. Never seen the Hardware Profiles disappear before. If anyone has any advice or has seen this before I appreciate it otherwise, assuming I can resolve the issue I will update with how.
I need some material such as Books, Articles and so on for how can I write the image processing using VHDL?
I know how can I convert code but I need some material to write image processing using VHDL by own.
I am trying to run PSIBLAST on my computer (PSIBLAST 2.3.0+) using NR data bank (the latest version). However, it seems that PSIBLAST does not use more than 8Mb RAM therefore, it take so long (in fact, it does not complete its task). I was just wondering what is the reason? I am using Ubuntu (14.04). I even tried using JRE Java (uninstalled JDK Java and installed latest version of JRE) but still it does not work. Does anybody have the same experience? Can anybody help me?
I've been working with VHDL programming since a long time. And I want to know a good methodology of programming complex algorithms in specially machine learning, signal processing.
I am trying to implement an image fusion algorithm using wavelet transform on FPGA. I just have a vague idea of the project. But to implement a hardware design, I am unaware of the concepts that I need to know of how to accumulate the data and to process the data further as required like filtering of the image , etc.
I am from software background and have a basic question.
I understand that CPU caches in multicore processors can snoop transactions on coherent system bus. They can also snarf the data flowing in some of the bus transactions.
Can the devices such as offload accelerators etc also snarf transaction data (based on some filtering criterion such as address ranges)?
I am designing my active power filter circuit in hardware design. I calculate the system parameters using the formula. I am confused on some points in my system designs.
1. The values in simulation are different than formula parameters in case of inductances.
2. How can I install the inductance towards the source side and load side? I mean do I have to use the transformer or separate inductance or source or line inductance?
3. My work is in active power filters, so I have to design the source and load prototype and which values I can used (Simulation one or formula one).
Kindly guide me in this matter. Thanks
I worked on a study about the implication of defensive programming over the reliability of software. The software in the study can be classified as being the software of critical application. We obtained very interesting results but I did not find, three years after the conclusion of the project, papers with a close relation to that subject. Is there no interest in development on this kind of study because the probability of random errors is low, or perhaps, this errors are corrected by hardware protection with sufficient effectiveness ?
I know VHDL and did some projects, I am familiar with the hardware design concepts. What i need is a reference book in which i can get the rules in Verilog
It is not possible to assign a wire data type inside always.
All ports are defined as reg data types.
I want to create my own hardware for WSN systems by modifying the open source hardware platforms like beagle bone or so.
Can somebody tell me which hardware platform provides all the hdl logic files and hardware design documents that can be modified to create your own hardware products.
I have to build an Hardware Abstraction Layer Between my device and my Application for understanding its characteristics.
Suppose a ZigBee device or Bluetooth device is connected to any host machine , machine should automatically identify the device by using the polymorphic method...and runs the predefined application
We are working on a project to baseline power consumption for a smart camera that can be configured for passive stereo vision or IR+visible multi-spectral. The design does most of the frame by frame processing in an FPGA, but we plan to integrate a TI-OMAP running embedded Linux to integrate some machine learning algorithms we want to test along with just basic network uplink and management interface - the camera will be dropped off in locations in the Arctic, so very power constrained. Just curious what sort of lifetimes people are seeing with Beagle Juice and how well the batteries work, lifetime, etc. Also, has anyone used solar charging? (Not a great option in the Arctic in winter of course).
Dear Hardware Community,
I am starting my Master Thesis and I would like to explore certain hardware structures and create accurate, parameterized high level models for it. I still haven't decided aon the details of my work and in this formative stage I would like to ask the community for useful resources.
A number of papers that I browsed so far are 5 to 10 years old and I am curious about the most up to date items.
I would also like to ask which kind of tools are commonly employed for power consumption estimation (both low level and high level).
Any information would be much appreciated.