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As a student who wants to design a chip for processing CNN algorithms, I ask my question. If we want to design a NN accelerator architecture with RISC V for a custom ASIC or FPGA, what problems or algorithms do we aim to accelerate? It is clear to accelerate the MAC (Multiply - Accumulate) procedures with parallelism and other methods, but aiming for MLPs or CNNs makes a considerable difference in the architecture.
As I read and searched, CNN are mostly for image processing. So anything about an image is usually related to CNN. Is it an acceptable idea if I design architecture to accelerate MLP networks? For MLP acceleration which hw's should I work on additionally? Or is it better to focus on CNN's and understand it and work on it more?
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As I understand from your question, you want to design the chip for your NN. There are two different worlds, one is developing a NN and converting it into an RTL description. Concerning this problem, if your design is sole to implement on ASIC then you have to take care of memories and their sizes. Also, you can use pipelining and other architectural techniques to design a robust architecture. But The other implements it on an ASIC with a commercial library of choice. This is the job of the design engineer who will take care of the physical implementation. Lastly, if you want to implement FPGA then you should take care to exploit DSPs and BRAMs in your design to gett he maximum performance of NN.
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In classical biotechnology, three stages are distinguished: pre-fermentation, fermentation, post-fermentation. Typical equipment used in biotechnological industries is known. Are there any features in the hardware design of biopolymer production, such as proteins (enzymes), polysaccharides (starch, cellulose), lipids (lipids of microalgae)?
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For thickening polysaccharides, like xanthan, mixing to ensure gas exchange is the limiting factor. At late stages, the injected air tends to rise in huge bubbles with very little exchange.
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Looking for good information sources, both academic sources and practical examples.
Informed opinions, comments and other types of answers are very much appreciated.
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Agile is almost always use in SW development.  What are some great examples of it being used for hardware development
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Is there anything like Leetcode or Hackerrank for practicing rtl design?
How does most people practice problem solving for rtl design/verification?
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I am working with DC compiler. My design has some sequential elements (D-FF) which reset's on negative edge of reset signal input to the design. Is there a way to tell compiler that on power-on, initially my circuit will go through the reset?
Due to this all the FF's may be having different initial states, and I do not get the expected synthesis results in terms of the logic elements.
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I think you have stumbled upon a tool optimization feature.
In my synthesizer (cadence genus), I get two flops if I run it with low effort. In high effort, the logic becomes a single flop.
See my code (attached).
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I have a hardware IP written in Verilog that I synthesized using Design Compiler for a given technology. The IP is basically an ALU, and I want to measure the power consumption or energy values associated with each operation performed inside the ALU (addition, multiplication, ...).
So I did a post-synthesis simulation on the synthesized design and I fed that into PrimeTime (PrimePower) in order to take in consideration the node acitivities. At the end I get reports showing power consumption. What I need is actually to get a graph representing the power consumtion vs. time, as shown in the attached example.
Is this possible in PrimePower? or should I use some other tool? Any ideas?
Thanks.
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you can use Mentor Graphics ..tanner eda tool
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Hello,
Currently in my project, I am making a hardware controller which can modify the incoming PWM signal and vary the EV A.C charging. To start of with, does anyone know which exact chapters of IEC 61851 standards to buy ? I find that there are many chapters. Basically this hardware will modify the incoming charging current from EVSE to EV according to our inputs. Any literature/material regarding this will be useful. Thanks
Regards,
Praveen
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Yes
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Hello all
I am doing my master thesis on model predictive control. I am controlling the quadruple tank system using the model predictive control. I have done with the hardware design by using arduino and stuffs like that and the MPC design has done as well. But the problem is, how to implement the hardware system with MPC design. Looking for the solutions for my issue. Thanks in advance
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Dear Vinoth
You can use laguerre functions to make MPC more efficient and make it feasible for real time implementation. For reference you can see the paper " real-time implemntation of MPC on a 16-bit microcontroller for speedc control of a DC motor". Thanks
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Dear RG Colleagues,
I have large number of music and pictures in CD-ROMs. I need to build LAN network accessed storage using of-the-shelf components.
What are the needed components for hardware and software?
I am good in Linux and I think It is easier and cheaper for me.
Your help please.
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Have a look at hardkernels products. I have been using the odroid XU4 for my project work, it has 8 cores and a GPU, based on Samsungs' exynos 5422 (was in the S5 phone). Odroid do a home cloud device, 4 boards with 8 cores if you are that serious and need 32 cores!! see https://www.hardkernel.com/shop/odroid-mc1-my-cluster-one-with-32-cpu-cores-and-8gb-dram/
They also have new boards in the release path, reasonably priced!
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Hi,
As per the definition of logic obfuscation, obfuscated circuit stays in obfuscated mode upon global reset (i.e. initial state) and generates incorrect output; upon receiving correct initialization sequence it enters into functional mode and generates intended outputs.
This is fine with respect to the design that does not connected with any further critical systems. If at all, the obfuscated logic needs to be connected to further safety critical systems, won't incorrect value generated in obfuscated mode affects the critical systems??
In such case, how to apply logic obfuscation??
Thanks in advance.
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You can read the literature yourself and come up with your own conclusions. It would do you good, you would sound less like a non-expert rambling about something you have very little clue about. I am done here.
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Since most user research or often called UX research deals with software design, I am wondering where I can find information on methods (e.g., interviews, card sorting), tools (e.g., eye tracking), and best practices (e.g., A/B testing) especially in the area of hardware design.
Thank you very much for any advice,
Jonas
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Dear Jonas,
a lot of "classics" in the field of UX/ Usability or Interaction Design are actually not tied to only software design. Most methods are applicable to hardware design, too, including all sorts of every day things (referring to the classical example "the design of everyday things" by Norman).
You might also want to look at DIN EN ISO 9241 specifically parts like 210, 110... whatever fits your needs.
The key point here "what fits your needs", "what is the problem" and "what is your goal".
A good book about general "HCI" research methods is for example:
Lazar, J., Feng, J. H., & Hochheiser, H. (2017). Research methods in human-computer interaction. Morgan Kaufmann.
All the best for your research!
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Can any one suggest me some Tips for Hardware Design of DC-DC Converters for high and low power Applications
boost converter, Buck & buck-boost Converter
1. Mosfet ( how Can I choose a mosfet for high &lower power applications ???? )
2. Diode ( which type of Diode should I use for high & lower power? )
3. Inductor ( for L I use Kg Method to design it by myself but I just do it upto calculation but not hardware. How can I design L on hardware??)
For Control I prefer I UC3843 IC but I want to use high Power do I need to change the this IC (UC3843) for should I use this same IC for its control ??
Thanks
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Turn on/turn off times "disguise" an "Rise Time"/"Fall Time" :)
(Turn on/off delays can be mitigated by appropriate control, rise/fall times can't.)
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I am required to build a optical VLC OFDM system and i understood the theoretical part well, how to start the implementation and hardware designs ? ,, I need to know how to build the hardware and the steps needed ? .. thanks in advance
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Optsim is a good option with examples
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For HDD, as per my understanding,
access time (approx) = seek time+ rotational latency + transfer time.
Now when data is contiguous then there is single seek time, single rotational time but for dispersed data it will take multiple seek and latency time. Even transfer time for contiguous data is less than or equal to transfer time of dispersed data since the data has a unit of reading data (called block) so for dispersed data it might need more block reads than contiguous data.
Please correct if my understanding about the HDD (Hard Disk Drive) is not correct.
I am not sure about the difference in access time for SSD (Solid State Disk) as I don't much about its working and the minimum unit of reading data.
Please throw some light.
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I'm going back to the subject. Today a few words about the SSD. Here you should not have a noticeable difference between continuous and distributed data. SSDs (and all other media based on Flash-NAND chips) always dissipate data. That is their principle of work. Dispersion of information between different circuits allows the entire media to accelerate. The SSD on the external interface also uses LBA addresses, but the Flash-NAND chip itself does not understand the term "sector." The basic unit for Flash-NAND is the page. The page size is related to the size of the data register and is equivalent to 1 to 32 sectors. At least in my practice I have not met bigger pages, but I expect that in the future they will appear.
But page size in bytes is not a simple multiplication result for example 32x512. The page is always bigger and contains ECC codes, various markers, sometimes other information necessary for proper media operation, and sometimes garbage, eg no meaningful strings 0xFF.
The controller writes the data to the pages in different layouts and then reads them from those layouts. You can be pretty sure that when you save a large enough file, parts of it will be in all Flash-NAND chips of storage media.
I have already mentioned that semiconductor media like SSDs also use LBA addresses. In their case, it is even better to see that the LBA address is not a physical address, but a translation layer between the physical addresses of the media and the file system. While LBA addresses on hard disks are quite closely related to physical addresses, SSDs are dynamically assigned and vary with each write operation. This involves the physics of writing in NANDs, which does not allow you to edit data, but requires erasing an entire block that counts multiple pages and then saving to a page by the page. So when you edit a file in an LBA address by changing one character, the SSD must perform a series of operations:
In simplification:
- reads the data block into the buffer
- means this block, as empty, intended to be erased,
- changes the contents of the block according to the command received from the computer,
- writes data to another physical block, and from the file system point of view these data still remain in the same LBA.
- the released block is deleted and you can save another data in it.
In fact, the process is much more complex. The algorithm must take into account requirements related to the speed and performance of the media and strive for a uniform consumption of the chips (wear-leveling). Because erase and write operations are destructive to Flash-NAND memory.
This way of writing and reading data makes you should not see the difference between continuous and distributed data. From a media standpoint, there is no such thing as continuous data. This does not affect its performance. Therefore, the SSD does not defragment.
Likewise, you should not see the difference in RAM. If you see it, you can actually search for cache or other data buffers (are you sure the requested data actually reads from the media, whether you get them from the buffer?), or in a system failure that may require additional time to correct errors or re-read.
Answers to your query do not look in the logical structure of file systems. The physical media do not understand of these structures.
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to enhance an image matrix, it is to be multiplied with another matrix. this is to syntheized
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When you use hdl languages you are describing Hardware. So  you could not think about the code but first about the circuit you want to implement and after you can use the code to implement that circuit
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Text file (LUT) Input/Output to FPGA Virtex 6 (ML605 board) 
I have an ML605 evaluation kit (Virtex 6 FPGA). I want to do the following: 
-Store/copy (binary) data from .txt file in BRAM (or preferably an external memory on the board).
-Read that data from BRAM, that will input for our module (e.g. input_1 and input_2).
-Store/write the output of module (e.g. sum) in BRAM.
-Export that data to .txt or any other file format from where we can fetch the binary values.
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Dear Wissam Marouche,
1. Do you have a processor in your design? If yes you can connect to a serial port (usb) to your system. In this way your processor cen receive/transmit data and read/write to BRAM with the processor.
2. Using JTAG I suppose you can do paratial reconfiguration and in this way you can change the BRAM contents.
Regards,
Jozsef Vasarhelyi
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What does the speed grade of an FPGA mean?
For example, a XILINX Virtex -4 FPGA has a speed grade of -10. What does it mean?
Can I use Speed grade as "-12" for core generation with a Virtex -4, 10 speed grade FPGA?
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The number doesn't represent anything in "real" terms - it's not nanoseconds of delay or anything like that (as it would on CPLDs). It's just a point of comparison: higher speed grades mean better performance. As @austin has said, the datasheet contains minimum specifications for each of the speed grades, so you know that (for example) a -12 device can handle at least 600Mbps DDR across the full temperature range while a -10 can handle at least 500Mbps (the -10 might handle 600Mbps too, but Xilinx makes no guarantee about that).
 You can safely generate a bitstream with a lower speed grade. For example, if your design meets timing for a -10 speed grade, you can run that on a -12 chip and it'll definitely work. The reverse is not true; if you take a bitstream that met timing for a -12 device and put it on a -10 device, you may encounter errors.
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Recently, the Hardware Profiles for my TQ4500 in Analyst 1.6.2 disappeared. I could not get them back. I could not save new profiles without reinstalling Analyst after which everything was fine until changing the Project Folder from default at which point Analyst crashed. Every time the program was opened the sotware crashed immediately after this. After reinstalling a second time the same occured. I'm stumped. Never seen the Hardware Profiles disappear before. If anyone has any advice or has seen this before I appreciate it otherwise, assuming I can resolve the issue I will update with how.
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The hardware profile may disappear if users fail to deactivate the hardware profile before turning the SelexION controller module on or off as failure to do so may result in the mass spectrometer entering an unstable state according to the Analyst 1.6.2 SW manual.
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Dear Researchers,
I need some material such as Books, Articles and so on for how can I write the image processing using VHDL?
I know how can I convert code but I need some material to write image processing using VHDL by own.
Thanks
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Dear researcher
please refer to this attachment if it is helpful for you.
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I am trying to run PSIBLAST on my computer (PSIBLAST 2.3.0+) using NR data bank (the latest version). However, it seems that PSIBLAST does not use more than 8Mb RAM therefore, it take so long (in fact, it does not complete its task). I was just wondering what is the reason? I am using Ubuntu (14.04). I even tried using JRE Java (uninstalled JDK Java and installed latest version of JRE) but still it does not work. Does anybody have the same experience? Can anybody help me?
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You can use top or htop command in terminal to see memory consumption details.
And make sure your application is x64 version. 32bits (x86) applications in some OSs may use just 3.2GB of RAM!
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I've been working with VHDL programming since a long time. And I want to know a good methodology of programming complex algorithms in  specially machine learning, signal processing.
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Thank you very much
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I am trying to implement an image fusion algorithm using wavelet transform on FPGA. I just have a vague idea of the project. But to implement a hardware design, I am unaware of the concepts that I need to know of how to accumulate the data and to process the data further as required like filtering of the image , etc. 
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Matlab is always to model system and we can have view of what I need to implement on hardware
Try to use an HDL(Verilog or VHDL ) for FPGA implementtaion. Recently a High level laguage such as Bluespecm system c and system verilog are useful for modelling the behavioural for the same system
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i want to fabricate a three phase Sen transformer. is anyone having hardware related papers related to Sen Transformer?
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Probably this book of the inventor of Sen Transformer will help
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Like RNS based addition and multipliucation ,can we do RNS based shifting and its hardware implementation?
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Shifting ,scaling  sign detection are the difficult operations  in RNS
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i want to implement array divider ckt...if any one working on it..please give your guidance
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No Ritika. I am working in multiplier for lossy applicaitons
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I am from software background and have a basic question.
I understand that CPU caches in multicore processors can snoop transactions on coherent system bus. They can also snarf the data flowing in some of the bus transactions.
Can the devices such as offload accelerators etc also snarf transaction data (based on some filtering criterion such as address ranges)?
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If it's called "offload", that usually means it's only connected via an IO bus (like PCIe), and not sitting on the processor's coherency fabric.  As such, it can't snoop coherency traffic.  (If this were not true, we could construct arbitrary-sized shared-memory machines using PCIe adapters - the performance might be terrible, but some people would be ecstatic about such a mechanism...)  If an accelerator is on the coherency fabric, I normally call it a coprocessor.
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Hello
I am designing my active power filter circuit in hardware design. I calculate the system parameters using the formula. I am confused on some points in my system designs.
1. The values in simulation are different than formula parameters in case of inductances.
2. How can I install the inductance towards the source side and load side? I mean do I have to use the transformer or separate inductance or source or line inductance?
3. My work is in active power filters, so I have to design the source and load prototype and which values I can used (Simulation one or formula one). 
Kindly guide me in this matter. Thanks
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Hello, i am the beginer  and i feel Gasim sir would  clarify this for you.
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I worked on a study about the implication of defensive programming over the reliability of software. The software in the study can be classified as being the software of critical application. We obtained very interesting results but I did not find, three years after the conclusion of the project, papers with a close relation to that subject. Is there no interest in development on this kind of study because the probability of random errors is low, or perhaps, this errors are corrected by hardware protection with sufficient effectiveness ?
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yes
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I know VHDL and did some projects, I am familiar with the hardware design concepts. What i need is a reference book in which i can get the rules in Verilog
something like
It is not possible to assign a wire data type inside always.
All ports are defined as reg data types.
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I found this book useful:
Fundamentals of Digital Logic with Verilog Design
by: Stephen Brown and Zvonko Vranesic
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I want to create my own hardware for WSN systems by modifying the open source hardware platforms like beagle bone or so.
Can somebody tell me which hardware platform provides all the hdl logic files and hardware design documents that can be modified to create your own hardware products.
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Maybe start here:
There are lots of open source hardware listed. But are you after HDL source or CAD files for some development boards? If the latter, maybe this is more helpful (there is some HDL stuff there too):
You could also have a look at the Raspberry Pi, which is a simple but reasonably powerful low-cost development board with schematics etc. freely available.
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    I  have  to  build  an  Hardware  Abstraction Layer  Between  my  device  and my Application for  understanding  its characteristics.
Suppose  a  ZigBee  device  or  Bluetooth  device  is  connected  to  any  host  machine , machine  should automatically  identify  the  device  by  using  the  polymorphic  method...and  runs  the  predefined  application
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Can  you  please  help  me  with  this   topic...   madam..?
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We are working on a project to baseline power consumption for a smart camera that can be configured for passive stereo vision or IR+visible multi-spectral.  The design does most of the frame by frame processing in an FPGA, but we plan to integrate a TI-OMAP running embedded Linux to integrate some machine learning algorithms we want to test along with just basic network uplink and management interface - the camera will be dropped off in locations in the Arctic, so very power constrained.  Just curious what sort of lifetimes people are seeing with Beagle Juice and how well the batteries work, lifetime, etc.  Also, has anyone used solar charging? (Not a great option in the Arctic in winter of course).
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Thanks - I will post on beagleboard.org/discuss - good idea!
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Dear Hardware Community,
I am starting my Master Thesis and I would like to explore certain hardware structures and create accurate, parameterized high level models for it. I still haven't decided aon the details of my work and in this formative stage I would like to ask the community for useful resources.
A number of papers that I browsed so far are 5 to 10 years old and I am curious about the most up to date items.
I would also like to ask which kind of tools are commonly employed for power consumption estimation (both low level and high level).
Any information would be much appreciated.
Yours,
Marcin Rutkowski