Questions related to FPGA Programming
Hello Everyone, I want to perform division operation in Verilog - HDL. Please suggest me an algorithm for division in which the clock cycle taken by division operation is independent on input. That is for division of any number a (a can be any number) by b(b can be any number),same number of clock cycle wil be taken by division operation for different set of a and b.
I started learning VHDL and FPGA Programming. I have watched tutorials regarding this, but that were just basic concepts.
Can someone please suggest me some good books for that?
I shall be very thankful for that.
I want to implement a 5 input and 2 output combinational logic using single 5x2 LUT in vertex 5 or vertex 6. Is there any way to implement that?
Is it possible to read-back from an already programmed FPGA? If possible, kindly explain the technique with EDA-CAD tool support for this operation.
Thanks in advance.
I have developed a new interferometry system that works with an atomic clock. Now I want to unwrap my detected signal by an FPGA program that should be timed with the atomic clock. The question is whether I can use a myRio instead of an FPGA or not.
Compare readback data to the RBD golden readback file or compare readback data to the configuration BIT file? and how to perform the comparison?
I need to develop an algorithm which runs on microblaze softcore and scans the FPGA device and provides free resource information (resource : FF/register/mux//BRAM/DSP)
I want to do stereo vision, and I have a FPGA board DE1-SOC, but I dont know what type of camera is better, I always have used a webcam with my laptop, but I saw other FPGA proyects with different camera interface. thanks for helping.
I have a question on "Online" VS "Offline" learning methods. In my thesis I have already simulated an "Online" method to train an RBM to develop a deep model (a DBN network) which is consisted of LIF neurons and uses spikes to train and test the model.
In my simulation with "Online" I mean that the model uses same platform for train and test. Indeed the model:
- Can be trained for any type of applications.
- The weights will be adjusted during the train process with input training spikes.
- and, in contrast with the "Offline" method which uses the trained weights (that have been adjusted and transferred to the test platform), the "Online" method uses same network for train and test.
Here, I want to know what the project means with "Online"? (Dose it mean same as what I have done in my thesis?)
Thank you very much.
Presently, I am trying to program FPGA in USRP E310 for MIMO application.
This is the link of its online datasheet.( https://www.ettus.com/content/files/USRP_E310_Datasheet.pdf )
I am trying to edit the FPGA program in verilog as per my requirement. I have downloaded the open source code from Github (https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300) and building the bitstream from source. Later, I upload the bitstream to FPGA using uhd_usrp_probe command.
So far, I could toggle the frontend LEDs of USRP E310. I am trying to transmit Logic1 signal to one of the Transmitter ports. However, I can not see any output on the oscilloscope. Is there any possibility that frontend of USRP is not configured properly? if yes then, How to configure the USRP to transmit and receive the signal?
I wish to achieve the objective by only FPGA programming without using Gnu radio or any other software.
Kindly guide me if I am doing something wrong. It would be great if you can list down other data ports to be controlled.
Please tell me if my approach is correct and steps to be followed to program the FPGA correctly.
Any suggestions are welcome.
Hope that all of you will be fine.I am trying to implement the motion estimation algorithm(block search) for video compression in FPGA.I am trying to implement memory reusability concept but I have a problem in reading column I can read row of memory in one clock but I can't read column in one clock.Can anyone suggest any method for reading column in one clock.Thanks in advance
Vibation analyzer in Measurement, Diagnosis and Speech Recognition use a state machine for event-driven control. Which programming language is the best for a software-state-machine in event-driven audiosignalprocessor?
sir, I am trying to do following -
I am giving a signal x(t) as input which has 1000 samples.(i have taken one signal and samples it using the matlab and got the points in form of integars)
Now i have extracted the local maxima and minima of that signal.
By using local maxima i have calculated the upper envelope by using linear interpolation and same i have done with local minima to calculate the lower envelope and then i have taken the average of the upper and lower envelope and have got a signal m(t)
now i have to calculate a new signal h(t) which will be
h(t) = x(t) - m(t)
I have to repeat all above three times, means now again h(t) will be the input signal,
x(t) = h(t)
How to repeat the steps? I have written the code separately for each step. Should i use FSm? If i am going to use FSMs then how can i instantiate the modules in FSMs? Please suggest. I ma in big trouble
I want to implement a circuit in Verilog but one of its inputs Is n-bit and based on that input the number of instantiated modules will be vary, so can I create an array of instances that its size will be calculated based on the width of the noted input ?? or are there any ways other than using arrays to do that at all ??
did any one have a UCF file for FPGA xillinx model zynq 7000
iam using ise to program this fpga my code is working will but in mapping process it is stop because it needs ucf file for zynq 7000
A real time visual attention system based on the human visual attention, it's better to use a only a FPGA, GPU or FPGA+dual core ARM?
i need to do a project about partial reconfiguration in fpga. i use a ise 14.2 software in my pc, when i run planahead and then try to make a new project, the partial reconfiguration enable option is not in the step two that should be, how i can solve this problem?
I am implementing raddix 4 fft on xilinx virtex 6 fpga. For that I tried some scaling schemes but I did not get satisfactory answer. so please suggest some good scaling scheme for that.
How to implement rounding in fpga program?
I want to execute the encryption algorithm on ML 506 board.So how can I give inputs to board and how can I receive the output from the board. In some papers they mentioned it is possible using HYPER TERMINAL. Can anyone know this?
i use xilinx vivado 2014.4. While declaring the inputs and outputs if i mention a port as inout ., a type mismatch error occurs.But if i replace inout with buffer the error is cleared.Why does it happen this way.My application requires a port to act as input once and later it should act as an output.
I am implementing raddix-4 DIF generic algorithm (N = 64,256,1024,4096,16384) on xilinx virtex-6 fpga. I have got two schemes for the twiddle factor generation for that.
1) generate sin and cos by cordic and store it in memory and call it in the process to multiply with the addition of inputs. In this I can do parallel tasking to increase speed but multiplication increases vector length drastically.
2) use cordic rotation for complex multiplication. This will not increase vector length but will reduce my speed. Xilinx CORDIC ip core takes phase input in 2QN formate but my maximum multiplication (2*π*k*n/N) answer lies in 3QN formate (around -4.71). So how can I solve this problem?
I wan to see output FFT through serial port from fpga to computer. How can I do that? Want to implement uart. How can I get output in computer?
what are the parameters and conditions which have to be considered for one to decide whether to use a micro-controller or an FPGA as a processor?
I used the xpower analyzer to estimate both dynamic and quiescent power consumption of my design, but when I performed it for different codes, I got the same value for all. I did the .pcf and .saif files uploads, but I don't know how to upload the settings file, i.e. I don't know how to generate the settings file. Am I missed some part of the procedure?
I am using SPARTRAN XC3S50 PQG208EGQ1117 D4238638A 4C FPGA for synthesis and simulation process. Where will the speed of the circuit be shown?
Port mapping refers to the concurrent statements and process refers to the sequential statement. If there is a data dependency between the blocks of the concurrent statements, each block itself is a concurrent statement and the entire flow becomes sequential because each block output goes to the input of the next block. In that case why can't we include these concurrent statements inside the process? I am confused and I don't know the reason for this.
I want to dump my project code to FPGA board. Please can anyone provide me the input pin numbers to Xilinx SPARTRAN XC3S50 PQG208EGQ1117 D4238638A 4C?
I want to use synopsys/cadence tools such as synopsys design compiler, synopsys prime time, cadence SoC encounter for place and route and synopsys tetramax ATPG. Are any of the mentioned tools freely downloadable?
I am doing a project related to image processing concept. I developed the code in Impulse c language. I can implement my designs in Spartan 3 Tyro plus (XC3S200) FPGA using microblaze processor. Is it possible to simulate the same in any of the simulation software (XPS/SDK, Model sim, ISIM, etc.)?
Please let me know what the relation is between the number of slices used in FPGA and maximum frequency. I saw that if the number of used slices is increased, the maximum frequency along with throughput is increased. Can anyone tell me why this happens? Why is the maximum frequency increased with respect to the number of slices used?
I would like to do partial reconfiguration with Xilinx system generator tool generated code. I have developed a physical layer model in Xilinx system generator. I found two of the blocks in this model to be of partially reconfigurable modules (I have different functionality for these two, no of IOs are same). I generated the code.
Can you please tell me if anyone has had success with this approach (with sysgen tool)?
I have a code for face detection using OpenCV with C++ language, and I have to implement it using FPGA Altera. Is there any software, or program that would synthesize my C++ code inFPGA?
I did a survey of and found the following noise that cause errors in transmitted data,attenuation of signal, cross-talk, cross coupling ,echo, skew of the signal etc. I am trying to model the data corruption that occurs because of these. Can anyone suggest other different types of noise and how they affect the data being sent?