FPGA Programming - Science topic

Here is a useful link that I found, with the block diagrams and Verilog codes

Even though Python is not a concurrent language as VHDL or Verilog, you may use MyHDL which is a Python to VHDL/Verlilog converter. I never tested this converter, but here are the references: https://en.wikipedia.org/wiki/MyHDL and http://docs.myhdl.org/en/stable/manual/conversion.html

Regards,

Interesting -following .

Intel® FPGAs and Programmable Devices / University Tutorials

@ Sumathi Gokulanathan

Not only you can read what you downloaded in the FPGA, which is known a readback configuration, but you can also readback what actually is running on the FPGA, with readback capture. Both are availabe from Xilinx from many years ago. The first information is actually what comes from what you have in your hard disk (the bitstream), and this information is saved in the "configuration memory" of the FPGA. The second information is read from actually the memory elements in the FPGA (flip-flops, BRAMs and LUTRAMs), you cannot read combinational functions, and this information can be capture on a single rising edge of the clock, and then save that information in a file. You may read as an example the UG191 document (Virtex-5 FPGA Configuration User Guide) from Xilinx for old Virtex5. It is the most complete document about configuration the FPGAs from Xilinx. For newer families, you can find similar documents. Also, you may read my research papers about this topic.

JPG format is too intricate, coding hardware to handle it is not trivial. If this is an undergrad project, you are shooting too high.

There is however a middle-ground solution. Use a softcore (e.g. microblaze) and a memory, those two fully coded in vhdl/verilog. Then write software that runs on the softcore and that software will do the actual work of parsing and understanding the JPG format.

Most IoT applications require a processor core, memory, networking chip (BLE/WiFi/Zigbee etc.) and a controller to actuate external devices. The processor core in IoT can be replaced by FPGA. FPGA could be coupled with an ARM processor to leverage higher-level software functions such as Web servers, if higher level of processing is required. For more information of FPGA in IoT, read the following article: “Sensor Systems Based on FPGAs and Their Applications: A Survey”.

i did not understand what you want do exactly

I think you cannot compare a FPGA chip with MyRIO.

A FPGA is a gate array where one can write the logic connections in a program written in VHDL development platform. These are the silicon chips, bare silicon chips!

MyRIO, in contrast is an embedded system that has an FPGA as a system component, but mainly wired around an ARM microcontroller with various analog and digital I/Os.

If you are talking about the interferometer for cross correlation of the input RF signals with various phase differences, a dedicated FPGA chip from a suitable vendor such as Xilinx, Altera etc. would be an ideal solution.

Excuse me for my own interpretation that by interferometry you meant the radio interferometer used to detect distant radio objects in the sky, a radio astronomy business!!!

I also have that doubt. If someone answers you, you'll be helping them with that doubt.

4

By AccelDSP Synthesis Tool

On-line learning in the said project is about learning on the go. Whenever there is a new situation the neural (network) will improve its knowledge by learning the additional knowledge to handle a new situation. Offline is more about static where a model is trained in the start with all the possible/available situations of the environment and then it is deployed. 

In other words, post-deployment need-based (re)training of model during its lifetime, as the new situations arise, is termed as on-line training. The aim is to make a model adopt autonomously to cope with such cases. 

 For the DWT transform implementation, in case you are using Xilinx FPGAs, you can intantiate the  FFT  as well as complex multipliers IPcores. I suggest you to adopt fixed-point format for your arithmetic operations. 

I think you need to localize your problem first, and make sure each step gives you the valid result. It could be many possibilities from this point.

Cheers

it seems like you need to use matrix buffer which mimic the memory 48x48. You need to ensure the clocking period to comply the design specification. Or if you need those data row and column at the same moment, you can copy the memory data into 2 identical memories, one with transposed format.

Dear Oussama Kerdjidj,

Please find my paper you requested at the publisher page:

Best regards

Marek Gorgon

Sir,

Everyone is best with the language they know the best. You mentioned a state machine, I would suggest LabVIEW using a Queue Driven State Machine (QDSM) approach. In this approach, you dedicate a Queue to each major function (GUI Input, GUI Output, File input, File Output, Data Acquisition, Preprocessing data, processing data, report generation, etc). Each of these Queues will be able to communicate with each other queue through queue commands or events. The entire project could have a script queue that would allow it to be scripted from a text file (something I often do to allow reusability of the code).

I find that I can handle projects with over a thousand subroutines / SubVIs  by myself using this method. So little outside help is needed once you get some experience with it.

Good Luck!!!

The best way to solve your problem is using Mealy FSMachines, becouse the change of the state depends of the imput values. In this case the imput values (true/false) can be the convergence criterion and the termination criterion.

Most simulation, synthesis, and other tools now support the "generate for loop" that's already been mentioned. The alternative if you have older tools is called an "array of instances." It looks something like this:

parameter N = 8;

output [N-1:0] dout;

input [N-1:0] din;

input [1:0] cntl;

mysubmodule [N-1:0] sub_inst (.Z(dout),.D(din),.C(cntl));

For this example, assume the submodule's Z and D are single bit and C is two bits wide. Connection signals that are the same width as the single instance port width (C in this example) are connected together to all instances, while those that are different (i.e. wider) are bit sliced to each instance. So this example unrolls to the equivalent of the following:

mysubmodule sub_inst0 (.Z(dout[0]),.D(din[0]),.C(cntl[1:0]));

mysubmodule sub_inst1 (.Z(dout[1]),.D(din[1]),.C(cntl[1:0]));

mysubmodule sub_inst2 (.Z(dout[2]),.D(din[2]),.C(cntl[1:0]));

etc...

You can contact coreEl , Bangaluru,India

Your question is not well framed. What you want to design is HARDWARE for matrix inversion using Verilog as an HDL. Verilog is not a programming language.  You may want to ask why one may want to invert a general matrix in the first place. Is it for solving a set of linear equations? Can there be an alternate method for solving a system of linear equations? You will probably benefit by looking at the work on systolic arrays.

The key to succeed in this kind of project is to properly partition the application, which blocks will be executed in the dual core ARM and which blocks will be executed in the FPGA fabric. You must know the formulas of your algorithm(s) and see if they show dependency or not with respect to time. If algorithm(s) do not show such a dependency, they can easily implemented in the FPGA using VHDL. If the algorithm show dependency, you must look for ways how you can convert a serial algorithm in a parallel version and take advantage of languages such as VHDL. Another option is to write high level language as C/C++ and use OpenCL implementation from Altera or Vivado HLS and see what hardware produce, but note both OpenCL and Vivado HLS have limitations, and not sure if the hardware those tools produce will be efficient. Finally, use the dual core ARM just as a control unit, to start/end  tasks in your algorithm.

I would be most interested to know how you get on.

I tried doing Partial Reconfiguration for the Virtex 6, but hit a problem that I couldn't make the reconfigured area bigger than a single clock region. As we wanted to reconfigure everything but the PCIe interface used to communicate with the chip, this was as show-stopper bug. As Xilinx have stopped supporting PlanAhead in favour of developing Vivado and Virtex 7, they weren't prepared to fix this bug in PlanAhead.

As we had paid for a partial reconfiguration license that we couldn't then use due to this bug in PlanAhead, we were pretty annoyed about all this.

Thank you so much sir for your help. Your work is really very helpful to me..

If your purpose is to conect your crypto setup so you can automate your analisys, It is not something you will find a ready-made solution. First, as Bhoopal has said, it is important to know if you will need to read some information that can not be made available as an input or output of the FPGA. For instance, if you are willing to make a DPA attack some way to receive power data must be available. In this case the problema is very different and you will need a special board with external circuitry to read this data. Assuming you only want to feed plain text to your circuit and get the encripted data out you will have to make two things: 1) First you have to design a block (using some HDL of your preference) that will receive octets and assemble the input word of your crypto block (for instance 64bits, 128bits, etc, depending on your algorithm). The same will have to be made for your outputs: a block will take the words and serialize then in groups of eigth bits (octets). Since this "connection block" will interface to your design it must be custom made by you. 2) You must include a UART that will take each octet and transmit serially, and also will receive serially and convert data to octets. Fortunatelly, a UART is a ready made block and you will find many in the Opencores.org as Maryam said. You can use a very simple one (I believe there is one called tinyUART that works well). Usually to send data your "connection block" will provide one octet, sinalize some 'send' input of the UART and wait untill the octet is sent (there is always a UART pin that will sinalize when ready somehow). After that, it will send the next octet and so on. To receive data, the UART will indicate in a pin that a octet has arrived and your "connection block" will read the octet from another set of pins. If you choose a simple UART and keep your communication protocol simple the "connection block" is a relativelly small state machine and a few registers. This proccess does, however, recquires some experience with HDL and FPGA. If you choose a SOC FPGA with internal microprocessor core there is an alternative: you can map your cryptographic block inputs and outputs to memory and use the development tools of the system to access the internal memory. There are different procedures to to this in each manufacturer tool and it usually requires the inclusion of some sort of predefined IP core in the system assembly tool (f.i. Qsys in Altera) .  Although I think using a UART may be better if you are not used to your SoC development tool, there are advantages to each approach.

In VHDL it is not possible to read a output (signal out in entity). Then you have the type buffer, with is a output, but it is possible to read. But iti is two problems:

- One signal declared as buffer can not be connected to a signal out.

- buffer is a reseved word in some tool, like Xilinx. That is a special component for the clock signal! Michmach

Now, a signal declared as inout is a realy pin used as input and output. You can read this signal. But that use a three-states buffer. If you want only read a output signal, you need to defined a internal signal:

on entity:  output_to_read_o : out std_logic

on architecture:  

  signal output_to_read_s : std_logic

you need to assign output_to_read_s instead the output output_to_read_o and you assign output_to_read_o <= output_to_read_s; Then you can read the internal signal. You get the same fonctionnality as the buffer but without error.

You can the explanation in french in my presentation on page 29 to 31:

If I understand correctly, you have the problem, that you give the DSP48s a 18bit and a 18bit vector and get out a 36bit answer?!

I am doing the same on our system and I would recommend looking at the input and  output. Our sine and cosine for example are always < 1. In consequence even though the tools will give you a 36bit output the top bits will always be 0, so you can just chop them off(be careful not to chop sign bits).

The bottom bits are more a question of what the accuracy of your inputs is. Generally if the inputs are only accurate to 18bits, then you do not need to keep 36bit, but can chop off at least down to 20bits without increasing the error on the output significantly (all your are essentially doing is chopping off the already erroneous bits and thus only changing the nature of the error).

Hope this helps.

Rabbia,

It all depends on the bandwidth you want between the FPGA and the computer. For moderate bandwidth, typically done is following:

- Implement an SPI interface on the FPGA.

- Use FTDI device (look for it on the internet), to translate SPI to PC USB.

The main and the most significant difference between the microcontroller and the FPGA is that FPGA doesn’t have a fixed hardware structure, on the contrary it is programmable according to user applications. However processors have a fixed hardware structure. It means that all the transistors memory, peripheral structures and the connections are constant. Operations which processor can do (addition, multiplication, I/O control, etc.) are predefined.And users make the processor do these operations "in a sequential manner" by using a software, in accordance with their own purposes.

Hardware structure in the FPGA is not fixed so it is defined by the user. Although logic cells are fixed in FPGA, functions they perform and the interconnections between them are determined by the user. So operations that FPGAs can do are not predefined. You can have the processes done according to the written HDL code "in parallel" which means simultaneously. Ability of parallel processing is one of the most important features that seperate FPGA from processor and make it superior in many areas.

Processors are generally more useful for routine control of a particular circuits. For example, using FPGA for simple functions such as turn on and off any device from a computer may be overstated. This process can be easily done with many ordinary microcontroller (PIC series, etc.). However, FPGA solution is more reasonable, if you want to process on a high-resolution video data on the computer.

Because video processing requires processing large data in high speed and make these types of applications are very suitable for FPGA that is capable of parallel processing.

Since the user can determine the hardware structure of FPGAs, you can program FPGA to process larger data with few clock cycle.

Whereas this is not possible with the processor. Because data flow is limited by processor bus (16-bit, 32 bit, etc.) and the processing speed.

As a result, applications that requires more performance such as intensive data processing FPGA has come to the fore, and processor / microcontroller has come to the fore for routine control operations.

Nevertheless, processors / microcontrollers can be embedded into the FPGA since they are logic circuits in fact.

Thus it possible to define and use processor and user-specific hardware functions on only one chip by using FPGA. This solution gives engineers the oportunity to control the hardware because of its great flexibility.

You can modify and update whole design (FPGA on the processor and other logic circuits) by only changing the code on FPGA, without any change on circuit board layout.

In this way, you can add different functions, improve performance and make your design resistant of time without having to redesign the cards.

As far as I remember there is a paper that covers how to obtain the netlist from the bitstream: "From the bitstream to the netlist"  by Jean-Baptiste Note and Éric Rannaud (http://dl.acm.org/citation.cfm?id=1344729) or https://www.researchgate.net/publication/200065272_From_the_bitstream_to_the_netlist

Another paper is "BIL: A tool-chain for bitstream reverse-engineering" by Florian Benz et al. (http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6339165). You can get the open source of the project in the following URL: https://github.com/florianbenz/bil/

Hope this helps

Hi Sumathi Gokulanathan,

Let me first tell you the simple procedure of using the Xilinx XPower Analyzer (for understanding) and then some information on that.

Implement the top module using the Xilinx ISE

Open the XPower Analyzer listed in the Place and Route tab of the Design sub window

After the design gets loaded 100%, in the 'Report Navigator' sub window of the XPower Analyzer, click on the 'By Clock Domain' listed in the 'Details' tab.

A list of the clock signals and the clock driven synchronous signals appears in the window pane, by the side if the 'Report Navigator'.

If your design uses clock, change the value of the Frequency of the clock, in the concerned field. (The default value given is 0 MHz)

After changing the clock frequency to the desired value, click on the 'Update Power Analysis' icon in the Toolbar.

After the update gets finished, click on the summary, listed in the 'Report Navigator', to get the updated power values.

NOTE: To measure the power values at different frequencies, restart the XPower Analyzer to get correct values. If you change the frequency many times at a single run, the power values get added up as the algorithm (according to my knowledge) preserves the previous values of power to add them in calculating the power values of next frequency.

All the best,

Regards

NP.

You can use the BlockRAM (i.e. for Xilinx Spartan series) as registered ROM memory by tying the write-enable input to low. You can do this by directly inferring the BlockRAM as ROM in the code and fill-in the coefficients directly or use the Xilinx's CORE Generator system where you can generate a special ".coe" file which initializes the ROM contents and assign it. For example you can check the XAPP463 "Using Block RAM in Spartan-3 Generation FPGAs" application note. Then you can use the memory address as the matrix cell index and the memory contents at this address as matrix cell value. And maybe this will be the fastest and easiest way. And you have various options for the memory organization (for example 4kx4, 1kx16, 256x72 and many others) so you can either write normalized values for that Sine and Cosine functions and use them as integers or write fixed-point arithmetic.

Some example of how to use the RAM/ROM can be found in "FPGA Prototyping by VHDL Examples" by Pong P. Chu (chapter 11.4.3 "ROM"). (His book is also avalaible for Verilog.) I used Xilinx and Verilog but other manufacturers, like Altera and Lattice, offer similar possibilities of implementing a ROM.

If your matrix changes dynamically it may be worth giving a try of the COordinate Rotation DIgital Computer (CORDIC) algorithm which is capable of evaluating many elementary trigonometric functions including Sine and Cosine. I have not personally used it but I know there are few free versions of CORDIC cores at opencores.org website.

Hope this can help you.

Best regards,

    Yassen

One more thing

Timing report after synthesis is not very accurate.

It would be much better to take timing results after place and route. these values tend to be more realistic, as it is estimated after implementing the design routing for the target FPGA.

Good luck

Port map is only used for physical signals and while process is a virtual operations that use variables which requires zero time to execute ( concurrent statements)

After performing the synthesis, a detailed report of the synthesis will be generated, just just scroll down the report, you can see the maximum clock frequency supported by the your system.

Window-based operations are very good candidates for hardware implementation. You can organize the incoming pixel stream as shown in this article:

This opens a way for the implementation of a lot of image image filtering and feature detection algorithms.

Hi folks, just to clarify, with PlanAhead you may implement partial bitstreams, but the partial reconfiguration (PR) flow given by PlanAhead provides only the initial partial bitstreams for the partially reconfigurable module (PRM). Even though Xilinx says that you can change the functionality of PR regions (PRRs), by dynamically download partial bitstreams on the same PRR, I consider that dynamic partial reconfiguration is more than that. Dynamic PR allows you to modify the partial bitstreams without going through the long PR flow. You may search literature about this topic, and take a look at my publications. Regards,

I do not think it is possible to download them for free. But many be you can interact with the application engineer and get some help from them.

More details I will mail you by evening

The Theory is in MacWilliams and Sloane; check also McEliece theory of Information and coding. This being said implementation is probably a pain.

No..I mean the next level of Built-In-Self-Test...Which is Built-in-self-repair..I have been working on Built in self test for past years....Now I want to work on Built inf self repair.

Thanks to all. I got my Answer. It's just a coincident. It's all because of my logic and number of LUTs used.

Hi..

There is no such a tool to convert matlab code into VHDL code.. Eventhough, if it is, it will produce inefficient code.. not all the matlab generated VHDL codes are efficient. its better to try it in vhdl itself, instead of conversion.

In order to answer, I will use Xilinx terminology. Sorry if you plan to use a different technology, you will probably be able to adapt some issues/terms/techniques.

Reconfiguration speed is dependent on:

- How many frames you need to write. Of course, frame length is also important. In modern Xilinx FPGAs, frame height corresponds to one clock region, but this is family-dependent (16 CLBs in Spartan-6 20 in Viertex-5, or 50 in Zynq).

- Which port you use. The fastest is the ICAP, which let the FPGA to reconfigure itself from the internal logic.

- The ICAP can be overclocked in some families (See Claus paper in ARC 2010), so time might be reduced.

- With heavy ICAP bandwidths, the provision of dato into the ICAP becomes a problema. If data to reconfigure is very small, think about having it in BRAM. If it is larger, you might perhaps off-line download the dynamic bitstream content from a flash into a DDR or similar, and by using DMA Access, read directly from there and put it into the ICAP. If you need to directly download from a flash, a parameter in the header determines the clock speed to use. Try to accelerate it as much as your design supports.

- Having compressed bitstreams helps for complete reconfiguration (i.e. at boot time), but it is not that useful for partial BSs.

- You may also think about Reading from the ICAP, relocate the bitstream by changing the addressing, and write again. This method does not impact memory utilization bandwidth, but Reading through the ICAP does not permit that much overclocking as when writing.

In ReCoSoc 2012 we have a paper on providing partial dynamic reconfiguration into a Spartan-6 device. Also, we show that, the fastest, the less energy consunption. In DSD 2010 we report the use of a peripheral for fast reconfiguration. You may also read articles form Michael Hubner or Jim Torrsen, or the above mentioned from Christopher Claus.

for modeling you can use MATLAB-Simulink, if you want to implement it into FPGA you need either separate the analog part from the design (off-chip components) and synthesize the rest into the FPGA chip. or you need to look for fully digital alternatives. The idea is that you can't control any of the gates parameters (e.g. voltage level) and thus you can't implement analog circuit.

check this great resource for all FPGA projects, they have various image\video processing projects

i am not sure and good at verilog but here is a link for VHDL code generation of RS encoders.

The article is good with complete GF(256) RS package.

Thanks waris and afaq for the answers

As far as I am concerned, openCV offers some GPU functions instead. The functions detect and describe interest points extracted from an image with several kind of appearance descriptors, including SIFT, SURF etc. If you use C/C++ , you can implement very fast a test code and see if it works for you.

Check out here:

Hi Srinivas,

I haven't used Xilinx SysGen for partial reconfiguration. However, I have used partial reconfiguration tools extensively for my research. You may wish to read my paper on partial reconfiguration "FPGA-Based Reconfigurable Hardware for Compute-Intensive Data Mining Application", which describes how it is being done. This paper received the best paper award.

Hope this helps.

Darshika

The short answer is no.

While there are C-FPGA tools (Vivado from Xilinx, OpenCL from Altera, CoDeveloper from Impulse, and ASIC/FPGA high level synthesis tools from Mentor-Synopsys-Cadence, none of them will take OpenCV code and push-button synthesize it.

That said, good methodologies exist for doing <C++>-C-FPGA-C-<C++> work on those portions of your code that need to be accelerated.

You stated that you "have to implement it using FPGA Altera".

What do you have to implement? What part of your application?

Usually, one accelerates the slowest part of the <OpenCV> application that is a bottleneck for your application to achieve real-time or good throughput performance.

This comes from having examples that and profiling that show what the slowest part of the application is. Do you have that information?

alan

I can give you answer if you can tell me the version of Quartus II

Not only noise reduces the quality of the signal and the eye diagram, also bandwidth limitations

have impact on the eye opening. This type of degradation is known as intersymbol interference (ISI) due to the effect of both low-pass filtering and high-pass filtering limitation.

The deviations of the threshold voltage crossings from their ideal position in time is called jitter. Jitter may influence the optimal sampling instant of the decision circuit. Just like noise and ISI, too much jitter closes the eye opening and introduces bit errors. The total jitter may be composed of deterministic jitter and random jitter. Examples of deterministic jitter are data-dependent jitter and duty-cycle distortion jitter. Data-dependent jitter is produced when the signal edge moves slightly in time, depending on the values of the surrounding bits. It can be caused for example by an insufficient bandwidth or by baseline wander due to an insufficient low-frequency cut-off. Duty-cycle distortion jitter occurs if the rising and falling edges do not cross each other at the decision threshold voltage. Random jitter is, in contrast to deterministic jitter, not related to

any data pattern or any deterministic cause. It is produced, for example, by noise on edges with a finite slew rate. It can also be caused by carrier mobility variations due to instantaneous temperature fluctuations. Besides the data jitter described above, also clock jitter exists. This jitter is important in the clock and data recovery circuit where the decision process takes place. For instance, if the sampling instant of the decision circuit varies with time, an increase in BER might occur. In the frequency domain, the jitter counterpart is called phase noise. It is extremely important for the design of oscillators and clock and data recovery circuits