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# FPGA Programming - Science topic

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Hello Everyone, I want to perform division operation in Verilog - HDL. Please suggest me an algorithm for division in which the clock cycle taken by division operation is independent on input. That is for division of any number a (a can be any number) by b(b can be any number),same number of clock cycle wil be taken by division operation for different set of a and b.
Here is a useful link that I found, with the block diagrams and Verilog codes
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Hello everyone, can we use python as a programming language for FPGA? thank you
Even though Python is not a concurrent language as VHDL or Verilog, you may use MyHDL which is a Python to VHDL/Verlilog converter. I never tested this converter, but here are the references: https://en.wikipedia.org/wiki/MyHDL and http://docs.myhdl.org/en/stable/manual/conversion.html
Regards,
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Hello Everyone,
I started learning VHDL and FPGA Programming. I have watched tutorials regarding this, but that were just basic concepts.
Can someone please suggest me some good books for that?
I shall be very thankful for that.
Thank you!
Interesting -following .
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I am new to FPGA programming I need to use Intel Quartus for my project.
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I want to implement a 5 input and 2 output combinational logic using single 5x2 LUT in vertex 5 or vertex 6. Is there any way to implement that?
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Hi all,
Is it possible to read-back from an already programmed FPGA? If possible, kindly explain the technique with EDA-CAD tool support for this operation.
@ Sumathi Gokulanathan
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I want jpg to bmp converter module in my vhdl project.
How can i write this? and where should i started?
JPG format is too intricate, coding hardware to handle it is not trivial. If this is an undergrad project, you are shooting too high.
There is however a middle-ground solution. Use a softcore (e.g. microblaze) and a memory, those two fully coded in vhdl/verilog. Then write software that runs on the softcore and that software will do the actual work of parsing and understanding the JPG format.
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Most IoT applications require a processor core, memory, networking chip (BLE/WiFi/Zigbee etc.) and a controller to actuate external devices. The processor core in IoT can be replaced by FPGA. FPGA could be coupled with an ARM processor to leverage higher-level software functions such as Web servers, if higher level of processing is required. For more information of FPGA in IoT, read the following article: “Sensor Systems Based on FPGAs and Their Applications: A Survey”.
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hi i need help to fully implement an USRP like B210, but ettus site is a little complicated, can i change the FPGA program by HDL language as i want?
i did not understand what you want do exactly
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I have developed a new interferometry system that works with an atomic clock. Now I want to unwrap my detected signal by an FPGA program that should be timed with the atomic clock. The question is whether I can use a myRio instead of an FPGA or not.
I think you cannot compare a FPGA chip with MyRIO.
A FPGA is a gate array where one can write the logic connections in a program written in VHDL development platform. These are the silicon chips, bare silicon chips!
MyRIO, in contrast is an embedded system that has an FPGA as a system component, but mainly wired around an ARM microcontroller with various analog and digital I/Os.
If you are talking about the interferometer for cross correlation of the input RF signals with various phase differences, a dedicated FPGA chip from a suitable vendor such as Xilinx, Altera etc. would be an ideal solution.
Excuse me for my own interpretation that by interferometry you meant the radio interferometer used to detect distant radio objects in the sky, a radio astronomy business!!!
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Compare readback data to the RBD golden readback file or compare readback data to the configuration BIT file? and how to perform the comparison?
I also have that doubt. If someone answers you, you'll be helping them with that doubt.
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I need to develop an algorithm which runs on microblaze softcore and scans the FPGA device and provides free resource information (resource : FF/register/mux//BRAM/DSP)
4
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I want to do stereo vision, and I have a FPGA board DE1-SOC, but I dont know what type of camera is better, I always have used a webcam with my laptop, but I saw other FPGA proyects with different camera interface. thanks for helping.
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By AccelDSP Synthesis Tool
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Dear all,
Hello
I have a question on "Online" VS "Offline" learning methods. In my thesis I have already simulated an "Online" method to train an RBM to develop a deep model (a DBN network) which is consisted of LIF neurons and uses spikes to train and test the model.
In my simulation with "Online" I mean that the model uses same platform for train and test. Indeed the model:
1. Can be trained for any type of applications.
2. The weights will be adjusted during the train process with input training spikes.
3. and, in contrast with the "Offline" method which uses the trained weights (that have been adjusted and transferred to the test platform), the "Online" method uses same network for train and test.
Here, I want to know what the project means with "Online"? (Dose it mean same as what I have done in my thesis?)
Thank you very much.
Sincerely yours,
Mazdak Fatahi
On-line learning in the said project is about learning on the go. Whenever there is a new situation the neural (network) will improve its knowledge by learning the additional knowledge to handle a new situation. Offline is more about static where a model is trained in the start with all the possible/available situations of the environment and then it is deployed.
In other words, post-deployment need-based (re)training of model during its lifetime, as the new situations arise, is termed as on-line training. The aim is to make a model adopt autonomously to cope with such cases.
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I am struggling in implementing image processing algorithms on FPGA. If anyone has tried implementing DCT, DWT on an FPGA please help me out.
For the DWT transform implementation, in case you are using Xilinx FPGAs, you can intantiate the  FFT  as well as complex multipliers IPcores. I suggest you to adopt fixed-point format for your arithmetic operations.
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Hi all,
Presently, I am trying to program FPGA in USRP E310 for MIMO application.
This is the link of its online datasheet.( https://www.ettus.com/content/files/USRP_E310_Datasheet.pdf )
I am trying to edit the FPGA program in verilog as per my requirement. I have downloaded the open source code from Github (https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300) and building the bitstream from source. Later, I upload the bitstream to FPGA using uhd_usrp_probe command.
So far, I could toggle the frontend LEDs of USRP E310. I am trying to transmit Logic1 signal to one of the Transmitter ports. However, I can not see any output on the oscilloscope. Is there any possibility that frontend of USRP is not configured properly? if yes then, How to configure the USRP to transmit and receive the signal?
I wish to achieve the objective by only FPGA programming without using Gnu radio or any other software.
Kindly guide me if I am doing something wrong. It would be great if you can list down other data ports to be controlled.
Please tell me if my approach is correct and steps to be followed to program the FPGA correctly.
Any suggestions are welcome.
I think you need to localize your problem first, and make sure each step gives you the valid result. It could be many possibilities from this point.
Cheers
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Hope that all of you will be fine.I am trying to implement the motion estimation algorithm(block search) for video compression in FPGA.I am trying to implement memory reusability concept but I have a problem in reading column I can read row of memory in one clock but I can't read column in one clock.Can anyone suggest any method for reading column in one clock.Thanks in advance
it seems like you need to use matrix buffer which mimic the memory 48x48. You need to ensure the clocking period to comply the design specification. Or if you need those data row and column at the same moment, you can copy the memory data into 2 identical memories, one with transposed format.
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Hello ;
I have Zybo board, i write my code using Vivado hls (C or C++).
My problem is here,
I need to know how i can stock a big matrix( 256*256 for example ) in Zynq using Vivado hls.   After how i can manipulate this matrix?
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Vibation analyzer in Measurement, Diagnosis and Speech Recognition use a state machine for event-driven control. Which programming language is the best for a software-state-machine in event-driven audiosignalprocessor?
Sir,
Everyone is best with the language they know the best. You mentioned a state machine, I would suggest LabVIEW using a Queue Driven State Machine (QDSM) approach. In this approach, you dedicate a Queue to each major function (GUI Input, GUI Output, File input, File Output, Data Acquisition, Preprocessing data, processing data, report generation, etc). Each of these Queues will be able to communicate with each other queue through queue commands or events. The entire project could have a script queue that would allow it to be scripted from a text file (something I often do to allow reusability of the code).
I find that I can handle projects with over a thousand subroutines / SubVIs  by myself using this method. So little outside help is needed once you get some experience with it.
Good Luck!!!
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sir, I am trying to do following -
I am giving a signal x(t) as input which has 1000 samples.(i have taken one signal and samples it using the matlab and got the points in form of integars)
Now i have extracted the local maxima and minima of that signal.
By using local maxima i have calculated the upper envelope by using linear interpolation and same i have done with local minima to calculate the lower envelope and then i have taken the average of the upper and lower envelope and have got a signal m(t)
now i have to calculate a new signal h(t) which will be
h(t) = x(t) - m(t)
I have to repeat all above three times, means now again h(t) will be the input signal,
x(t) = h(t)
How to repeat the steps? I have written the code separately for each step. Should i use FSm? If i am going to use FSMs then how can i instantiate the modules in FSMs? Please suggest. I ma in big trouble
The best way to solve your problem is using Mealy FSMachines, becouse the change of the state depends of the imput values. In this case the imput values (true/false) can be the convergence criterion and the termination criterion.
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I want to implement a circuit in Verilog but one of its inputs Is n-bit and based on that input the number of instantiated modules will be vary, so can I create an array of instances that its size will be calculated based on the width of the noted input ?? or are there any ways other than using arrays to do that at all ??
Most simulation, synthesis, and other tools now support the "generate for loop" that's already been mentioned. The alternative if you have older tools is called an "array of instances." It looks something like this:
parameter N = 8;
output [N-1:0] dout;
input [N-1:0] din;
input [1:0] cntl;
mysubmodule [N-1:0] sub_inst (.Z(dout),.D(din),.C(cntl));
For this example, assume the submodule's Z and D are single bit and C is two bits wide. Connection signals that are the same width as the single instance port width (C in this example) are connected together to all instances, while those that are different (i.e. wider) are bit sliced to each instance. So this example unrolls to the equivalent of the following:
mysubmodule sub_inst0 (.Z(dout[0]),.D(din[0]),.C(cntl[1:0]));
mysubmodule sub_inst1 (.Z(dout[1]),.D(din[1]),.C(cntl[1:0]));
mysubmodule sub_inst2 (.Z(dout[2]),.D(din[2]),.C(cntl[1:0]));
etc...
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did any one have a UCF file for FPGA xillinx model zynq 7000
iam using ise to program this fpga my code is working will but in mapping process it is stop because it needs ucf file for  zynq 7000
You can contact coreEl , Bangaluru,India
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Hello Everyone,
For my project work i have to calculate the inverse of a matrix using verilog for my project work. Any suggestion or anyone who have already done this in verilog?
Your question is not well framed. What you want to design is HARDWARE for matrix inversion using Verilog as an HDL. Verilog is not a programming language.  You may want to ask why one may want to invert a general matrix in the first place. Is it for solving a set of linear equations? Can there be an alternate method for solving a system of linear equations? You will probably benefit by looking at the work on systolic arrays.
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A real time visual attention system based on the human visual attention, it's better to use a only a FPGA, GPU or FPGA+dual core ARM?
The key to succeed in this kind of project is to properly partition the application, which blocks will be executed in the dual core ARM and which blocks will be executed in the FPGA fabric. You must know the formulas of your algorithm(s) and see if they show dependency or not with respect to time. If algorithm(s) do not show such a dependency, they can easily implemented in the FPGA using VHDL. If the algorithm show dependency, you must look for ways how you can convert a serial algorithm in a parallel version and take advantage of languages such as VHDL. Another option is to write high level language as C/C++ and use OpenCL implementation from Altera or Vivado HLS and see what hardware produce, but note both OpenCL and Vivado HLS have limitations, and not sure if the hardware those tools produce will be efficient. Finally, use the dual core ARM just as a control unit, to start/end  tasks in your algorithm.
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i need to do a project about partial reconfiguration in fpga. i use a ise 14.2 software in my pc, when i run planahead and then try to make a new project, the partial reconfiguration enable option is not in the step two that should be, how i can solve this problem?
I would be most interested to know how you get on.
I tried doing Partial Reconfiguration for the Virtex 6, but hit a problem that I couldn't make the reconfigured area bigger than a single clock region. As we wanted to reconfigure everything but the PCIe interface used to communicate with the chip, this was as show-stopper bug. As Xilinx have stopped supporting PlanAhead in favour of developing Vivado and Virtex 7, they weren't prepared to fix this bug in PlanAhead.
As we had paid for a partial reconfiguration license that we couldn't then use due to this bug in PlanAhead, we were pretty annoyed about all this.
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I am implementing raddix 4 fft on xilinx virtex 6 fpga. For that I tried some scaling schemes but I did not get satisfactory answer. so please suggest some good scaling scheme for that.
How to implement rounding in fpga program?
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I want to execute the encryption algorithm on ML 506 board.So how can I give inputs to board and how can I receive the output from the board. In some papers they mentioned it is possible using HYPER TERMINAL. Can anyone know this?
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i use xilinx vivado 2014.4. While declaring the inputs and outputs if i mention a port as inout ., a type mismatch error occurs.But if i replace inout with buffer the error is cleared.Why does it happen this way.My application requires a port to act as input once and later it should act as an output.
In VHDL it is not possible to read a output (signal out in entity). Then you have the type buffer, with is a output, but it is possible to read. But iti is two problems:
- One signal declared as buffer can not be connected to a signal out.
- buffer is a reseved word in some tool, like Xilinx. That is a special component for the clock signal! Michmach
Now, a signal declared as inout is a realy pin used as input and output. You can read this signal. But that use a three-states buffer. If you want only read a output signal, you need to defined a internal signal:
on entity:  output_to_read_o : out std_logic
on architecture:
You can the explanation in french in my presentation on page 29 to 31:
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I am implementing raddix-4 DIF generic algorithm (N = 64,256,1024,4096,16384) on xilinx virtex-6 fpga. I have got two schemes for the twiddle factor generation for that.
1) generate sin and cos by cordic and store it in memory and call it in the process to multiply with the addition of inputs. In this I can do parallel tasking to increase speed but multiplication increases vector length drastically.
2) use cordic rotation for complex multiplication. This will not increase vector length but will reduce my speed. Xilinx CORDIC ip core takes phase input in 2QN formate but my maximum multiplication (2*π*k*n/N) answer lies in 3QN formate (around -4.71). So how can I solve this problem?
If I understand correctly, you have the problem, that you give the DSP48s a 18bit and a 18bit vector and get out a 36bit answer?!
I am doing the same on our system and I would recommend looking at the input and  output. Our sine and cosine for example are always < 1. In consequence even though the tools will give you a 36bit output the top bits will always be 0, so you can just chop them off(be careful not to chop sign bits).
The bottom bits are more a question of what the accuracy of your inputs is. Generally if the inputs are only accurate to 18bits, then you do not need to keep 36bit, but can chop off at least down to 20bits without increasing the error on the output significantly (all your are essentially doing is chopping off the already erroneous bits and thus only changing the nature of the error).
Hope this helps.
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I wan to see output FFT through serial port from fpga to computer. How can I do that? Want to implement uart. How can I get output in computer?
Rabbia,
It all depends on the bandwidth you want between the FPGA and the computer. For moderate bandwidth, typically done is following:
- Implement an SPI interface on the FPGA.
- Use FTDI device (look for it on the internet), to translate SPI to PC USB.
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what are the parameters and conditions which have to be considered for one  to decide whether to use a micro-controller or an FPGA as a processor?
The main and the most significant difference between the microcontroller and the FPGA is that FPGA doesn’t have a fixed hardware structure, on the contrary it is programmable according to user applications. However processors have a fixed hardware structure. It means that all the transistors memory, peripheral structures and the connections are constant. Operations which processor can do (addition, multiplication, I/O control, etc.) are predefined.And users make the processor do these operations "in a sequential manner" by using a software, in accordance with their own purposes.
Hardware structure in the FPGA is not fixed so it is defined by the user. Although logic cells are fixed in FPGA, functions they perform and the interconnections between them are determined by the user. So operations that FPGAs can do are not predefined. You can have the processes done according to the written HDL code "in parallel" which means simultaneously. Ability of parallel processing is one of the most important features that seperate FPGA from processor and make it superior in many areas.
Processors are generally more useful for routine control of a particular circuits. For example, using FPGA for simple functions such as turn on and off any device from a computer may be overstated. This process can be easily done with many ordinary microcontroller (PIC series, etc.). However, FPGA solution is more reasonable, if you want to process on a high-resolution video data on the computer.
Because video processing requires processing large data in high speed and make these types of applications are very suitable for FPGA that is capable of parallel processing.
Since the user can determine the hardware structure of FPGAs, you can program FPGA to process larger data with few clock cycle.
Whereas this is not possible with the processor. Because data flow is limited by processor bus (16-bit, 32 bit, etc.) and the processing speed.
As a result, applications that requires more performance such as intensive data processing FPGA has come to the fore, and processor / microcontroller has come to the fore for routine control operations.
Nevertheless, processors / microcontrollers can be embedded into the FPGA since they are logic circuits in fact.
Thus it possible to define and use processor and user-specific hardware functions on only one chip by using FPGA. This solution gives engineers the oportunity to control the hardware because of its great flexibility.
You can modify and update whole design (FPGA on the processor and other logic circuits) by only changing the code on FPGA, without any change on circuit board layout.
In this way, you can add different functions, improve performance and make your design resistant of time without having to redesign the cards.
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As far as I remember there is a paper that covers how to obtain the netlist from the bitstream: "From the bitstream to the netlist"  by Jean-Baptiste Note and Éric Rannaud (http://dl.acm.org/citation.cfm?id=1344729) or https://www.researchgate.net/publication/200065272_From_the_bitstream_to_the_netlist
Another paper is "BIL: A tool-chain for bitstream reverse-engineering" by Florian Benz et al. (http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6339165). You can get the open source of the project in the following URL: https://github.com/florianbenz/bil/
Hope this helps
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I used the xpower analyzer to estimate both dynamic and quiescent power consumption of my design, but when I performed it for different codes, I got the same value for all. I did the .pcf and .saif files uploads, but I don't know how to upload the settings file, i.e. I don't know how to generate the settings file. Am I missed some part of the procedure?
Hi Sumathi Gokulanathan,
Let me first tell you the simple procedure of using the Xilinx XPower Analyzer (for understanding) and then some information on that.
Implement the top module using the Xilinx ISE
Open the XPower Analyzer listed in the Place and Route tab of the Design sub window
After the design gets loaded 100%, in the 'Report Navigator' sub window of the XPower Analyzer, click on the 'By Clock Domain' listed in the 'Details' tab.
A list of the clock signals and the clock driven synchronous signals appears in the window pane, by the side if the 'Report Navigator'.
If your design uses clock, change the value of the Frequency of the clock, in the concerned field. (The default value given is 0 MHz)
After changing the clock frequency to the desired value, click on the 'Update Power Analysis' icon in the Toolbar.
After the update gets finished, click on the summary, listed in the 'Report Navigator', to get the updated power values.
NOTE: To measure the power values at different frequencies, restart the XPower Analyzer to get correct values. If you change the frequency many times at a single run, the power values get added up as the algorithm (according to my knowledge) preserves the previous values of power to add them in calculating the power values of next frequency.
All the best,
Regards
NP.
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As you know, conventional nonlinear controllers are works based on system's dynamic, so how we can design FPGA-based nonlinear controller?
You can use the BlockRAM (i.e. for Xilinx Spartan series) as registered ROM memory by tying the write-enable input to low. You can do this by directly inferring the BlockRAM as ROM in the code and fill-in the coefficients directly or use the Xilinx's CORE Generator system where you can generate a special ".coe" file which initializes the ROM contents and assign it. For example you can check the XAPP463 "Using Block RAM in Spartan-3 Generation FPGAs" application note. Then you can use the memory address as the matrix cell index and the memory contents at this address as matrix cell value. And maybe this will be the fastest and easiest way. And you have various options for the memory organization (for example 4kx4, 1kx16, 256x72 and many others) so you can either write normalized values for that Sine and Cosine functions and use them as integers or write fixed-point arithmetic.
Some example of how to use the RAM/ROM can be found in "FPGA Prototyping by VHDL Examples" by Pong P. Chu (chapter 11.4.3 "ROM"). (His book is also avalaible for Verilog.) I used Xilinx and Verilog but other manufacturers, like Altera and Lattice, offer similar possibilities of implementing a ROM.
If your matrix changes dynamically it may be worth giving a try of the COordinate Rotation DIgital Computer (CORDIC) algorithm which is capable of evaluating many elementary trigonometric functions including Sine and Cosine. I have not personally used it but I know there are few free versions of CORDIC cores at opencores.org website.
Best regards,
Yassen
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I am using SPARTRAN XC3S50 PQG208EGQ1117 D4238638A 4C FPGA for synthesis and simulation process. Where will the speed of the circuit be shown?
One more thing
Timing report after synthesis is not very accurate.
It would be much better to take timing results after place and route. these values tend to be more realistic, as it is estimated after implementing the design routing for the target FPGA.
Good luck
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Port mapping refers to the concurrent statements and process refers to the sequential statement. If there is a data dependency between the blocks of the concurrent statements, each block itself is a concurrent statement and the entire flow becomes sequential because each block output goes to the input of the next block. In that case why can't we include these concurrent statements inside the process? I am confused and I don't know the reason for this.
Port map is only used for physical signals and while process is a virtual operations that use variables which requires zero time to execute ( concurrent statements)
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I want to dump my project code to FPGA board. Please can anyone provide me the input pin numbers to Xilinx SPARTRAN XC3S50 PQG208EGQ1117 D4238638A 4C?
After performing the synthesis, a detailed report of the synthesis will be generated, just just scroll down the report, you can see the maximum clock frequency supported by the your system.
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Type of Image Processing Algorithms suitable for FPGA/ASIC.
Window-based operations are very good candidates for hardware implementation. You can organize the incoming pixel stream as shown in this article:
This opens a way for the implementation of a lot of image image filtering and feature detection algorithms.
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I have done programs with FPGA using VHDL. Now I want to to do Dynamic Partial Reconfiguration. Where do I start?
Hi folks, just to clarify, with PlanAhead you may implement partial bitstreams, but the partial reconfiguration (PR) flow given by PlanAhead provides only the initial partial bitstreams for the partially reconfigurable module (PRM). Even though Xilinx says that you can change the functionality of PR regions (PRRs), by dynamically download partial bitstreams on the same PRR, I consider that dynamic partial reconfiguration is more than that. Dynamic PR allows you to modify the partial bitstreams without going through the long PR flow. You may search literature about this topic, and take a look at my publications. Regards,
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I want to use synopsys/cadence tools such as synopsys design compiler, synopsys prime time, cadence SoC encounter for place and route and synopsys tetramax ATPG. Are any of the mentioned tools freely downloadable?
I do not think it is possible to download them for free. But many be you can interact with the application engineer and get some help from them.
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I am doing a project related to image processing concept. I developed the code in Impulse c language. I can implement my designs in Spartan 3 Tyro plus (XC3S200) FPGA using microblaze processor. Is it possible to simulate the same in any of the simulation software (XPS/SDK, Model sim, ISIM, etc.)?
More details I will mail you by evening
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I am doing reed solomon codes in verilog and I need some help in designing euclidian block.
The Theory is in MacWilliams and Sloane; check also McEliece theory of Information and coding. This being said implementation is probably a pain.
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I want to know about Basic Built-In-Self-Repair systems for communication protocols in Verilog HDL. How I can start one?
No..I mean the next level of Built-In-Self-Test...Which is Built-in-self-repair..I have been working on Built in self test for past years....Now I want to work on Built inf self repair.
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Dear All,
Please let me know what the relation is between the number of slices used in FPGA and maximum frequency. I saw that if the number of used slices is increased, the maximum frequency along with throughput is increased. Can anyone tell me why this happens? Why is the maximum frequency increased with respect to the number of slices used?
Thanks to all. I got my Answer. It's just a coincident. It's all because of my logic and number of LUTs used.
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I am working on project of FPGA Based Face recognition.
Hi..
There is no such a tool to convert matlab code into VHDL code.. Eventhough, if it is, it will produce inefficient code.. not all the matlab generated VHDL codes are efficient. its better to try it in vhdl itself, instead of conversion.
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Are there any designs or algorithms that reduce the timing in the dynamic reconfiguration of blocks in an FPGA ?
In order to answer, I will use Xilinx terminology. Sorry if you plan to use a different technology, you will probably be able to adapt some issues/terms/techniques.
Reconfiguration speed is dependent on:
- How many frames you need to write. Of course, frame length is also important. In modern Xilinx FPGAs, frame height corresponds to one clock region, but this is family-dependent (16 CLBs in Spartan-6 20 in Viertex-5, or 50 in Zynq).
- Which port you use. The fastest is the ICAP, which let the FPGA to reconfigure itself from the internal logic.
- The ICAP can be overclocked in some families (See Claus paper in ARC 2010), so time might be reduced.
- With heavy ICAP bandwidths, the provision of dato into the ICAP becomes a problema. If data to reconfigure is very small, think about having it in BRAM. If it is larger, you might perhaps off-line download the dynamic bitstream content from a flash into a DDR or similar, and by using DMA Access, read directly from there and put it into the ICAP. If you need to directly download from a flash, a parameter in the header determines the clock speed to use. Try to accelerate it as much as your design supports.
- Having compressed bitstreams helps for complete reconfiguration (i.e. at boot time), but it is not that useful for partial BSs.
- You may also think about Reading from the ICAP, relocate the bitstream by changing the addressing, and write again. This method does not impact memory utilization bandwidth, but Reading through the ICAP does not permit that much overclocking as when writing.
In ReCoSoc 2012 we have a paper on providing partial dynamic reconfiguration into a Spartan-6 device. Also, we show that, the fastest, the less energy consunption. In DSD 2010 we report the use of a peripheral for fast reconfiguration. You may also read articles form Michael Hubner or Jim Torrsen, or the above mentioned from Christopher Claus.
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How do you make the model?
for modeling you can use MATLAB-Simulink, if you want to implement it into FPGA you need either separate the analog part from the design (off-chip components) and synthesize the rest into the FPGA chip. or you need to look for fully digital alternatives. The idea is that you can't control any of the gates parameters (e.g. voltage level) and thus you can't implement analog circuit.
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Its regarding fpga based implementation of eye tracking system.
check this great resource for all FPGA projects, they have various image\video processing projects
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Its regarding FPGA implementation of OFDM transmitter.
i am not sure and good at verilog but here is a link for VHDL code generation of RS encoders.
The article is good with complete GF(256) RS package.
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My question concerns Computer-Aided Design and VLSI and low power VLSI.
Thanks waris and afaq for the answers
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If we implement SIFT algorithm on FPGA then what kind of optimization is possible in it?
As far as I am concerned, openCV offers some GPU functions instead. The functions detect and describe interest points extracted from an image with several kind of appearance descriptors, including SIFT, SURF etc. If you use C/C++ , you can implement very fast a test code and see if it works for you.
Check out here:
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I would like to do partial reconfiguration with Xilinx system generator tool generated code. I have developed a physical layer model in Xilinx system generator. I found two of the blocks in this model to be of partially reconfigurable modules (I have different functionality for these two, no of IOs are same). I generated the code.
Can you please tell me if anyone has had success with this approach (with sysgen tool)?
Hi Srinivas,
I haven't used Xilinx SysGen for partial reconfiguration. However, I have used partial reconfiguration tools extensively for my research. You may wish to read my paper on partial reconfiguration "FPGA-Based Reconfigurable Hardware for Compute-Intensive Data Mining Application", which describes how it is being done. This paper received the best paper award.
Hope this helps.
Darshika
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I have a code for face detection using OpenCV with C++ language, and I have to implement it using FPGA Altera. Is there any software, or program that would synthesize my C++ code inFPGA?
While there are C-FPGA tools (Vivado from Xilinx, OpenCL from Altera, CoDeveloper from Impulse, and ASIC/FPGA high level synthesis tools from Mentor-Synopsys-Cadence, none of them will take OpenCV code and push-button synthesize it.
That said, good methodologies exist for doing <C++>-C-FPGA-C-<C++> work on those portions of your code that need to be accelerated.
You stated that you "have to implement it using FPGA Altera".
What do you have to implement? What part of your application?
Usually, one accelerates the slowest part of the <OpenCV> application that is a bottleneck for your application to achieve real-time or good throughput performance.
This comes from having examples that and profiling that show what the slowest part of the application is. Do you have that information?
alan
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I want to implement a delay chain using Adder in QuartusII. But after synthesis, the Adder is removed by QuartusII. I don't know how to set QuartusII.