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Questions related to FPGA
I have been trying to find a resource to identify the circuit element structures (from an optical micrograph) of delidded/decapsulated electronic devices, including the imaged Xilinx Arty A7 FPGA. My goal is to electrically stress one element or region of the circuit and see if that affects the sensitivity to localized ionizing radiation in the form of single event transients or single event upsets. I can see the electrical leads towards the octagonal structures, but I am not sure what they are (Capacitors?). I have circled a few other structures that appear as dots on this micrograph. Is there a resource I could use to help me identify these structures and how to locally electrically stress them? I have done so on simpler devices, like operational amplifiers, but this structure is more complex.
Thank you.
I am looking for a few good journal papers for my next work, which is used for efficient network traffic classification (NTC) using FPGA and ML algorithms for real-time NTC.
It is a kind of framework that works on the real-time organization traffic that works at the ingress router.
I am using FPGA basys 3 board in my college, having 100MHZ clock frequency, i divided the default clock (clk) by 216 and getting clk_out in the output as the minimized clock after division. if the following command is used for the default clock in the constraint file
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
then what will be the command in constraint file for the clk_out? the clock division is done in the following way
module clk_divi(clk,rst,clk_out);
input clk;
input rst;
output reg clk_out;
reg [7:0] delay;
initial begin
delay = 0;
clk_out = 0;
end
always @(posedge clk or posedge rst)
// if(rst)
// begin
if (delay < 108)
begin
delay <= delay+1;
end
else begin
delay <= 0;
clk_out <= !clk_out;
// $display("clkout=%d ",$unsigned(clk_out));
end
endmodule
I created a project in vivado (target language: Verilog, FPGA Device: NEXYS 4 DDR). After successful simulation, synthesis and implementation of all the modules, I am getting Device Utilization Summary as zero(i.e. utilized slices, FFs, LUTs, IOBs, GCLKs = 0).
What can be the possible reason for this?
I need help in monitoring the ADC(Model LTC2268-14) data which is interfaced with Artix Ultrascale+ XEM8320 board.
Hello everyone. Can anyone tell me if it is possible to build a lock-in amplifier by recording all the signal and reference in FPGA and then doing integral over the recorded data? All the process for demodulation seems to be possible by mathmatical calculation if I've already recorded all data, am I right? Many thanks for your help.
How can I make a connection between FPGA and Simulink?
I want to use FPGA-In-the-Loop (FIL) and my purpose is performing altera board DE1-soc and Simulink.
Unfortunately I haven't found a way to do that yet if it's even possible.
Please leave any suggestions.
Best regards
Hello everyone, can we use python as a programming language for FPGA? thank you
FPGA Implementation of Soft Decision Forward Error Correction Codes is required for High Speed Optical Communication Systems. Which tools and what hardware are required for the FPGS implementation.
Can de design the FEC encoder/ decoder for 10GBPS and beyond?
Please let us know the suggestions
Hi all,
I am trying to deploy neural network to a FPGA board mentioned in the question. So far I have succeed with simple projects provided by Mathworks such as:
and right now I would like to change images sent from PC to images from camera (ideally live video) connected directly to the FPGA board making it standalone machine, from image acquisition and preprocessing to image postprocessing.
Best example I found is:
But it requires a sister card which I don’t have, so before purchase I would like to explore other options. If its possible I would like to stick with Matlab/Simulink and HDL coder.
Thank you in advance.
Hello, can anyone guide me on "How to Interface DAC with FPGA using Xilinx System Generator?"
Hello, I am working on a project in which I need to regulate the speed of the DC motor using the PID controller in Verilog for the FPGA Spartan 3e, is there any code I can start with?
As a student who wants to design a chip for processing CNN algorithms, I ask my question. If we want to design a NN accelerator architecture with RISC V for a custom ASIC or FPGA, what problems or algorithms do we aim to accelerate? It is clear to accelerate the MAC (Multiply - Accumulate) procedures with parallelism and other methods, but aiming for MLPs or CNNs makes a considerable difference in the architecture.
As I read and searched, CNN are mostly for image processing. So anything about an image is usually related to CNN. Is it an acceptable idea if I design architecture to accelerate MLP networks? For MLP acceleration which hw's should I work on additionally? Or is it better to focus on CNN's and understand it and work on it more?
As per datasheet of AD4111 I cannot make the interface mapping for AD4111 to FPGA If any helps come it will be good for my recent project.
Register mapping will be more helpful.
#embedded_systems #VHDL #electronics #fpga #adc #spi
Hello everyone!
I'm trying to implement 4 step commutation for AC-AC choppers using FPGA board from Xilinx (Spartan 6). The 4 step commutation code works perfectly fine on the FPGA and the output from the FPGA board has been verified on oscilloscope as well. The input to FPGA comes from Dspace microlab box( rti1202).
However, when I try to give the pulses from the FPGA board to the gate drivers (NCD57001) and try to verify the output of the gate drivers for 4 step commutation, one of the states of four step commutation gets missed and instead 0000 state appears.
I expect the output of FPGA to be exactly replicated by the gate drivers but there's a difference in the results. (files attached)
The propagation delay of gate drivers is 90nsec. The DESAT pin of the gate driver has been grounded at the output. Four gate drivers receive pulses from the 4 output pins of FPGA. The input grounds of all the gate drivers are connected to the output ground of FPGA.
Can anyone please suggest some solutions?
TIA
I have designed a CNN model in python using TensorFlow. Now I need to implement the same model using Verilog on FPGA.
We wish to write verilog code, which can be placed on an FPGA to generate FMCW radar waveform. Could, anyone suggest any code/ program pertaining to this. Thank you.
We are planning to implement matrix based mathematical algorithms on FPGA. Could anyone suggest good book for these topics?
According to the number of Input and outputs ports of the FPGA chip we have, can we add (implement) any number of ethernet (100base) RJ45 and Fibre LC connector to the FPGA? What is the way to do that?
Also how can I also implement the following protocol into the FPGA; DNP3 , GOOSE and MODBUS?
which tools or libraries are using for these protocols on FPGA?
and what is best affordable cheap FPGA development board to buy with Ethernet Rj45 and Fibre LC connector SFP
What is the best low-cost FPGA for power electronics modulation and control?
I am a student new to this implementation, I need to design a frame for satellite communication for image transmission.
I am using QPSK modulation and demodulation, LDPC encoder and decoder.
help me out, I am programming in MATLAB later will test on FPGA
Thank you
I have 100 samples of data (sampled at 170 Hz) each having 16-bit wide, first of all I want to store the data in FPGA basys 3 board and secondly how it can be displayed with the help of FPGA VGA or any other port to a computer monitor?
( I am using Vivado 2017.4 for verilog coding and Digilent FPGA Basis 3 for hardware verification)
# information obtained so far#
For Verilog code, we can use $readmemh(for hexadecimal data) or $readmemb(for binary data) command to load a converted binary/hexadecimal text file directly into FPGA.
Is it possible to implement the maximum power point tracking (MPPT) system in the solar cell using artificial intelligence algorithms in FPGA through Vitis AI?
How to make a fair utilized area comparison between three designs; one of them uses 4-input LUT, the second one uses 6-input LUT, and the last one which is an Altera based uses ALUTs ( Adaptive LUT). Can I calculate the equivalent gate size/number for each case?
hello I am searching for an FPGA implementation that can be improved with redesign CORDIC algorithm for my Thesis project. has some one any idea?
I am looking for a new application for the CORDIC algorithm or an improvement of the algorithm for new applications
i am doing research with optical devices and working with semiconductor optical amplifier based logic gates. i have achieved 405 ps response time for my logic design. now i would like compare both electronic and photonic logic gates. what is the maximum response time (RT) achieved by FPGA based logic gates and devices? kindly refer papers to understand the difference
Comparison of different Micro Controllers and its features. Every micro controller has specific gui interface. In which, dSPACE specifically has online control feature. Except that what are the benefits of other micro controllers like Arduino, Raspberry, FPGA, dSPACE, PIC, C2000 with respect to digital io's and ADC and DAC and their resolutions. Please share features and views on any micro controller you are using.
I have designed a training model for the breast cancer dataset using floating-point multipliers and adders (adder tree)by storing patient data and weight value for each feature in BRAM for further processing. Some 20% of data is kept stored in the BRAM for testing. My doubt is how to pass testing data to the trained model. I have calculated the weight value for each feature using python script and which is the same for all patients. Please help me in this regard. If I am following the wrong method please suggest me.
- My first step is to add FPGA into the hydroacoustic communication system to improve the performance and anti-interference of the system, the second step is to import the algorithm into FPGA, and the third step is to optimize the algorithm
- So first I have to go to add FPGA to hydroacoustic communication system, but I don't have any clue, are there any papers I can refer to?
Hi everyone,
I am trying to optimize my data in FPGA and reduce the data movement between off-chip memory and FPGA. one of the possible techniques is the data reuse methodology. I need a reference, lecture or tutorial to learn about the spatial and temporal reuse techniques. I appreciate any help or guidance from you in advance.
I am using Xilinx Zedboard and I want to generate optical codes using FPGA. Any idea how to do this?
What are the main challenges of implementing different deep learning models architectures on FPGA platforms? I am particularly interested in CNNs.
with HDL coding, we can do functional verification. what else can we do with the help of other tools may be like chipscope pro, FPGA board etc
Hello guys I'm a student and actually I'm working on spiking neural network , is there anyone could help me about finding a verilog code implementation on FPGA of a spiking neural network.
Thank you
Actually, I want to know the process of the implementation of cryptanalysis on AES and Blowfish using the FPGA board, can you suggest to me what resources are available for this implementation
Hi,
Can anyone guide me on which cheap FPGA kit can I used for linear as well as non-linear type controller implementation in Power Electronics Applications?
Thanks
I don’t think that the textbook scaling equations can be used for fair comparisons for recent nodes.
How to implement max Log MAP algorithm turbo decoder on FPGA? Simulation is done on MATLAB. What are the next steps to be followed? Do I need to use HDL Coder feature in MATLAB? Is it needed to implement it on Simulink or System Generator first?
I need to implement matrix inversion in hardware. The size of the matrix can be anywhere from 50 *50 to 8*8. Are ready-made standard codes available or inbuilt modules available with FPGA boards, please let me know? How feasible it is. If not FPGA can anyone suggest, another type of hardware to do so.
Hi,
I am trying to implement a basic CNN on FPGA using fixed point arithmetic. It is originally trained using 32 bit floating point computation. I want to implement this with 16 bit fixed point arithmetic on FPGA. Do we need to get the max , min and std deviation values of each layer for this. It will be great help if someone can explain this. Also how we can find these values ie. max, min and std. deviation for each layer of CNN.
What is the difference between the softcore ARM processor with FPGA (example xilinx) and the hardcore ARM processor! : limitations and performances
I am trying to implement a deep CNN onto FPGA. I trained my model using Keras and is trying to do the inference on FPGA. I would like to know how to get the kernel values to feed to FPGA or do we provide activation maps instead?
I am trying to implement a processor tile on FPGA using vivado but it is taking too long to synthesize design due to large amount of Instruction and Data Memory.
Currently, I have put complete machine code of a simple GCD code in the instruction memory and generated the bit stream file.
But I cannot afford to wait for hours everytime I try to synthesize processor for a new code.
There must be a way to interact with internal memory of FPGA so I can put machine code in the memory and connect to instruction memory of processor.
In this way I will generate bit stream file of processor tile only once. Burn it to FPGA and put different machine code every time to test a different code.
I have gone through documentation of board and explored many other documents but could not find something useful at my level.
Board I'm using: Nexys A7-100T.
Software: Vivado 2019.2
Field programmable gate arrays (FPGAs) have been constantly used for embedded systems in various applications, such as inverters, medical appliances, etc. The reverse engineering in the FPGA is a way of re-configurating the netlist inside the FPGA in various ways. There are some known tools such as Debit, BIL, and Bit2ncd that could be especially used for Xilinx products. However, these are still under developmental phase. Are there more such products available for stable use? What if non-Xilinx products such as from Intel Altera FPGA's are adopted for use?
I have written a verilog program in which some of lines of code runs based on positive edge of clock pulse (Ex: always @ (posedge clk) ). Therefore, the code requires a clock (clk) as one of the inputs. Assigning clock pulse as an input in the target device CMOD S6 (spartan 6) is possible and hence programming/flashing CMOD S6 become success. Also verified that the obtained output results are satisfactory.
Now, instead of flashing an external real world FPGA, I wish to flash the above code into the internal FPGA of Opal-RT target device OP4510 using system generator 14.7. However, I got stuck in accessing FPGA clock which is required, as I said before, as an input for the code. I have tried to use pulse generator as a clock input but can not set its frequecy as 8MHz (desired clock frequecy) due to simulation step time limitation.
I would be thankful for the relevant responses.
What FPGA accelerator algorithm for CNN's have significant reduction in resource usage while maintaining high accuracy and performance comparable to normal algorithm.
I'm training the network in a PC and planning to export the inference into a FPGA.
What will be the RTL design? How can it be implemented inoder to secure voice communication using AES128 bit encryption on FPGA.
I'm currently working with ECG and PPG signals implementing them in FPGA. I have to do A-D conversion for further processing.
I have decided to go with non-uniform sampling method.
How can I set my sampling frequency, quantisation step size, sampling rate for non-uniform sampling?.
Can anyone give me solution?
I'm a researcher doing my research on the Acoustic Emission (AE) Technique. A few days ago a problem arises in AE WIN software (Physical Acoustic Corporation, Micro II Express, Digital AE System). It is showing "Can't read FPGA correctly". Does anyone have any idea why the software is showing this type of error? and how to counter it? A Screen Shot Is Attached.
The Network elements includes Hubs, Switches, Routers, and Gateways.
i Need any link or reference paper for gateway architecture design
in FPGA or VLSI design, How can, identified short path problem and corrections.
Hello Friends,
Am developing flight control system completely in VHDL. for PID implementation, i have developed algorithm in arduino and tested for single axis, it works fine. while tuning Kd,Kp,Ki values, it responds accordingly. the same algorithm i developed in VHDL. i used modelsim for simulation. but after inserting into FPGA keeping all other setup same, while testing it is not functioning as expected. while increasing Kd value, instead of reduce oscillation, it increases oscillation. i have checked orientation of motors and other hardware. everything fine. am not sure where am missing. requesting suggestions.
Thanks
edit: Thank you for your valuable replies. Based on all of your inputs, currently am checking step by step, comparing arduino output with FPGA output. I have one doubt to clear. arduino gives PWM signal with 5V output which is connected to Simonk ESC to drive BLDC motor.But FPGA gives gives 3.3V PWM output. will it be the problem? need i put 3.3V to 5V logic level shifter, to give control input to ESC?
I am trying to interface with a IR sensor(640x480) and display the raw data(for now) via HDMI out.
PSYNC for the sensor is 19.2MHZ @ 60Hz (HSYNC is 25 psyncs and VSYNC is 689 psyncs)
I'm struggling with displaying it over HDMI 640x480@60hz because the output pixel clock is 25MHz.
The main issue is that psync for the sensor is 19.2MHZ and display clock is 25MHZ.
The input frame time from the sensor is (665*480 + 664)/19.2M = 16.659 ms
And the display output frame time is 800*525/25M = 16.8 ms
So the input frame is always faster in this case and hence causing the issue where the buffer between the 2 doesn't remain constant.
I have tried buffering various lines in BRAM of input data and then starting the output stream when the buffer is full but the data on the display doesn't seem to be stable (meaning there is a non-static misalignment between one horizontal line to the other).
I have been trying to get this to work for 3 days now. Any help/idea would be appreciated.
Please let me know if I'm missing some information here. This is the first time I am diving into images/video and FPGA.
This must be a common issue and there must be solution for this but it's just that this is my first project in images and I don't know where to look.
Help me to identify the Fast and Area efficient convolution methods that can be implemented using FPGA.
Hello,
I am currently working on the estimation of the electromigration of an FPGA.
We just performed the construction analysis so we know all the values of wire width and height for each metal line. From the data sheet, we also know the current consumption of the device.
We would like to estimate the electromigration lifetime for each metal line. In order to do so, I need to know the current density. Any idea how can I (roughly) estimate it, with the data I have available?
Thanks a lot
High-end APIs of python, Tensorflow and Keras dramatically reduce the time and effort put into experimenting and deploying DL/ML models for various tasks. but I can't seem to find a High- level framework that quickly implements these algorithms on FPGAs.
What is the reason behind this? Is there any framework which helps me quickly experiment on FPGA?
I have written code for DEMUX and it is synthesizing it with LUTs only and it is not taking DEMUX into consideration while synthesis. why?
I am using xillinx zybo board and synthesis with vivado software.
In 7-series FPGAs (and Zynq on Zybo belongs to this cathegory) there are no Demultiplexers as building blocks. Basic building blocks are CLBs containing look-up-tables (LUT), Flip-Flops and some Multiplexers. These multiplexers can help to build wider multiplexers from LUTs.
Why isn't it so important to have DEMUXes physically on an FPGA or in digital integrated circuits at all?
Find the answer by inspecting a demultiplexers internal circuit and compare it to a decoder. What do these two circuits have in common? They both have a group of selection signals decoded by AND-gates. The only difference is, that a demux feeds an input line to each AND-gate. Each AND-gate points to a target logic.
During circuit synthesis the demux-decoding can take place in the target logic directly and also the input will go directly to each target. So, decision to take an Input or not is derived from select lines from the target logic itself, in fact in each target's LUT.
I have implemented the direct torque control using matrix converter in the matlab simulink. Now I want to proceed for the hardware implementation..
I read about the xilinx system generator software to develop the code for FPGA.. Is it easy to implement or any other mode of code generation for FPGA is available? Kindly someone suggest me a path to proceed with by sharing your ideas.
Hi,
I am working with a platform to deal with signals based on FPGA boards.
I have currently built the reference design on GitHub ( https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2), and the Linux software core with it.
I now need to reduce the voltage of the signal output on DAC, but I have no idea where I can start to modify the project. I am wondering if someone has solved similar problems before and can give me a hint what I can do.
Thank you!
I am trying to implement a model predictive controller to control my soft robot. Right now, the robot is being controlled in an open loop. I have written python code for the MPC but the codes are not running very fast. I don't think the computation time is sufficient for my purpose. Is it possible to interface an FPGA board with the Pi? or Is it possible to do the main computations on a PC and communicate with the Pi.
FPGA boards can be used to implement signal processing algorithms. However, SVD needs many matrix multiplications and inversions. Can it be implemented using FPGA libraries or VHDL code or it is difficult?
I am working on processing real time sensor data on FPGA using Neural Networks. But I am not able to acquire the data on FPGA. One solution was suggested that I use High Level Synthesis(HLS) for this, using the soft-IP processor core. I want to know if there is any other way to do this, preferably using I/O onboard FPGA. Please suggest. Thanks in advance.
I am looking for an open source alternative for HDL Simulators such as Modelsim Student Edition (limited version). Any suggestions??
I am trying to create some pattern with a DMD (digital micromirror device) and I want to configure a FPGA to drive the DMD but I'm running into some problems.
I would like to design and develop a control system based on FPGA ALTERA DE0, this system control a bridge inverter with PWM technique, I need to sens the load current and control it at thier reference.
Please does anyone have an experience in implementing Decision Trees on FPGAs? I have read a couple of papers and emailed a couple of people but i haven't received very good feedback on how to go about the design and implementation. I have searched online for tutorials in this regard but can't seem to find much out there.
If you have experience in this, please can someone point me to the right direction either tutorials or where I can get substantial information on this. The area for implementation is not too important as I can always tailor it to my needs.
I am trying to design and implement it using the Xilinx vivid tools and implement it on the ZEDBOARD.
Any help is greatly appreciated.
Many thanks.
I am working on a project to send data to a database using FPGA over Ethernet connection. I believe the FPGA needs to communicate with SQL Server in order to transfer the data to a database. I am very new this and unfamiliar to the protocol. Any advise would be much appreciated.
VLSI is the process of creating an integrated circuit (IC) by combing thousands of transistors into a single chip. There are two kinds of widely used IC technologies. One is FPGA and other is ASIC. Budget, power consumption, and speed are the common parameters considered for the selection of these technologies. Suppose, a medium volume production of an image transformation circuit is required. As a Circuit Design team lead, which one of the two IC technologies you will select considering the above given parameters for the design of production of required transformation circuit?
i want grab frames from VGA camera for processing
As per the concept of "reversible" and "irreversible" logic, the amount of heat dissipation for an FPGA module varies. However, in any practical scenario, it can't be purely reversible logic processing (Plz correct me, if I am making any blunder in this assumption), then how much heat dissipation should a thermal analyst consider?
I will be responsible for the FPGA implementation, and i need a researcher with a ML application that needs to be implemented. Highly recommended that we could find a topic that related to robotics or IoT
Hello everyone,
which ways could I use for obtaining data about colour of every pixel in image which has .jpg or .png formats? In the end I want to get .txt file with numerical values of colours in the RGB palette to download it to FPGA by UART. If you know better methods to do this, I will be glad to learn them.
Thank you in advance.
I have developed a BLDC Motor Model, that model I have to upload to a FPGA board which would simulate the real time behavior of the motor . My problem is I cannot create a simulink block which can convert PWM signals to gate signals.I have generated gate signals using electrical rotor angle but i dont need that right now
Hi there,
I tried to implement the "PRINCE" algorithm in FPGA using the Xilinx simulation tool and I have a problem to do that and I missed enough knowledge to do that, so please any advice for help and how and from where should I start?
Thanks for the advice...
Best regards.