Science topic

Electronic Engineering - Science topic

Electronic engineering is an engineering discipline where non-linear and active electrical components such as electron tubes, and semiconductor devices, especially transistors, diodes and integrated circuits, are utilized to design electronic circuits, devices and systems, typically also including passive electrical components and based on printed circuit boards.
Questions related to Electronic Engineering
  • asked a question related to Electronic Engineering
Question
4 answers
Why commercial EDLC supercapacitors have polarity? Are they asymmetric?
Relevant answer
Answer
Commercial Electric Double-Layer Capacitors (EDLC) supercapacitors have polarity because they consist of two electrodes with opposite charges: a positive electrode and a negative electrode. When the supercapacitor is charged, ions in the electrolyte accumulate at the interface between the electrodes, creating an electric double layer. This results in a potential difference between the electrodes, giving the supercapacitor its polarity.
EDLC supercapacitors are typically symmetric, meaning both electrodes are made of the same material (usually activated carbon). However, there are also asymmetric supercapacitors, which use different materials for the positive and negative electrodes to enhance performance. Asymmetric supercapacitors can achieve a wider operational voltage window and higher energy density compared to symmetric ones
  • asked a question related to Electronic Engineering
Question
2 answers
2024 4th International Conference on Advanced Manufacturing Technology and Electronic Information (AMTEI 2024) will be held in Chongqing, China from September 20 to 22, 2024.
Conference Website: https://ais.cn/u/JnEVZb
---Call for papers---
The topics of interest include, but are not limited to:
Track 1: Optoelectronic Integration and Advanced Manufacturing Technologies
· Precision Manufacturing of Micro and Nano Optoelectronic Devices
· 3D printing and additive manufacturing of optoelectronic materials
· Application of optoelectronic integration in intelligent manufacturing systems
· Design and fabrication of high-performance optoelectronic sensors
· Photoelectric driven robot and automation equipment technology
Track 2: Electronic Information Technology
· Convergent development of information processing technology
· Applications and Challenges of Optical Communication Technology in Data Transmission
· The Role of Photovoltaic Conversion Technology in Energy Efficiency Improvement
· Applications of Photodetectors in Security and Surveillance Systems
· Recent Developments in Optical Information Storage Technology
--- Publication---
All accepted full papers will be published in the conference proceedings by SPIE - The International Society for Optical Engineering (ISSN: 0277-786X)and will be submitted to EI Compendex, Scopus for indexing.
---Important Dates---
Full Paper Submission Date: July 12,2024
Registration Deadline: September 9, 2024
Final Paper Submission Date: September 13, 2024
Conference Dates: September 20-22, 2024
--- Paper Submission---
Please send the full paper(word+pdf) to Submission System:
Relevant answer
Answer
interested
  • asked a question related to Electronic Engineering
Question
4 answers
International Conference on Engineering, Science, Technology, and Innovation (IESTI 2024)
Date: 19-09-2024
Location: Online
Submission Deadline: 15-07-2024**** Extended to 1-8-2024
The Organizing Committee of the International Conference on Engineering, Science, Technology, and Innovation (IESTI 2024) is pleased to invite researchers, practitioners, and professionals to submit papers for presentation and publication at the IESTI conference. This prestigious event aims to bring together leading scholars, researchers, and industry experts to exchange and share their experiences and research results on all aspects of Engineering, Science, Technology, and Innovation.
Topics of Interest
Topics of interest for submission include, but are not limited to:
  • Engineering:
    • Mechanical Engineering
    • Electrical and Electronics Engineering
    • Civil Engineering
    • Chemical Engineering
    • Aerospace Engineering
    • Materials Science and Engineering
    • Computer Science and Engineering
  • Science:
    • Physical Sciences
    • Life Sciences
    • Environmental Sciences
    • Earth Sciences
    • Chemical Sciences
    • Artificial Intelligence
  • Technology:
    • Information Technology
    • Communications Technology
    • Nanotechnology
    • Biotechnology
  • Innovation:
    • Technological Innovation
    • Innovation Management
    • Entrepreneurship
    • Sustainable Development
    • Policy and Innovation
Submission Guidelines
Authors are invited to submit original, unpublished research papers that are not currently under review elsewhere. All submissions will be peer-reviewed and evaluated based on originality, technical and research content, correctness, relevance to the conference, contributions, and readability.
Paper Submission Process:
1. Format: All papers must be formatted according to the conference template available on the conference website.
2. Length: Full papers should be between 6-10 pages, including all figures, tables, and references.
3. Submission Link: Submit your papers through the online submission system available on the conference website.
4. Review Process: Each paper will undergo a blind peer review process.
5. Notification: Authors will be notified of the review results by 15-08-2024.
6. Camera-Ready Submission: Final versions of accepted papers must be submitted by 31-08-2024.
Important Dates
  • Paper Submission Deadline: 15-07-2024 **** Extended to 1-8-2024
  • Notification of Acceptance: 15-08-2024
  • Camera-Ready Paper Submission: 31-08-2024
  • Early Bird Registration Deadline: 20-08-2024
  • Conference Dates: 19-09-2024
Conference Proceedings
All accepted and presented papers will be published in the journals listed on the following website:
Special Sessions and Workshops
  • IESTI 2024 will also feature special sessions and workshops focusing on current trends and emerging topics in Engineering, Science, Technology, and Innovation. Proposals for special sessions and workshops can be submitted to editor@academicedgepub.co.uk, by 1-8-2024.
Contact Information
For any inquiries regarding paper submissions or the conference, please contact:
We look forward to your participation in IESTI 2024 and to a successful conference!
We would like to extend our invitation to invite you to join the editorial board of the:
- Journal of Probiotics and Bioactive Molecules Research (JPBMR)
Please send an email including your full name, affiliation, CV, and mention the selected journal to the following email address: editor@academicedgepub.co.uk
Sincerely,
IESTI 2024 Organizing Committee
Relevant answer
Answer
Looking forward to seeing this all progress
  • asked a question related to Electronic Engineering
Question
7 answers
I am currently studying Renewable Energy Engineering and am looking for possible topics for my master's thesis related to solar energy. My first degree was in Electrical and Electronics Engineering. I am seeking a thesis topic in the area of solar energy, with a focus on technical aspects and battery storage. Thanks in advance.
Relevant answer
Answer
What I am offering you does not match what is in the description...:
'I am seeking a thesis topic in the area of solar energy, with a focus on technical aspects and battery storage.'
If you want another topic in the area of solar energy, you can read my article about graviton:
and
Here is a text from its finish English translated part:
'(...) There is no concept that encompasses all that I have imagined about graviton, which describes an elementary particle that has no momentum, but because of its presence, the effect of any particle with a different moment of inertia is amplified when it is in direct contact3 with it and has the opposite effect to the photon. While a photon has a repulsive effect and has momentum, some tangible material content that carries information about the world from which it originates and through which it passes, this particle manifests itself as an attraction effect and contributes to the collection of information carried by the photon. For example, it has a biological role: in the formation of the optic nerve sensation it has a mediating function in the transmission of information through neural pathways. The understanding of this particle can be used to develop technologies that can increase the efficiency of solar power generation. If such technology has already been developed, itis possible to know which theory is an excellent explanation for the improvement in efficiency.'
Regards,
Laszlo
  • asked a question related to Electronic Engineering
Question
2 answers
I am doing thermal simulation of power semiconductor devices attached to heatsink. I have models of transient thermal impedances in Foster network model. To do combined simulation of power device with the heatsink I need to transform Foster model to Cauer model. I am looking for the methodlogy or algorithm to do this. Can anybody help?
  • asked a question related to Electronic Engineering
Question
4 answers
2024 6th International Conference on Electronic Engineering and Informatics (EEI 2024) will be held in Chongqing, China from June 28 to June 30, 2024.
Conference Website: https://ais.cn/u/2qEVvu
EEI 2024 is to bring together innovative academics and industrial experts in the field of Electronic Engineering and Informatics to a common forum. The primary goal of the conference is to promote research and developmental activities in Electronic Engineering and Informatics, and another goal is to promote scientific information interchange between researchers, developers, engineers, students, and practitioners working all around the world. The conference will be held every year to make it an ideal platform for people to share views and experiences in  Electronic Engineering and Informatics and related areas.
We warmly invite you to participate in EEI 2024 and look forward to seeing you in Chongqing!
---Call For Papers---
The topics of interest for submission include, but are not limited to:
◕ Electronic Technology
- 3D process and integration technology
- Substrate embedding and advanced flip chip packaging
- MEMS and sensor technology
- Design and Analysis of Transmission System
- New materials, equipment and 3D interconnection
- Wearable, flexible and stretchable electronics
- Optical interconnection and 3D photonics
- Digital system and logic design
- Computer architecture and VLSI
- Network-driven multi-core chip
- Advanced robotic system
- Analog and digital electronics
- Signals and Systems
◕Information and Communication
- Electronic equipment
- Satellite and Space Communications
- Network and Information Security
- Signal processing for wireless communication
- Cognitive Radio and Software Radio
- Optical networks and systems
- Electromagnetic field theory
- Antenna, propagation and transmission technology
- Optical communication
- Radar signal and data processing
- Other related topics
All accepted full papers will be published in the conference proceedings and will be submitted to EI Compendex / Scopus for indexing.
Important Dates:
Full Paper Submission Date: April 10, 2024
Registration Deadline: June 17, 2024
Final Paper Submission Date: May 25, 2024
Conference Dates: June 28-30, 2024
For More Details please visit:
Invitation code: AISCONF
*Using the invitation code on submission system/registration can get priority review and feedback
Relevant answer
Answer
Dear Bouziane Ghoual ,Thank you for your attention to EEI 2024. We apologize that considering the on-site experience, this conference only accepts offline presentation in China.
If you are interested in this conference, you could consider submitting your papers and attending the conference offline. Or you could also consider joining as a listener without submmison online.(Listener could participate online)
  • asked a question related to Electronic Engineering
Question
5 answers
I'm trying to design a tunable microstrip combline filter with its initial f0 at 2.45GHz, with my resonator's electrical length at 45 degrees to provide maximum tuning range. I'm having problems with my CST simulation, where I'm trying to find the unloaded Q-factor of a resonator. I don't trust the results I'm getting (a Q0 of over 1000 for a 18um copper trace on a Rogers substrate, which I thought would be below 300) and am wondering if I'm using CST correctly.
The only thing I think can be wrong with the dimensions is that I might have chosen a PCB with too thin or thick a dielectric thickness. What are some common thicknesses used for applications at 2.45GHz?
The below list is the steps that I've followed. Hopefully something erroneous pops up to someone more experienced than I.
I've set up the simulation for Q0 extraction as follows:
  1. I entered the required parameters: resonator's height, width, length; substrate's height, width, length (based on the resonator's dimensions), and eps_r; the vias' outer diameter and offset from the bottom.
  2. I created the substrate, groundplane, and resonator, defined their geometries, materials, and positions, and placed them accordingly. I then created an airbox and set its position on top of the substrate with appropriate dimensions, and set its material to vacuum.
  3. I then boolean inserted the vias into the substrate, groundplane, and resonator. After this, the resonator and vias were boolean inserted into the airbox. I wonder if the boolean operations I performed were incorrect, as I'm not sure what exact operations to follow in order to ensure proper electrical connections.
  4. I selected the eigenmode solver, used the tetrahedral meshing technique, and defined the frequency ranges.
  5. The simulation was then run: two modes were found, both not at my desired f0 but almost double and 4x respectively, both showing an unloaded q factor of way higher than 300 (which I thought was a practical max for copper on most Rogers substrates).
My goal is to get Q0 at my desired resonant frequency, but the mode frequencies CST gave me is not at 2.4GHz. I don't think it's a fault with the dimensions, but I could very well be wrong. I suspect I might have made a mistake in how I set up my simulation.
Please advise me on any possible errors I could be making, or perhaps better ways of going about the simulation.
I can't seem to find anything on YouTube detailing the process I'm embarking on, nor do the papers I've found detail exactly how they arrived at their filter's dimensions from simulation, they simply provide their resulting parameters.
Thank you for your time.
Relevant answer
How did you implement the resonating capacitances? Depending on earthplane spacing and bandwidth, waveguide modes below cut off can also do funny things.
For coupling factors, etc., Involving two resonators, the resonant frequencies without coupling must be exactly the same if you want to use the standard equation for coupling factor [k=(fo^2-fe^2)/(fo^2+fe^2)].
R.Levy published several excellent must-read articles on comb line filters.
  • asked a question related to Electronic Engineering
Question
11 answers
Please suggest some fast publishing Elsevier/IEEE/Springer/T&F journals in Electrical and Electronic Engineering/ Computer Science
Relevant answer
Answer
If you look for fees in Elsevier, IEEE or Springer, you can find an Excel with the fees and journals. Their names can help you and they have usually basic specs.
  • asked a question related to Electronic Engineering
Question
8 answers
As a research scholar, I feel that a lot of time is wasted in preparing a manuscript according to a journal format. The worst part is that if the paper gets desk rejected, then we have to prepare the manuscript in some other journal style. A lot of time is wasted in this cycle.
When the paper can be type set by the journal after getting accepted, then why dont journal allow a general free format submission.
#I_support_free_format_submission
Relevant answer
Answer
Hello Amit Das ,
Bravo! I agree with you completely, which is one, among many reasons, why I have not submitted any articles to printed-media journals. I have found ResearchGate to be a great way to get my ideas in front of the technical public without having to worry about page limits, word count limits, endnote requirements (I prefer footnotes, myself), formatting, etc. I mean, RG allows anyone in the world, who has an Internet connection, to see your documents and download them, if they so desire. You can even find collaborators on RG, if people like what you are writing.
At the same time, I understand the need, if you are an academic, of satisfying your institution's requirements above getting your articles published in peer-reviewed journals. Publish or perish is still the law of the land in many, if not most, institutions, and it is a requirement for continued employment and career advancement.
Regards,
Tom Cuff
  • asked a question related to Electronic Engineering
Question
4 answers
How to calculate the power dissipation for different switching activity in sequential elements?
Relevant answer
Answer
Sandeep Kumar To calculate power dissipation in latches and flip-flops, first determine the switching activity of the circuit. This may be accomplished by counting the number of transitions (the number of times the signal changes state) during a certain time period.
Once the switching activity is known, the power dissipation may be estimated using the following formula:
Power dissipation = switching activity x capacitance x voltage2 x frequency
Where capacitance is the entire capacitance of the circuit, voltage is the supply voltage, and frequency is the switching frequency.
Furthermore, several CAD programs like as HSPICE, Pspice, and others may be used to simulate and calculate power dissipation for various switching activities in sequential elements.
It's also worth noting that power dissipation may be influenced by other factors such as leakage current, temperature, and process changes, therefore keep these in mind while studying power dissipation in a circuit.
  • asked a question related to Electronic Engineering
Question
10 answers
Hallo every one,
I did nanoidentation experiment :
1 photoresist with 3 different layer thicknesses.
My results show that the photoresist is harder when it has thicker layer..
I can't find the reason in the literature.
Can any one please explaine me why is it like that??
is there any literature for this?
best regards
chiko
Relevant answer
Answer
The nano layer thickness is very very small layer, otherwise it's cannot use by Resistivity method and it has VES limitation.
Best regards.
P. Hakaew
  • asked a question related to Electronic Engineering
Question
9 answers
Thermal management of electronics/PCB boards purely depends on the power it dissipates (component power dissipations). But the power dissipation values provided by the component suppliers are the maximum power dissipation and in realty on field the power dissipation is far from this max values. So, i am looking into other possible ways to determine this values, through physic or analytically maybe.
Any bit of information would be highly helpful !
Thanking in advance !!!
Regards,
Rajesh.
Relevant answer
Answer
Dear
You can benefit from this valuable Link about your topic:
"PCB Simulation: How to Simulate a PCB Design"
###########
Also this one:
"PCB thermal calculator & simulation"
##############
"7 Considerations for PCB Power Supply Design"
###############
"Five Approaches to Cooling Military Electronics"
@Five Approaches to Cooling Military Electronics
###################
"Basics: Power dissipation and electronic components"
################
Online calculator for PCB circuits
I hope it will be helpful..
Best wishes..
  • asked a question related to Electronic Engineering
Question
3 answers
the question in the paper is related to vehicle electronics and vehicle control. i am stuck on how to approch such questions so gaining an insight on how to approach will be helpful. thanks
Relevant answer
Answer
Muhtashim Altaf MATLAB tutorial might help
  • asked a question related to Electronic Engineering
Question
11 answers
Does anyone have access to any of this article? I have already tried to contact some of the authors, but without success. I don´t speak Mandarin so is very difficult with CNKI where they are available through payment. I can not understand even the payment method or if I would have access from US. Thanks in advance for any help.
P.S. Even with google translator it was impossible understand the database.
DU Yu-ming YANG Jian-yu (College of Electronic Engineering, UESTC,Chengdu Sichuan 610054, China)
Linear FMCW radar is a kind of high-range-resolution radar, and motion compensation is a key problem to realize high range resolution. A multiple repetition frequency waveform is adopted and a Doppler frequency cluster (DFC) algorithm is proposed, which is capable of recovering true velocity from the coupled velocity estimation directly. Aiming at solving resolution of multiple targets, a match algorithm based on mean square error is also proposed. The combination of the above two methods realizes distance and velocity decoupling for multiple moving targets. The result of simulation verified the effectiveness of the methods, the velocity estimate performance of DFC algorithm improve obviously contrast to Chinese remainder theorem.
Relevant answer
Answer
Ana María Rojas-Gómez check your inbox i have sent you
  • asked a question related to Electronic Engineering
Question
4 answers
The 2023 ranking is available through the following link:
QS ranking is relatively familiar in scientific circles. It ranks universities based on the following criteria:
1- Academic Reputation
2- Employer Reputation
3- Citations per Faculty
4- Faculty Student Ratio
5- International Students Ratio
6- International Faculty Ratio
7- International Research Network
8- Employment Outcomes
- Are these parameters enough to measure the superiority of a university?
- What other factors should also be taken into account?
Please share your personal experience with these criteria.
Relevant answer
Answer
Cenk Tan; There are, of course, several websites that rank the universities worldwide. However, QS is the most famous of which.
  • asked a question related to Electronic Engineering
Question
4 answers
I would like to know the areas of Electrical and Electronics Engineering in which Java can be applied. Please give your inputs along with some materials to be followed.
Relevant answer
Answer
IoT
  • asked a question related to Electronic Engineering
Question
15 answers
I want to know the Scopus or SCI journals for electrical and electronics Engineering, which provide a fast review process without a publishing fee. ??
Relevant answer
Answer
Now a days most of the SCIE journals covers three months. This much of time is really required for the the process. Don't count the days, Go for good journals.
  • asked a question related to Electronic Engineering
Question
30 answers
My first degree was in Electrical and Electronics Engineering. Presently, I want to obtain a master degree in electrical engineering. I am looking for possible topics for my master thesis. The subject of my master's thesis is renewable energy (especially wind).
Relevant answer
Answer
I think it would be interesting for you to invest in geothermal research. Who knows about the efficiency of steam turbines, or most efficient heat exchangers? Saw interesting systems in New Zealand in 2012, Taupo plant (https://www.mbie.govt.nz/building-and-energy/energy-and-natural-resources/energy-generation-and-markets/geothermal-energy -generation/).
Looking ahead, heat exchangers, steam turbines and control systems for these thermal equipment will be very useful when nuclear fusion becomes available.
Good luck!
Prof.Wiltgen
  • asked a question related to Electronic Engineering
Question
13 answers
HFSS and Maxwell were made by Ansoft in the last century, and there actually were little problems with them. You could always trust the simulation provided by those systems.
However after Ansoft was absorbed by ANSYS, nothing was improved in solvers from engineering point of view. Instead some crazy non-scientific poorly documented things were introduced, probably programmed by game and CGI designers without any thoughts of engineering application.
One of the craziest thing I discovered lately is ANSYS's "closest point interpolation".
What is the "closest point" value, you may guess? Well, I think it is obvious - a value of the point found closest to the coordinate of interest.
It would be a very good approach feeding the discrete precalculated input fields, or material parameters for precisely simulating complex designs.
However what does ANSYS think about the closest point values!? You may be surprised.
Below, I show you a test of the clp() function, which SHOULD find a value of the closest point from the dataset "$dataset" for every mesh node with coordinates XYZ.
It should be placed in the material editor, in any property cell as clp($dataset, X,Y,Z).
According to manual, X,Y,Z, are provided in SI units, i.e. in meters. The output should be in the dataset units, but it is not, recognized by HFSS on practice. So I recommend making it unitless, and multiply by the desired unit, like clp(...)*1cel.
Now I define a simple dataset with a script:
<code>
dim pushdata()
redim pushdata(1) 'generate the data incrementally in dynamic dataset
pushdata(0)="NAME:Coordinates"
pushdata(1)=Array("NAME:DimUnits", "", "", "", "") 'in meters
for x = -1.1 to 1.1 step .1 'in millimeters
  for y=-1.1 to 1.1 step 0.1
    for z=-1.1 to 1.1 step 0.1
      redim preserve pushdata(ubound(pushdata)+1)
      pushdata(ubound(pushdata))=Array("NAME:Point", CDbl(x/1000), CDbl(y/1000), CDbl(z/1000), 1) ' see that "1" in the end. it is a value of "1" inside the Unit-BOX
      if ((abs(y)>=1) or (abs(x)>=1) or (abs(z)>=1)) then
        pushdata(ubound(pushdata))=Array("NAME:Point", CDbl(x/1000), CDbl(y/1000), CDbl(z/1000), 0) ' see that "0" in the end. it is a value of "0" AROUND the Unit-BOX
      end if
    next
  next
next
oProject.EditDataset "$Dataset", Array("NAME:$Dataset", pushdata) 'write the dataset to HFSS (ANSYS EDT))
</code>
Now lets see what the clp() function reads out from the dataset, and substitutes to material properties:
See the yellow and red lines on the plot below.
Obviously, those are NOT ones(1), and NOT zeroes(0), as one would expect.
I do not know what is that, but it is not a simple bug. I checked it in ANSYS EDT 2021 R1, and R2, both. It is a way how the programmer's head works.
Crazy stuff.
And we are forced to pay hundreds of thousands (some organizations pay millions) of Dollars for that, risking the corporate security btw. Because EDT is a security hole requiring Internet connection to work, and providing a backdoor for ANSYS, and anyone who could exploit that, to your system.
Relevant answer
Answer
Dear sir:
Thank you for sharing this important and valuable information .....
With best wishes....
  • asked a question related to Electronic Engineering
Question
9 answers
I have been studying quantization in context of Digital Image Processing. I referred to the 4th edition of the book titled "Digital Image Processing" by Rafael C. Gonzalez and Richard E. Woods.
In the book, the intensity quantization levels are defined as
L=2^k
where k is an integer.
Now the first thing that comes to my find is why is that the quantization levels should be integer multiple of two and why not just any integer in general.
A paragraph has been attached regarding this from the book.
Then I found a homework problem and its solution online which are both attached as images.
In the homework question, I believe n is used in place of k to calculate bits per pixel or bits per picture elements. While k was defined as integer in Gonzalez, here n comes out to be 3.32 bits per pixel (not an integer). Isn't it a contradiction?
Relevant answer
The colleagues really gave satisfactory answers to your questions. However, I have to stress the main cause of using the binary numbers in signal processing.
It is the available electronic devices that impose the number system used in digital computers and consequently signal processing.
There are two major electronic devices imposing the binary system:
The memory cells are binary that is a cell sores either logic one or logic zero.
So, to wright or read them directly they have to handle binary numbers.
The other major device is the arithmetic and logic unit. It also use binary numbers in their operations.
So, any other signal format must be converted into the binary from including the samples of analog signals. Every sample must be converted into n bit code. Which is a strings of one and zeros.
The conversion from analog to digital and vice verse is accomplished by A.D converters. According to the required resolution, every sample is represented by an n bits binary codes.
Best wishes
  • asked a question related to Electronic Engineering
Question
3 answers
The Mission "make in India" is promoted by the government recently. But "made by India" is necessary in the current crisis.
Researchers are rapidly increasing on Electronic Engineering field. Especially in India, No. of Publications and No. of Ph.Ds are increasing to reach a new peak every year. But most of the research papers,thesis are only in paper with out product outcome. What kind of initiation is required from government side in this regard? Is conventional politics affecting the development of Science and technology?
The discussion is open.
Relevant answer
Answer
I think to T Thammi Reddy point, it is only a Trillion rupee ($14 Billion) industry in India. The current cost of a 14nm fab (which is not state of the art, but state of practice) is around $14 Billion, so it is difficult for the semiconductor industry in India, whose entire market is less than or equal to the value to build one moderate technology factory in that industry, to grow in any meaningful way. India has huge capacity to assemble and test finished semiconductor products, but does not have any significant capacity to produce the underlying semiconductor die, which require these very large, and expensive factories. These factories also typically take years to build in countries with completely developed semiconductor fab industries, so building one in a new locale will probably take even longer. I would imagine the construction to take at least 8 to 10 years. In addition, there are a number of ancillary advanced high technology industries which must exist to support the semiconductor fabrication industry, which India also does not currently have, which would also need to be setup and successful prior to the start of any initiation of a semiconductor fab factory.
The Indian government would not only need to provide very lucrative incentives to all of these industries (free money, free loans, complete bankruptcy protection, and guaranteed bailouts), as the governments of South Korea, Taiwan, and China have done in order to catch up to more established semiconductor industries in the USA, Japan, and Europe, but also guarantee a return on the investment by either requiring large portions of electronics purchased by the government (offices, schools, military), or complete tax exemptions and subsidies until profitability is reached. In the instance that all electronics purchased by the government must be locally made, there will be a 5 to 10 year gap during which the local electronics will be inferior or more expensive, or both to those imported from other countries, which will make non-subsidized or non-government sales more difficult. The Indian government would need to have these policies in place for at least 15 to 20 years, independent of changes in the government or leading party, to get investors interested in such a project.
Semiconductors are a fundamentally expensive, slow, and typically a low margin industry, so unless there is a concerted effort from the Indian government across all political parties, the private sector will not risk tens of billions of dollars to create an industry where one doesn't exist if there are better areas in which to invest said billions.
  • asked a question related to Electronic Engineering
Question
14 answers
Environmental Engineering, Electrical engineering, Mechanical Engineering, Electronics Engineering
Relevant answer
Answer
Raindrop falling from the sky possesses kinetic energy, where K.E=1/2 mv2. However average mass of a raindrop is too small to produce usable amount of energy for household needs. The idea is to increase the size of the raindrop, as such it can be used to turn an electric generator as it falls down from a height. Please read my article in research gate on how to do it.
  • asked a question related to Electronic Engineering
Question
120 answers
We had a problem with "negative resistance" since it represented two different types of resistances - "true negative resistance"
and "differential negative resistance"
Now we have a similar problem with "negative impedance" since it represents different things in electronics and electrotechnics...
IN ELECTRONICS, we believe that all natural passive components (resistors, capacitors and inductors) absorbing energy from the input source have "positive impedance" (or simply "impedance"). So, from this viewpoint, the impedances of capacitors and inductors have the same positive signs. Conversely, the artificial electronic circuits - NICs (negative "resistors", negative "capacitors" and negative "inductors"), behaving in an opposite way (adding energy to the input source in the same manner as the according passive components do it), have a true "negative impedance". So, this classification regards to the way of processing energy - "positive impedance" means consuming while "negative impedance" means producing energy; "positive impedance" means "ordinary impedance" while "negative impedance" means something opposite as "inverse impedance", "opposite impedance" or "anti-impedance".
IN ELECTROTECHNICS, they classify the impedance of the reactive elements capacitor and inductor according to their behavior in time when a DC input voltage is applied - "negative impedance" symbolizes an "increasing voltage opposition" while "positive impedance" symbolizes a "decreasing voltage opposition". From this viewpoint, the impedances of capacitors and inductors have opposite signs.
IN ELECTRONICS, BOTH CAPACITORS AND INDUCTORS HAVE POSITIVE IMPEDANCE WHILE IN ELECTROTECHNICS, CAPACITORS HAVE NEGATIVE IMPEDANCE BUT INDUCTORS HAVE POSITIVE IMPEDANCE.
This concept is extremely simple, clear and intuitive if we think in terms of voltages when we apply a constant input voltage to the elementary RC and RL circuit. Then, voltage drops appear across capacitors and inductors; they change in a different (opposite) way through time but both they are voltage drops. Conversely, voltages appear across negative capacitors and inductors; they also change in a different (opposite) way through time but now both they are (electromotive) voltages, not voltage drops.
After these speculations, it is interesting to remember what a negative impedance converter did. What does it convert? Does it make a capacitor behave as an inductor and v.v., an inductor as a capacitor? No, it doesn't. A gyrator can do this magic. A negative impedance converter can make capacitors and inductors behave as sources (negative impedance elements) instead as passive elements having positive impedance:
I have presented these speculations in the archived Wikipedia talk page about negative resistance:
I have inspired to ask this question by the enthusiastic speculations of Tolga Soyata in the related questions about capacitor and inductor:
Relevant answer
Answer
Dear Cyril Mechkov sir,
I don't have much idea about the fabrication of ideal voltage source and ideal current source. But I think, ideal voltage source doesn't exists in real. It's only for the comparison purpose just like the ideal diode. But a practical voltage source can be used to made to act as an ideal voltage source if the source resistance (RS)is made smaller as much as possible so that the terminal voltage across the load is almost independent of load resistance. In ideal voltage source, this Rs is zero.
VL= VS*{RL/(RL+RS)}
Similar analysis can be made for an ideal current source
  • asked a question related to Electronic Engineering
Question
5 answers
I have to compare five level MLI in term of efficiency and THD which has less number of switches.
Relevant answer
Answer
  • asked a question related to Electronic Engineering
Question
10 answers
The op-amp will be used in the physical layer of the USB 2.0 PHY. 
Relevant answer
Answer
Dear Nam ho sir,
The best way to increase the bandwidth of an opamp is by decreasing the closed loop voltage gain of opamp.
Explanation: Opamp has a very low bandwidth(around 5Hz) and to increase the bandwidth, we apply negative feedback which decreases closed loop gain. Since gain*bandwidth=constant, so bandwidth increases in case of negative feedback.
  • asked a question related to Electronic Engineering
Question
15 answers
Inverse bias of an NPN Transistor
-----
I have heard that if we bias the collector and emitter of an NPN transistor inversely, its gain will be decreased in comparison with the correct bias condition.
Could you please tell me why?
Relevant answer
Answer
I agreed with all the answers given above Morteza Shabanzadeh sir. Reversing the role of emitter and collector with decrease the forward current since collector(which is now playing the role of emitter) is not heavily doped to emit the charge carriers like the emitter region. This is the main reason, why you get a reduced gain in this case. There is one more reason, emitter being heavily doped(acting as collector now) will have a very low breakdown voltage, so you can not operate it at higher voltage level.
  • asked a question related to Electronic Engineering
Question
5 answers
Hi!
I have started working on a project "floating sensor networks (FSN) for continuous water quality monitoring". For which I need simulator to measure Like, pH, Turbidity, Salinity, Temperature, DO, EC, etc. Rather than going with real time deployment of FSN for measuring water quality sensors.
Objectives of the Project:
A. Water Quality Measurement
B. Reliable Data Transform
C. Congestion Control
D. Deployment Strategy
E. Energy Harvesting
All objectives should be carried out simulation based. Kindly suggest whether this work will done via simulation design (either partially or whole) 
Thanks in Advance.
Relevant answer
Answer
Dear Sarang, did you find any suitable simulation software? We also need it for a small project we are working on
  • asked a question related to Electronic Engineering
Question
5 answers
Eg to find emissivity or radiant exitance based on temperature.
Relevant answer
Answer
  • asked a question related to Electronic Engineering
Question
15 answers
When I was an engineering student, while investigating a circuit schematic, I was often discouraged by a device whose symbol I was not familiar with. Thinking that it was a different device, I was usually giving up. In some of the cases, I was finding out (much later) that the device was actually just a regular device (e.g. an inductor or a Zener diode, etc.) with another symbol accepted/used by some other engineers.
When I started to teach electronics, I noticed that I should make convincing explanations for my students to relax them about such occasions. For example, I mention multiple symbols used for Zener diodes, along with the meaning/purpose of essential items of each symbol version. Unfortunately, sometimes I cannot convince some of the students about this many versions of symbols used for the same specific device.
This issue can be an important problem when you are publishing or reading papers in different scientific journals.
Now, I remembered another case -although not very similar-, namely the unit of electrical conductance, which is given with the unit "Siemens", as well as with 1/Ohm, represented by Ω-1 or by and even by "mho" (Leaving away the "inverted omega" symbol which I also regard as unusual, I have always thought that, Georg Ohm would not be happy about the "mho" unit).
Of course, some symbol versions (e.g. some of the ground symbols given in the figure) may represent a slightly or substantially different property/behavior. However, many people occasionally use those different symbols to represent the same specific device. With no doubt, that's another aspect of the "multiple symbols" issue.
For sure there are multiple standards that we cannot alter to fix a unique symbol for a specific device.
On the other hand, this "multiple symbols" issue often creates problems, especially for the students who are in a struggle to learn/understand new devices.
The "handy" versions of the symbols (like the last ground symbols in the figure) preferred by some instructors may complicate the issue further.
A symbol which reminds of the device's main behavior, points out to difference and similarity with another device, provides ease of drawing and ease of spotting the device on a schematic, etc., can be assumed a good symbol (This can explain, for instance, the different versions of Zener diode symbols).
I know that many of you may think that I am exaggerating the problem. Nevertheless, I would like to know what others think about this issue.
Any personal experiences or suggestions which may be helpful especially for teaching will also be appreciated.
Best regards...
Relevant answer
Answer
In my first answer, I referred to the symbols in the upper row of the attached file. These replaced those in the lower row which were a former DIN attempt to make German symbols "unique" but those older ones had at least some resemblance to the more widespread symbols.
  • asked a question related to Electronic Engineering
Question
25 answers
Normally, the mechanical energy harvester, such as piezoelectric generator (PEG), can drive small electronic loads directly after rectified the signal by converter. However, one can see the main issue of discontinuous operation of loads, e.g., the blink of LEDs that depends on the periodic force applied. To solve this issue, the PEG is connected to the capacitor to store the charge in specific period, and then discharge to the loads. After discharged, the electronic loads can operate stably, but they can do only in short period.
So, are there the methods to extend the discharging time of capacitor? For example, some circuit that can control the ability of charging-discharging of energy harvesting system.
I have also attached the additional information (.jpg) to describe the problem.
Normally, capacitor needs to charge for a long time due to high impedance of PEG, and rapidly discharge due to low R of electronic loads.
Best regards,
Thank you
Relevant answer
If this is the case then you have to:
either increase the capacitor and increase the charging time to full charge the capacitor. Supercapacitors may help you increase the the discharging time.
The other solution is to increase the generated power from the PEG.
The concept is to size the source to be able to supply the load for the intended duration.
Do you use full or half wave rectifier. If you use full wave rectifier you will double the charging current and therefore double the power!
Best wishes
  • asked a question related to Electronic Engineering
Question
13 answers
Hi, a friend wants to publish an article related to the mobile robot navigation slam algorithm. Could someone please suggest a few journals with low impact factor?
Relevant answer
Answer
  • asked a question related to Electronic Engineering
Question
23 answers
Online mobile banking is dynamically developing because pro-development factors continue to outweigh the factors limiting this development.
The main development factors are the reduction of operating costs for banks and facilitating remote access to banking services, including mobile payments to clients.
Currently, the only barrier to development can be increased activity of cybercriminals stealing data from online banking clients, hacking into online bank accounts of customers and robbing clients of financial means. However, banks have so far quickly identified this type of cybercrime incidents and have been gradually improving their mobile banking security systems.
Another factor limiting the development of online mobile banking may be the number of bank customers interested in this type of banking.
What are the other key determinants of the development of mobile banking?
Please answer
Thank you very much
Dear Friends and Colleagues of RG
I described the problem of cybercrime in publications:
I invite you to discussion and cooperation.
Thank you very much
Best wishes
Relevant answer
Answer
During the SARS-CoV-2 (Covid-19) coronavirus pandemic, the e-commerce industry accelerated its growth. The scale of purchases and payments made via the Internet has increased. In addition, due to anti-pandemic security, more and more citizens use mobile banking implemented from the smartphone level and make contactless payments with a smartphone, avoiding cash. Therefore, the development of internet banking could partially offset the decline in lending caused by the decreased interest in bank loans.
Best regards,
Dariusz Prokopowicz
  • asked a question related to Electronic Engineering
Question
2 answers
I am working on the project of LC voltage controller oscillator. i have design a LC VCO for C band application. I am facing problem to design the layout of inductor on L-edit of Tanner EDA tool. can anybody help??
Relevant answer
Answer
FromTanner there is @ MIT or Cornel University a very old document from 2008 related probably to the old Tanner v13 (tdb-based layout: Tanner data base, since 10 years Tanner is using OA open access for storing layout views!) about the Dev-Gen 13 (Device Layout Generator).
This document is related to a very old Tanner L-edit release, therefor any statement about the existance of Dev-Gen in recent Tanner 2016/2020 releases is doubtfull.
You will need the scripts behind for the newer OA-based Tanner L-edit releases....
see page 11 related to inductor Dev-Gen
  • asked a question related to Electronic Engineering
Question
6 answers
Expansion of SU in SU-8 Photoresist?
Relevant answer
Answer
SU-8 Photoresist
By: Frederik Ceyssens and Robert Puers
SU-8
  • asked a question related to Electronic Engineering
Question
9 answers
I use a piezoelectric sensor, a humidifier electronic circuit and a 32-volt power supply to generate high-frequency ultrasound waves. I use these waves to atomize the liquid.
the problem is that the viscosity of the liquid is high, so the generated ultrasonic waves cannot atomize the liquid well.
any idea for this problem?
for example, can i use two circuit with two supply power and connect their output to the sensor to higher the sensor power? or ...
Relevant answer
welcome!
I think the problem is not only in the power of the ultrasound waves.
As the ultrasound generator invokes harmonic waves then
P= pm sin wt where p is the pressure, Pm is the peak value of the pressure w is the angular frequency.
Assume that the speed of the pressure waves is v,
Then the wavelength lambda= v/f,
The division of the material is the matter of lambda.
You have to decrease lambda to the about double the interatomic distance.
So you have to concentrate your effort to see t5he effect of decreasing lambda oo your liquid.
Best wishes
  • asked a question related to Electronic Engineering
Question
13 answers
i used [peanoisy, snrnoisy] = psnr(A, ref);
Relevant answer
Answer
I agree with Dr. Abdelhalim Zekry
  • asked a question related to Electronic Engineering
Question
7 answers
Is there some effective and equantitative methods to measure the fault tolerance of combinational circuits and sequential circuits?
Relevant answer
Answer
Fault tolerance is the property that enables a system to continue operating properly in the event of the failure of (or one or more faults within) some of its components. If its operating quality decreases at all, the decrease is proportional to the severity of the failure, as compared to a naively designed system, in which even a small failure can cause total breakdown. Fault tolerance is particularly sought after in high-availability or life-critical systems. The ability of maintaining functionality when portions of a system break down is referred to as graceful degradation.
For Fault tolerance measured we have:
  • asked a question related to Electronic Engineering
Question
6 answers
I'm basing my question on the paper: "Efficient Maximally Stable Extremal Region (MSER) Tracking". It's not clear to me how to compute the stability measure of a node when it has multiple descendants with the same grey-level. Does the node have more than one stability measure assigned to it?
Relevant answer
Answer
  • asked a question related to Electronic Engineering
Question
9 answers
Hello, I am about to start my final year as an undergraduate Electrical and Electronic Engineer at The University of Nottingham Ningbo China. I am going to be writing my dissertation this year and was hoping someone could give me a bit of a perspective upon the active general research topics that would be worth focusing effort upon, or a certain area of research to consider.
I would also be looking forward to your helpful advice and suggestions regarding dissertation writing.
Relevant answer
Answer
I second Frederico that many staff members in specific specialization such as electrical and electronic engineering propose Bsc projects for their students to exploit their effort in solving real existing problems in such engineering branches.
There are many subdivisions under electrical and electronic engineering.
In which division you have an interest.
So the question is so broad and includes all courses in electrical and electronic engineering.
For example:
- power generation
-power transmission
-power distribution
- power control
- Power electronics
- renewable energy sources, solar, wind etc
- In Electronics:
- Electronic materials
- Electronic devices
-Electronic circuits analog and digital
- Electronic systems for different applications
as computing, signal processing, communications, instrumentation. ..etc
I would propose that you work on electronic applications in advanced systems such that as internet of things. biomedical applications and communications system.
If you narrow your target one can propose for you you a specific research project.
Best wishes
  • asked a question related to Electronic Engineering
Question
8 answers
In this forum it is required to discuss the effect of the n emitter layer parameters on the the conversion efficiency of the Si np solar cells. These parameters are the junction depth, the doping concentration,the minority carrier life time and the surface recombination of the minority carriers.
Relevant answer
Dear Jayakumar,
welcome!
Hope you are well!
The heavy doping concentration has the followings benefits:
- It reduces the reverse saturation current of the solar cell n-p junction and thereby leads to an increase in the opencircuit voltage Voc. This improves the photo conversion efficiency.
- It decreases the resistance of this layer and thereby contribute to the reduction of the series resistance. It leads then to an increase in the fill factor and the PCE.
- The metal silicon contact will be ohmic and its resistance will be smaller leading to higher PCE.
Best wishes
  • asked a question related to Electronic Engineering
Question
8 answers
As we have seen that most powerful and expensive quadcopters being swept away by prevailing wind gusts and losing connection with the controller, and even that “fail-safe” GPS-enabled Return To Home feature will struggle and oftentimes fail when flying into a strong headwind.
How to make it reliable and robust for sever weather conditions?
Relevant answer
Answer
First basic step is to define "strong wind" speed, and then compare that with the quadcopter's maximum speed. No Return To Home (RTH) feature can be effective as long as wind speed > quadcopter maximum speed so "speed" has to be first defense. Once quadcopter max speed is exceeded, it is just be a matter of time before the quadcopter is out of ground control range; options then are to land, and wait for input, (maybe not a great option in heavily wooded areas, or over water), or switch to an autonomous mode which will attempt return to base GPS location as long as power allows.
Next consideration would be turbulent response; in strong winds, particularly in urban areas, where wind gusting around buildings will make control response times critical.
Note also that GPS-enabled RTH features will struggle with tall obstacles, be they trees or high rise buildings, that block the (most direct) return path.
  • asked a question related to Electronic Engineering
Question
6 answers
I was getting stuck on the coefficient part of the summation.
  • asked a question related to Electronic Engineering
Question
19 answers
Layout of VLSI circuits.
Relevant answer
Answer
Electric VLSI Design System is an opensource IC Design tool. Good help/tutorials are available at cmosedu.com
In combination of another free tool LTSpice, you can have compete pre and post-layout simulation experience. Also, LTSpice supports BSIM4 models and you can use them by adjusting Lambda accordingly in the ELECTRIC.
  • asked a question related to Electronic Engineering
Question
44 answers
While the COVID-19 Pandemic is continued, I want to present to my students some of the laboratory experiments, unfortunately, there is a curfew in my country and I can't reach my lab to filming the experiments.
So, I am looking for an alternative that makes me able to show my students the experiment results, via virtual oscilloscope, power supply, etc.
Relevant answer
Dear Ahmed,
You can use the electronic work pinch EWP it is thought to be a virtual electrical and electronic circuit laboratory. I think it is the most appropriate software for experimenting and demonstrating the operation of the elements devices and circuits.
This program has a spice core and it will remain useful the student in all their stages of educations.
Best wishes
  • asked a question related to Electronic Engineering
Question
5 answers
Hello everyone,
I am in Electronic Engineering area and looking to start my research in the domain of Embedded System and HW/SW Codesign field.
I am a bit confused about where to start from ?
Please can you oriented me ?
Any kind of help will be really really really appreciated. Thanks
Relevant answer
Answer
Hi Kevin,
This my favourite area and yes it can be confusing and there is no certain answer. You can take different routes and approaches to address your problem.
You need to make sure you know what you need and what resources you have to achieve it. Well-defined objectives can also be a good start.
Best wishes,
Mani
  • asked a question related to Electronic Engineering
Question
12 answers
I know half of that energy is dissipated in heat in the resistance of the charging pathway, and only QVb/2 is finally stored on the capacitor at equilibrium
I'm just going to lower the resistance of the charging pathway so I will get more energy on the capacitor , but why this doesn't work ?
Relevant answer
Charging the capacitor by using potential energy source or voltage source through a frictional media such as the electrical resistor will cause losing the electrical energy into friction, since the current passing to charge the capacitor will meet friction in the resistance. So, in the charging process the potential energy of the charging source is converted into kinetic energy where a fraction of it, commonly one half will be converted int heat and the other half will be stored.
In order to avoid this loss one first store the kinetic energy into an inductor and then transfer this stored energy into a potential energy in a capacitor to be charged.
So charging capacitor through kinetic energy storing element will be not lossy if the inductor is ideal.
That is substituting the lossy resistor by storing lossless inductor will resolvethe problem of the losses.
It is the same idea of the pendulum.
Best wishes
  • asked a question related to Electronic Engineering
Question
4 answers
Although my code does not have error apparently, it doesn't offer proper solution. I have attached some parts of my code.I would be grateful if you could give me some tips on how to implement sos1 variables in gams.
Relevant answer
Answer
That's easy to be implemented!
Assume a typical mathematical program with equilibrium constraints as below:
Min f(x,y)
s.t.
g(x,y)>=0
y>=0
y * g(x,y) =0 (your complementarity condition i.e., 0<=y_|_g>=0)
-----------
To solve the problem above using SOS1 variables, you can reformulated it as follows:
Min f(x,y)
s.t.
g(x,y)>=0
y>=0
u = 0.5 * (y+g(x,y))
u - (vp + vn)=0
vp - vn = 0.5 * (y-g(x,y))
where, 'vp' and 'vn' are SOS1 variables that can be easily defined in GAMS as below.
----------
variables x , y , u;
SOS1 variables vp , vn;
----------
Good luck,
Morteza
  • asked a question related to Electronic Engineering
Question
7 answers
In the design of power converter ICs, sometimes the power switches are not given by the PDK. That means we have to design the power transistors as the switches (NMOS and PMOS).
Since the power loss causes by conduction loss and switching loss, the power efficiency of the converter is decided by a very well trade-off between these losses. The conduction loss depends on the Ron of the switch, that means larger switch (with larger Width of the transistor), the lower conduction loss. In the mean time, the switching loss increases since the parasitic capacitor of the power switch increase. 
So I would like to know the method of sizing the power switches in the converter for maximizing the power efficiency. Any ideas or recommendations/reference papers from you are highly appreciated. Thank you so much.
Relevant answer
For any MOS switch the losses can be expressed by this relation
ploss= Pstat + pdyn= Ion^2 Ron Ton/T +CVdd^2/T where T=1/f with f is the switching frequency. Ion= un cox w( ,Vgs-Vtn)^2/2L, Vgs=Vdd , Ton = T/2 for square wave operation with a duty ratio =0.5, C= Cgs= cox wL, Ron is also a function of w. So, can get an optimum w as the on losses decreases with increasing w while the dynamic losses increases. Therefore there will be an optimum value which give a minimum of the power losses. L is taking as a minimum feature size.
Best wishes
  • asked a question related to Electronic Engineering
Question
2 answers
I am looking at the integration of Bi4Ti3O12 thin films on Ultrananocrystaline diamond (UNCD) substrates. I deposit my thin films using RF-Sputtering, but am unable to do in-situ substrate heating, so I rely on post deposition annealing to crystallize the thin films. I normally perform annealing in ambient atmosphere, producing good insulative, ferroelectric and dielectric properties.
However, due to the nature of the UNCD substrate, I have been limited to annealing the films under vacuum conditions.  From impedance spectroscopy, I have determined the films to possess a dielectric constant of 80, about 60% of what it should be when annealed in atmosphere. I am looking for references to confirm the dielectric properties of BTO thin films when annealed in vacuum. If anyone could provide any, I would be extremely grateful.
Best Wishes
Jamie
Relevant answer
Answer
Hruang science invites research papers for the current edition in Science, Engineering , Technology,Pharmacy, Agriculture,Mining, Marine, Agriculture, Fashion designing and Animal Sciences.
All papers are published free of charges.
plagiarism is not entertained
for details visit us at www.hruangscience.com
  • asked a question related to Electronic Engineering
Question
13 answers
Is there any electronic part that made from pure (metallic) zinc?
Relevant answer
Pure zinc is used as an electrode in a Daniell cell and also in dry batteries.
  • asked a question related to Electronic Engineering
Question
27 answers
I'd like to know about the best method to defined a fuzzy rule base for fuzzy logic controllers, most of references said experience knowledge is the best way, but what are the other parameters?
Relevant answer
Answer
Useful link from , thanks for sharing.
  • asked a question related to Electronic Engineering
Question
19 answers
Could you please tell me the electronic parts which contain germanium?
Relevant answer
Answer
Dear Sina,
due to the low band gap of about 0,67 eV, Ge is used for photodetectors (wavelength < 1,862µm.). Therefore, the efficiency of solar modules could be enhanced to the infrared range. Nevertheless, Ge-diodes are very sensitive for temperatures above 70°C. An application for temperature sensors is possible. Diodes have a lower knee-voltage than Si. This may be a benefit for digital applications.
I used a High-purity Ge-detector for X-ray detection. Today, more Si-detectors are used for this purpose (Li-drifted SiLi-detector).
Generally, Ge is well recommended for special applications, but it is an expensive technique. Especially, the material is hardly to obtain. It is a material for military applications (guidance for rockets an so on).
With Regard
R. Mitdank
  • asked a question related to Electronic Engineering
Question
3 answers
Feel free to reference any literature in support of your replies.
Thanks in advance
Relevant answer
Answer
Australian Science journals
ASJs publish a research article free of cost for the first two issues as we are turning into electronic journals from the print mode.
Austra & Lian journal of Medical Sciences
publish all topics, Health, Medicine and Pharmacy
Austra & Lian Journal of Animal Sciences
Publishes all topics related to veterinary SCience
Austra & Lian Journal of Engineering & Technology
All engineering Topicshttps://www.australiansciencejournals.com/aljet
Austra & Lian Journal of Basic Sciences
All areas of Phisical Sciences, life Sciences, Social Sciences, Arts, Languages, Business & Management
submit papers online
Austra & Lian Science Journals
548 Fashion Avenue
New York, NY 10018
The U.S.A.
Phone: (001)347-688-8931
  • asked a question related to Electronic Engineering
Question
8 answers
I am trying to write my dissertation about automatic quantification of algorithms. These algorithms are written as a C function, which represents the behaviour of a VLSI circuit. The main purpose of the dissertation is to maximize the number of removed bits from the word-lengths of the signals describing a VLSI circuit, by finding a sub-optimal combination which fits a rule. The rule is that any combination must cause an error less or equals to a boundary error.
In order to find this suitable combination which is close to the error boundary and maximize the removed bits, my dissertation supervisor suggested to use local search algorithms. Due to the execution of the quantification will be made over a GPU (CUDA), I have found that the differential evolution and cellular genetic algorithm are suitable for a SIMD machine and easy to implement and execute in parallel. The constraints of the problem are: use of fixed point quantification, error produced at the outputs = fitness function and word-lengths from 1 to 22 bits (integer values). Actually, I have implemented the canonical DE (DE/rand/1/bin) and cGA (NEWS, 2D toroidal grid) over CUDA for any number of signals describing the VLSI circuit.
Before testing the algorithms with real VLSI circuits, I am testing them with a synthetic benchmark to confirm the related work and suggestions made about DE. This benchmark returns an output error (1 output circuit) based on this formula: sum in j elements of [ (element_j_of_individual_i - element_j_of_local_optimum) * 2 * factor ] with factor selected randomly for each element for 0,5 to 0,9 . Hence, if an individual of the population is an exact match of the pre-selected local optimum, the error returned by this fitness function will be 0. For an individual who has at least one element under the corresponding element of the local optimum will be discarded (and if it belongs to the initial population, will be regenerated until obtaining a valid individual).
Using this schema, the parameters of the benchmark are:
- population size of 5D, 10D, 15D and 20D (with D = number of signals describing the VLSI circuit), with each element in the population set randomly from 16 to 22 for each execution. ex: for D = 5, individual_number_0 = {14, 17, 21, 19, 20}
- randomly pre-selected local optimum from these values: {6,7,8,9,10}. ex: for D = 5, local_optimum = {7, 10, 6, 9, 6}
- ten executions trying to eliminate someway the bias caused by a pre-selected local optimum
- F = 0.5 and CR = 0.1
- the algorithm will stop when the local optimum is found or when all the generated offsprings are not valid and/or not better than their parents
For this set-up, I have found that for 50, 100 and 150 signals, the DE found the exact pre-selected local optimum for populations of 5D, 10D, 15D and 20D in the ten executions in several iterations (if requested, I could upload the iterations, timings, etc). For 200 signals the DE only found the local optimum for 10D, 15D and 20D. For 250 signals, only one execution of the ten for 20D found the local optimum; not founding it for any iteration of 5D, 10D or 15D. I have tried to relax the termination condition of the search by establishing an error boundary some way close to 0 (like 50, 70, 100 values) to find sub-optimal solutions for population sizes of 5D, 10D, 15D and 20D (D = 250). Although I have relaxed the termination condition, the algorithm stops without founding the local optimum.
I have found the Q&A from Stephen Chen: 'What is the optimal/recommended population size for differential evolution? ' but I do not know if these questions will fit my needs a priori, because I would like to use DE for VLSI circuits up to 400 signals in a first approach.
(Edit): added some examples: one randomly initialized individual in the initial population and one randomly pre-selected local optimum.
Relevant answer
Answer
Papers report that DE is sutable for optimization problems from low dimensional spaces to high decisión variables.
  • asked a question related to Electronic Engineering
Question
8 answers
Dear researchers,
I facing a problem regarding the model of wind turbine(DFIG or Full Scale converter) in DigSilent Power factory.
Actually i have to analyze the influence of different wind generator on power system small signal stability. I have modeled the DFIG and full converter model of wind generator with all the standard controllers from power factory library.
During modal analysis, i am getting some unstable oscillatory mode which is actually due to improper tuning of controllers. I tried in different ways but all in vain.
Could anyone of you help me regarding this issue?
Best regards,
your new research fellow
Relevant answer
Answer
Jawwad Siddique Can you please send me the sanpshot of your DFIG model you made in Digsilent. I urgently need it. Thanks.
  • asked a question related to Electronic Engineering
Question
13 answers
Antenna design in one software varies with result in another software. Also which one is better for mesh analysis.
Relevant answer
Answer
For antenna parameters HFSS is quite good choice.In case of it's physical and equivalent circuit simulation please try another software, ADS
  • asked a question related to Electronic Engineering
Question
9 answers
What is the main difference between dual band and dual radio?
Let
A system equipped with:
Dual Band= 2.4 GHz and 5 GHz
Dual Radio=802.11 and 802.14.5
where 802.11 with 5GHz is deploy between air to air link
and 802.11 with 2.4 GHz between air to ground.
similarly some nodes are also connected through 802.15.4 with 2.4 GHz between air to air.
The above system is dual band dual radio
or triple band dual radio
or triple band triple radio?
Relevant answer
Answer
Dual band refers to a device which uses two different frequencies to communicate.
Dual radio refers to a device which uses two different protocols to communicate.
Maybe an illustration would help. A dual band device is like a person at a party who can move between two different rooms (different frequencies) to talk with other people, while a single band device would be limited to talking to people in only one room. On the other hand, a dual radio device can speak with people who speak in two different languages, while a single radio device can only speak one language.
A dual radio device is typically used as an intermediary between two different networks like 802.11 (like WiFi) and 802.15.4 (like many wireless sensors).
  • asked a question related to Electronic Engineering
Question
14 answers
I am running optimization using Optimizer Tool in CST 2014. I do not know why after about 300 iterations, the optimization is suddenly stopped with an error showing up (see figure). I need to keep running my optimization but it always is stopped suddenly. In my design, each iteration takes about 5 minutes. Is there any one who has the same problem? Can any one help me to solve this problem? Thank you.
Relevant answer
Answer
1. Clean up unnecessary old result files from the directory and re-simulate
2. If no.1 doesn't work, save the project in different name and re-simulate
3. If no.2 doesn't work, redraw the design, and re-simulate.
Hope it fixes your problem. Good luck.
  • asked a question related to Electronic Engineering
Question
9 answers
I have designed a different topology of boost converter. I calculated the transfer function of the converter. Their is a zero at the right half plane.
1. What will be the effect of that zero on the stability of the circuit?
2. Can any one explain to me how i can analyze the Bode plot of this transfer function.  In the attachment is the bode plot.
3. Does PI controller will be suitable for the compensation in close loop system?
Relevant answer
Answer
Dear Aamir,
The right half plane zero has gain similar to that of left half plane zero but its phase nature is like a pole i.e., it adds negative phase to the system. Instead phase increasing from 0 to 90 degrees, its phase increases from 0 to -90 degrees. This causes delay in your system response which can lead to instability if not taken care.
The intuitive way of understanding right half plane zero can be as follows. Imagine you have a boost converter 24V to 48V i.e., duty of 0.5. Due to some reason, the input voltage has decreased to 20 and the output voltage falls to 40V if operated at 0.5. In order to restore output voltage to 48V, we have to increases the duty to 0.5833. Assume that, you have increased the duty from 0.5 to 0.5833. If you observe the output voltage closely, the voltage decreases below 40V instead of increasing to 48V and after some time the voltage starts increasing towards 48V.
The reason is that, we have increased the duty from 0.5 to 0.5833 i.e., we have increased the ON time of the switch from 50% to 58.33%. If you see the circuit during on time, the inductor is connected to the input source and the output is supplied by capacitor alone. So when we increase the ON time of switch, that much amount of time the capacitor discharges to the load which would decrease output voltage further compared to the previous switching cycle. If your controller is very is very fast, it assumes that the voltage is decreasing instead of increasing and it increases the duty further which eventually makes the system unstable. Ideally, your controller should wait for the output voltage to fall and then increase towards the desired value and then do corrective action if required. This is done just by making the system slow i.e., by selecting lower bandwidth (gain crossover frequency). In general, if you take one gain crossover frequency as one tenth of the right half plane zero frequency, your system will be stable.
This phenomena of instant fall in voltage and then raising towards the reference value becomes a right half plane zero in the transfer function. The instant fall in voltage in spite of increasing command (opposite action to that of the desired action) is the negative phase of right half plane zero. I hope this is helpful.
Regards
Srikanth
  • asked a question related to Electronic Engineering
Question
9 answers
how can I modify my input file in order that I will be able to read Highest  and Lowest Unoccupied orbitals (HOMO and LUMO) in output file either in scf or relax calculations?
Relevant answer
Answer
If you specify the nbnd value in your pw.x input file, the HOMO and LUMO values will be printed in the output file. YOu need to choose nbnd, depending on your system, pw.x documentation says;
for an insulator, nbnd = number of valence bands (nbnd = # of electrons /2); for a metal, 20% more (minimum 4 more)
  • asked a question related to Electronic Engineering
Question
8 answers
I have obtained s-parameters of a material placed inside a resonator. How can I extract its permittivity?
Relevant answer
Answer
To calculate dielectric and magnetic parameters from scattering parameters, you can read the application notes with calculation examples here in the attached file.
this will help you alot...
  • asked a question related to Electronic Engineering
Question
7 answers
This question is dual to the question below that I asked a few hours ago:
There, we began thinking what would happen when connecting the input voltage source in parallel to another voltage source (the output of a voltage follower) what was quite confusing for traditional thinking electrician and not so for electronics specialists. Here, we would like to know what happens if we connect the input current source in series to another current source (the dual situation). We would like to know it since we have the feeling that this is a powerful idea in electronics-:) Well, let's begin thinking...
It is obvious that we should apply the input current to the input of a current amplifier (e.g., a BJT) and to take the output current from its output. But we are curious enough to (try to) "blow" the input current into the output of the current amplifier (the BJT collector) and to take the collector voltage as an output. And we ask the same confusing questions:
Is this arrangement (two current sources connected in series) possible and correct from the basic electricity viewpoint? What would be the sense of this nonsensical connection? Can we use it somewhere in electronics? Can we see it in some existing circuit solutions? Can we see this idea in our life? Can we generalize it as a fundamental (particularly, circuit) principle?
BTW we have already managed to "blow" the input current into the collector of a BJT by applying a parallel-parallel negative feedback
but here we mustn't apply a negative feedback. Then?
As in the dual question, I have given a hint with the same attached picture. If this is not sufficient, look again at the link below:
I warn again: do not consider these speculations as an absolute truth; they show only my personal viewpoint at this phenomenon...
Relevant answer
Answer
Cyril, You are right. This topic can be debated :-)
Josef
  • asked a question related to Electronic Engineering
Question
6 answers
My research is all about the assessment of program outcomes of Bachelor of Science in Electronics Engineering by asking the employers of the graduates to rate them with a listed performance indicators. One of the comments of the external reviewer of my research is that ethical protocol is missing in my abstract. How can I address this?
Relevant answer
Answer
Dear Framses,
In addition to what has been said, I think you are required to include explanation about the ethical considerations in your research at the abstract level: this includes the process of obtaining ethical clearance and approval from by an IRB
  • asked a question related to Electronic Engineering
Question
8 answers
In grid-tied solar PV system if generated power by solar PV system is higher than the load requirement then the extra power will be exported to grid or if generated power lower than the load requirement then required power will be imported from the grid. How we can identify the imported and exported AC power flow?
Relevant answer
Answer
I agree with U. Dreher
  • asked a question related to Electronic Engineering
Question
10 answers
Suppose I have two material having high carrier density (hole=5x1022 cm-3 and electron =5x1020 cm-3).. will this two film form good quality diode?
Or I can make a diode putting one p and n type layer with higher resistivity in between the afore mentioned device i.e with structure p+-p-n-n+??
Which one would provide better rectification theoretically??
Relevant answer