Digital Electronics - Science topic

Digital Electronics

I am confused on the sampling rate and samples per record. If I can set values of sampling rate and horizontal time scale why is there option for samples per record. What does it mean?

Technologies typical of the current fourth technological revolution and Industry 4.0 have been developed and implemented in various sectors of the economy since the end of the last century. Technologies typical of the current fourth technological revolution and new technologies Industry 4.0 are used, among others also in the field of creating new solutions increasing the scope of energy savings. In view of the developing energy crisis, this is a particularly important issue at present. The key technologies of Industry 4.0 include: technologies improving analytical processes such as Big Data Analytics, Business Intelligence, Data Science, besides also cloud computing, artificial intelligence, learning machines, Internet of Things, robotics, horizontal and vertical data system integration, multi-criteria models simulation, digital twins, additive manufacturing, Blockchain, 5G, smart technologies, cybersecurity technologies, Virtual and Augmented Reality and other technologies of computerized multi-criteria data processing Data Mining. With the help of the above-mentioned Industry 4.0 technologies, it is possible to improve system solutions for saving electricity and / or heat as well as management systems for economical energy consumption, intelligent production of energy generated from various sources, energy security management systems, failure risk and energy blackout management systems, etc. The issue of improvement management systems for both energy production and its economical consumption is now particularly important in the context of the current energy crisis. In the future, not only subsequent energy and economic crises will increase the importance of using new technologies in order to increase the scale of energy saving, increase energy efficiency, energy storage, and build new sources of clean energy. In the future, the developing climate crisis will also increase the importance of this issue, as climate warming will generate greater energy consumption, e.g. by increasing the scale of installing cooling devices in various buildings.

In view of the above, I would like to address the following question to the Distinguished Community of Researchers and Scientists:

What is your opinion on this topic?

Please reply,

I invite everyone to the discussion,

Thank you very much,

Kind regards,

Dariusz Prokopowicz

I found that, latches can capable to hold the correct data even the data changes slightly before the falling edge of the clock.

What is the major difference between the pre-layout and post-layout simulation?

Other than LATEX, is there any tool/software to write a technical book where we can add figures and write equations

At schematic level design i need to add bitline capacitances in HSPICE Simulation. preferred model card is PTM.

RRAM device has metal/insulator/metal structure, in which insulating layer acts as an active switching layer. I am looking for any correlation between the crystllite size of the active switching layer's nanoparticles with resistive switching mechanism. Does the size of Nanoparticles control the switching mechanism?

Please share some relevant articles.

When I teach bipolar junction transistor (BJT) in the classroom, I emphasize "Cut-off", "Saturation" and "Forward Active Mode" as the 3 operation modes of BJT useful in digital and/or analog applications.

Finally, I mention the 4^th mode, namely "Reverse Active Mode", and reveal its properties to emphasize that a BJT is actually not symmetrical, i.e. emitter and collector cannot be interchanged in hope of a similar performance as in Forward Active Mode.

I also add that, although it is usually regarded as useless, I know of one specific application of Reverse Active Mode, namely TTL logic ICs (which have been manufactured/sold in > billions parts).

As many engineers familiar with digital electronics would know, input transistor(s) of a typical TTL logic gate (e.g. TTL NAND) operate in Reverse Active Mode for some input logic combinations.

I would be glad to learn other applications which benefit from Reverse Active Mode of BJT.

RRAM device consists M-I-M (Metal - Insulator - Metal) structure and in most of the RRAM device insulating layer plays important role in resistive switching between HRS (High Resistance state) and LRS (Low Resistance State).

Thanks

Can someone help me to solve this task below.

This is the reference http://www.bittpolytechnic.com/images/pdf2/ECE_Mobile%20communication%20e-books.pdf

Hi, a friend wants to publish an article related to the mobile robot navigation slam algorithm. Could someone please suggest a few journals with low impact factor?

Hello Folks

I am a recent graduate and started my career in the Power Electronics field. It's really great field and I am lucky to get an opportunity to learn PCB design, control of power supply, reliability analysis. My study background more related to power engineering and I want to be an expert in Analog Electronics, Digital Electronics, and Embedded control systems. Can you please anyone guide me for each field (Analog, Digital Electronics, Embedded system) what resources I should use? It would be really great help

Thanks

Avi

This project is related to transient states.

I want to study the behaviour of a circuit (like a current source) by suddenly increasing the resistance from one value (5 ohms) to another (10 ohms).

At first, I used Brick resistance, which I could not achieve to my goal.

Now I use Carbon resistance which has not worked.

Which resistance are used for high frequencies (100ns; 10 Mhz)?

If I use carbon resistors, is there a proposed circuit that I can increase their frequency?

For a OFDM signal, after DAC with 12.5Gsa/s sampling rate, what is the bandwith?  How to calculate?

If the OFDM signal with Hermitian symmetry, what is the bandwith? The Hermitian symmetry will reduce the bandwith?

For a OFDM signal with DAC sampling rate of 12.5Gsa/s, after ADC with 25Gsa/s, what is the bandwith? After down converter, what is the bandwith?

I'm very  confused by the  bandwith calcluation of the OFDM signal? How to calcluate the bandwith?

Forward Error Correction (FEC) schemes square measure a necessary a part of wireless communication systems. The number of symbols inside the availability encoded message is enlarged in an passing controlled manner thus on facilitate a pair of basic demands at the receiver one is Error detection and alternative is Error correction. In telecommunication and data theory, forward error correction (FEC) (also referred to as channel coding]) may be a system of error management for knowledge transmission, whereby the sender adds consistently generated redundant knowledge to its messages, additionally referred to as associate error-correcting code (ECC). In digital electronic systems, data is painted in binary format (1's and 0's).When binary data is passed from one purpose to a different, there's continually some likelihood that a slip-up are often made; a one understood as a zero or a 0 taken to be a 1. This can be caused by media defects, electronic noise, component failures, poor connections, deterioration due to age, and other factors. When a bit is mistakenly interpreted, a bit error has occurred. Error correction is the process of detecting bit errors and correcting them and can be done in software or hardware. For high data rates, error correction must be done in special-purpose hardware because software is too slow. A group of bits in a computer has conventionally been referred to as a "word.” Each bit can be thought of as one of two "letters,” 0 or 1. Error correcting systems add extra or "redundant" letters to computer words. The extra letters (bits) add a certain structure to each word. If that structure is altered by errors, the changes can be detected and corrected.

Papers:

Rolf Johannesson and Kamil Sh. Zigangirov. Fundamentals of Convolutional Coding. IEEE Press, 1998.

Zou Decai Nat. Time Service Center, Chinese Acad. Of Sci.Lintong, Lu Xiaochum; Wu Haitao; Xu Jinsong,“Implementation of convolutional code based on FPGAIn OFDM-UWB system” Industrial Electronics and Application, 2008. ICIEA 2008,Pp 1119-1122.

A few months ago, I asked a similar question (surprisingly, still unanswered?) about the bizarre circuit of DRAM sense amplifier:

There I told how, in the past, I could not understand how a DRAM cell can be refreshed by simply reading. I was able to imagine how this could be done by reading and next writing... but I was not able to imagine how it could be done only by reading...

At the beginning of yesterday's lecture on DRAM, to motivate my students to reveal this brilliant circuit idea themselves, I told them my story. Then, with the help of analogous situations from our daily life (some of them a little fictitious:), we managed to explain it in a simple and spectacular way...

So we already know what the main function of the sense amplifier is in a DRAM - to refresh the contents of the cells. But what is its function in an SRAM where there is no need for refreshment, but only for simple reading? Why do we use there such an odd 2-terminal amplifier?

The conventional amplifier is a 4-terminal (2-port) device - it has an input (port) where to apply the input voltage and an output (port) from where to take the output voltage. Can not we read (and amplify) the contents of the cells with its help? What is the need for such a weird amplifier having only two terminals?

This morning, the answer to this old question suddenly emerged in my mind. I clearly imagined how to present it to my students to understand the need for such a unusual circuit solution in SRAM.

I will spend some time at the beginning of the next lecture on Thursday to unveil this need with the same success as we did in the lecture on DRAM.

I hope this time you will not remain impartial and will support us...

Looking for any studies on the effects of Digital/Electronic Devices on health: including brain occupation when on or off, addictive nature of devices, family relationships including divorce rates, suicides (Belgium now calls this 'opting out of life'), depression, addictive nature of devices, impact on productivity, ROI, blood markers, eye health, incidence of cancer, careers and anything else you could make us aware of I'd not considered. Particularly valuable are studies with over 1000 subjects... but all gladly accepted. Thank you.

I have observed that the picture of a chaotic strange attractor is much more beautiful on an analogue oscilloscope than on a digital oscilloscope.

When the FM radio in my car is replace with a DAB radio

I will observe fall out with no connection just as with my mobile phone.

When you travel by public transport you observe that all people are

looking on their mobile phones. People do not communicate in a natural way anymore. We are becoming robots in a modern world with artificial intelligence.

How can I connect a pico-ammeter to measure the current of several pico ampere? We have keithley source meter 2400. In case of nano ampere current, source meter showing the same but pico ammeter shows micro ampere current when pico ammeter connected in series with sample and source meter.

the critical success factors that contribute to the successful implementation of digital/electronic records still not clear from the literature.  Although many studies have been conducted on the successful implementation of technology, they rarely consider the context of implementation. Given that the digital records management in most countries provides a complex environment for the implementation of technology, the context becomes highly significant.  

There are two version of NAND and NOR cmos gate in dynamic gate design. One is N-logic based and the second one is P-logic based. Which one have to use for low power design requirement?

To build the most elementary storage cell (latch, SRAM cell) we take a non-inverting amplifier (Fig. 1) and simply connect its output to the input (Fig. 2). For some reasons, we implement this configuration by two cascaded inverting stages (Fig. 3):

In its simplest form, this cell is implemented by two transistors (SRAM - Fig. 4) or logic gates (RS latch).

So, naturally, the question arises, "Why do we need two transistors? Can not we realize a cell with only one transistor with positive feedback?" If possible, we would reduce the size of SRAM twice... and it would look like DRAM!

In fact, this issue comes down to the more general question, "Can we apply positive feedback to a single transistor?"... and even to the more primary question, "Can we make a non-inverting amplifier with a single transistor?"

It is interesting that the answer to the dual question, "Can we apply negative feedback to a single transistor?", is positive. Here are some examples:

Then, once we can apply negative feedback to a single transistor, why can not we apply positive feedback?

After two days, I will have a lecture about SRAM (on the subject of Digital and Microprocessor Devices). At the beginning of the lecture, I have to uncover the basic idea of the elementary SRAM cell by making a connection with the previous lecture on latches (flip-flops). Fortunately, I remembered that, three years ago, I asked such a question in the RG forum...

https://www.researchgate.net/post/How_do_we_present_in_an_attractive_way_the_basic_idea_behind_the_most_elementary_memory_cell?

... and decided to see what was going on there...

Then I revealed this idea with great care, enthusiasm and inspiration... and I was very much helped by the exact professionally written comments of Prof. Abdelhalim Zekry. The topic was (and still is) very relevant because this memory element is the basis of modern computers... so I was expecting now to see a lot of registered visitors and comments... which I could show to my students to motivate them...

But what was my surprise when I saw a zero interest in all these three years - no more visits, no followers... no comments! Even Google had not indexed this page... and maybe that was one of the reasons for the lack of interest...

So I decided to renew the topic by expanding it with even more aspects. For example, once cells are claimed to be RS latches, where are then their (total four) inputs and outputs? How so here they are reduced to two? Does not this cause any problems? What are these terminals - inputs, outputs or both?

To enhance students' interest, I intend to make a "shocking" experiment with the elementary cell built of two bipolar transistors (see the attached photo and movie). I will try to "burn" the turned-on transistor by "brutally" connecting the +V_CC rail to its collector. If it does not want to "burn", I will break the feedback (for example, by removing the black wire)... and will repeat the experiment. Interesting, will I succeed?

I have a modulator that through an inductive link, I send my ASK modulated data to the secondary coil and on the secondary part, with some circuit I detect my data, now I want to compare two transmitted data and received data together and calculate bit error rate, as a transmitted data I put an LFSR circuit in the transmitter circuit and use PBRS5 (a pattern of random data producer) .I think that I need some digital electronics information that determine to me how to get data and compare it to the transmitted data. I used serial port for example RS232 to get data. but because of start and stop bit of serial port it was not true(because my random data is not in serial format, it is millions bits of random). so what port should I use and how calculate the bit error rate. I want a true and simple method to calculate this parameter practically.

In 8085 microprocessor, we have conditional jump instructions. If condition is not met, it requires 2 machines cycles to execute the instruction. One machine cycle is for opcode fetch and why do we require another machine cycle?

Hello,

I implemented a fully-differential RF down-conversion mixer on-chip. I have differential RF input signals, differential LO input signals, and differential IF output signals. So I have 6 PADs and I didn’t implement balun circuit to convert single-ended to differential due to area limitation.

My questions are:

* What should I suppose to do to measure such a design?

* Is there any method for measuring differential signals?

 * What kind of equipment should I use?

OR

* Should I implement on PCB balun circuit?

Note: We just have a 4 channels vector network analyzer.

Thanks in advance and I really appreciate your help.

Best Regards,

Hello everyone,

I would like to know how select the value of the delay time between the complementary pulses during the pwm control of an inverter in order to be safe and not to short-circuit the power supply of the single-phase  inverter. Here is the datasheet of the mosfet i chose for the inverter. Moreover, I use the dspic30f4011 for the pwm control (25kHz pwm frequency). Here is the code I use:

#include <stdio.h>

#include <stdlib.h>

#include "p30f4011.h"

// Config

_FOSC(CSW_FSCM_OFF & FRC_PLL16);

_FWDT(WDT_OFF);

_FBORPOR(MCLR_EN & PWRT_OFF);

_FGS(CODE_PROT_OFF);

#define FCY 29480000 // clock's freq

#define FPWM 25000 // switching freq

void main(void) {

PWMCON1=0; //Clear PWMCON registers

PWMCON2=0;

OVDCON =0; //Temporarily disable PWM outputs

PTPER =0x024D; // PTPER=589 // Frequency - approx.25KHz

DTCON1=0000000000000001; //Deadtime 

PTCON = 0x8002; //PWM time base is ON and in paraller PWM

//time base operates in a continuous up/down counting mode

PWMCON1=0x0033; //Enable PWM output pins and enable complementary mode

PWMCON2=0x0004; //Updates to the active PDC registers are immediate

PTMR = 0x0000;

OVDCON = 0x0F00; //Output on PWM 1L-1H-2L-2H pin is controlled by

//the PWM generator

PDC1 = 0x024D;

while(1){

}// infinite Loop

}

Thanks in advance!

If no, what is the difference between capacitance type transmitter and intrinsically safety type transmitter?

I'm equipping a home analog/digital electronic and telecommunication laboratory.

I listed some basic components/parts and tools & devices but i'm looking for a semi complete list of elements and tools/devices needed for such a laboratory.

can anyone suggest me a list of components/parts and tools/devices i need to supply for my lab?

I have a transistor level schematic of 4x2 encoder and i have applied rectangular pulses at all the 4 inputs. Now how to find the delay of both the outputs with respect to four inputs i have applied. There would be 16 input combinations and 16x16=256 possible input transitions. So logically i should apply all the 256 input transitions and should find Tplh and Tphl of both the outputs and worst case Tplh or Tphl among all cases should be the delay of the circuit. But i cant apply all 256 transitions just by using rectangular pulses and i dont have any other source. Please tell if i am wrong or not and tell a general way to find delay of the circuit?

What are the applications of "Active filter tuned oscillators" ?

What are its advantages over other oscillator circuits?

Can we call other oscillators "amplifier tuned oscillators" ?

I'm looking for the simplest way to rectify and collect electrical energy from an electromagnetic vibrational energy harvester in two different cases:

1) for immediate utilization (a supercapacitor..?)

2) for further utilization   (a battery..?)

I'm assuming the harvester to produce way more power than that requested from the load, so I don't need great efficiency, I need the simplest, valid solution that is actually usable to supply a certain DC load replacing its primary battery as a power supply.

I've studied a lot of cases and solutions that vary from a simple full wave rectifier + capacitor to very complex power management circuits, but this field is huge for an inexperienced person like me.

So my question is (assuming I DON'T need great efficiency and therefore a taylor made solution):

should I realize the circuitry on my own? If yes, is there anyone that did it before and could tell me where to get an example of a practical realization or some kind of guide?  

Is it better instead to get some off-the-shelf circuitry?

Thanks in advance

J.B.

I want to know how I can make a circuit if I have input 0-6v an analogue to digital conversion with maximum quantization error 0f 0.1%

In Xpower 7.1i, when I calculated power of a 2-input AND gate, it gave me the total power as 120mW. For a 32bit carry skip adder, it is 124mW, which is totally wrong in my opinion as a 32 bit adder will have many transistors when compared to AND gate. What might be the problem in this. Can anyone, suggest me the correct way of calculating power in Xpower from Xilinx ISE 7.1i

Hi there

I am trying to connect a resistive ladder network to an 16X1 MUX in Cadence UMC-180nm CMOS process. My MUX is basically made of a transmission gate type. I am unable to obtain the exact voltages at output of the MUX after voltage division from the ladder.

The MUX voltage would be then connected to the input of the comparator. I am looking for exact voltages as obtained in the resistive ladder network

I suppose the impedance matching could be one of the basic reason

In cochlear implant products, Class D power amplifier is a really good option to use, I think class E power amplifier can be used too, but I am not sure that in cochlear implant products which of these amplifiers is used.

I try to switch the pin of a quartz crystal resonator XTAL1 and XTAL2 between an oscillator driver circuit and a scalar network analyzer circuit

The quartz crystal oscillator circuit is a Pierce oscillator based on the driver sn74lvc1gx04 http://www.ti.com/lit/ds/symlink/sn74lvc1gx04.pdf

The circuit design is the same reported in the datasheet and in the fihure attached (pierce oscillator)

The scalar network analyzer is the one developed and shared by Brett Killion on hackaday, network analyzer on an arduino shield which covers from 0-72MHz

The schematics file of the network in attach (ArduinoSpecAn)

I'd like to switch the quartz crystal pin between the Pierce oscillator circuit and scalar network analyzer one after the other. I've tried to use CD74HCT4053B High-Speed CMOS Logic Analog Multiplexers and Demultiplexers for switching the quartz crystal pin between the two electronic circuits. Each control of the mux select one of a pair of channel which is connected in a singlepole, double-throw configuration.

The pin configuration I have used is:

Q1 BN pin 15

Q2 CN pin 4

XTAL1 B0 pin 2

XTAL2 C0 pin 5

SMAJ2 B1 pin 1

SMAJ1 C1 pin 3

the switch controls are

oscillator > S0=S1=S2= LOW

network analyzer > S0=S1=S2= HIGH

Using this configuration the network analyzer still works but the Pierce oscillator does not work, that is the oscillator is not able to drive the quartz crystal in stable oscillation. I do not understand why it does not work, maybe I have used a wrong configuration or my idea is not so straightforward to implement.

thank you in advance for suggestions

IIL=Integrated injection logic

Hello my working is on Atlys Board (Spartan 6 ) i want to generate 400 MHz clock , How i can do it ?

The SIMON simulator cannot calculate delay of a Single Electron Transistor (SET) based circuits? How can I do that?

Master slave flip flop is used to eliminate race around condition. So where do we use this configuration.

I am trying to Implement the design to detect the pulse and according to that measure the frequency of that signal. But I am just in learning phase of VHDL coding, So I am having trouble in this. Any answers related to the topic are Welcomed. Thank you.

I have an analog electrical circuit that generates many frequencies in a weak field, but its signals are unique when they are observed.  I do not mind sampling the 'sum' of those frequencies, nor each separate frequency that it generates.  

This is easy, but it gets very difficult when there are thousands of them.  These boards are NOT fed by a common clock cycle.

How would I isolate just one of them, and read any signals unique to that board?  I cannot touch them, or hook anything up to them.

I am looking for concepts only.

What is the role of EDA tools in signal Integrity?

Please reply with  some technical Data and personal experience if you have.

Thanks.

Hello Every one,

This might b a silly question but i am bit confused about it.

I have the following scenario:

I have adc outputs stored in variables a, b, c, d.

I want to pass these inputs through a filter made in a function in C.

My question is: how i can pass these 4 parameters through a single filter function and get there result.

Looking forward for your reply!

Regards

Awais

Hello Everyone,

I am doing the Aging Analysis of the circuit using the relxpert tool of cadence. i am using the free version if the UMC/TSMC provided by them for academic use. For aging analysis we require a reliabilty file which is not included in free version. Anyone here have worked on this topic. Please suggest how to write that file for againg analysis.

my gate driving circuit of IGBT needs 5V volt where as my FPGA board can supply max of 3.3V .So i need to amplify the signal.

If I am using HCPL 3101 with 5V supply then  I can amplify but my signal is getting distorted.so please help me to know is there any other means, I can do so.

thank you 

I am in a situation where all the possible 22 digit binary number are required. Also, the number must be sorted from smallest to largest.

Kindly, suggest me the fast and the efficient way to get this all the binary numbers.

I mean to get the list of all the binary strings between

00 0000 0000 0000 0000 0000 

to

11 1111 1111 1111 1111 1111 

Thanking in advance..

I can't understand for a 64 QAM it will take 6 bit input and produce ! and Q values that will need 4 bits for representation(for + and - 1,3,5,7)...

How will we then perform IFFT on I and Q to get a the data to be transmitted by the OFDM transmitter...

Can anyone help me to find the method for identification of IR drop in a electrochemical capacitor using charge discharge profile?

Is there any standard protocol to determine IR drop?

Please provide related literature if any?

Thank you.

Hello! I am simulating cmos circuits in Tanner (T-Spice) by importing to it, PSpice Netlists While in PSpice everything is successfully simulated, in Tanner I get a fatal error.

The line in which the error is referring to is the following:

.FUNC ROUND(x) { x-IF(cos(PI*x)>0,arcsin(sin(PI*x))/PI,-arcsin(sin(PI*x))/PI) }

And the error that it generates is:

Fatal Error : syntax error, unexpected unary function call, expecting ) (right paren) or device or node name ["ROUND(x)= (x)-IF(cos(PI*x)>0,(arcsin(sin(PI*x))/(PI)),(-arcsin(sin(PI*x))/PI)) " at column 42]

Does anyone know how can I resolve this? This is not a parenthesis I am missing. It is more than that. It has something to do with how ROUND(X) is perceived by Tanner, but I don't have a clue what is it... Any ideas?

I am using the ADS for my simulation but I find it hard to choose for the appropriate active device to be used in 90nm CMOS process. Please help.

Effects of acceleration on RAM and ROM.

What are the various applications of digital electronics, embedded systems and wireless sensor networks in Healthcare?

What method can I use for accurate measurement of dielectric constant of non-metallic materials? How can I put this together with a proximity sensor?

Hello Every One,

I am making a readout circuit for sensor data measurement. I am using a quarter bridge with AC excitation.

My line are approx 2m long which results some capacitance in the line that has to be compensated. This is causing offset into my signals.

How i can compensate this?

Looking forward for your suggestions.

Regards

Awais

Hello everybody

How can I replace the Artificial Neurons (ex.:Stochastic Binary) with a Spiking Neuron (ex.: lif or HH or ... ) in an architecture (ex.: RBM)?

Hello Every body,

I am generating 3Vp-p from DAC inside PSOC 5LP. It looks very nice as long as i do not connect it with bridge (in order to excite the bridge). When i connect it, the voltage drops from 3 to 1/3 of that. I tried to place a voltage follower externally at the output of the DAC but as a result my signal becomes very noise and drops too (but not much).

I am failed to find the reason. Can any body have any idea?

Looking forward for your suggestions.

Regards

Awais

Here you can find a question from Barrie Gilbert, from another thread:

======

As long as we're thinking about its problematical

behavior using the notion of infinite bandwidth,

I must note that the "capacitively-loaded resistor"

does not have to be represented as an infinitely-

distributed line.The attached jpg shows a simpler

feedback network which not surprisingly will also

cause the system to oscillate; and of course, the

actual value of the time-constant(s) doesn't have

any bearing on the maximum permissible gain --

though it necessarily will alter the frequencies of

oscillation.

.

Here's what I found: Using first an AC analysis in

which the scalar gain parameter A is varied over

some range while the magnitude of the response

maxima are noted, the value of A resulting in the  

maximum gain is (about) A = 20.9690082650087

and it is 220 dB  -- equivalent to an impedance of

j1011 ohms, at a frequency of 3.272960203..MHz

'

However, in further simulation experiments, now in

the time domain, in which the circuit was hit with a

2 ps-wide 1 Amp stimulus, the critical value of gain

at which the oscillation magnitude neither grew nor

decayed, was found to be substantially greater, at

(roughly) 21.1719. The oscillation frequency at this

value of A was (about) 3.2847944982971781 MHz.

.

This discrepancy in this critical value of A is larger

than I'd expected. Note that as a matter of general

practice I typically set unusually tight convergence

tolerances. In these experiments chgtol = 1e-22 C,

abstol = 1e-15, vntol = 1 nV and reltol = 1n. I have

qualified the accuracy of this particular simulation

environment over many decades of its use and as

contributor to its capabilities.

.

So... I am puzzled by this anomaly. Can someone

out there "can explain it away"?

Barrie

=======================

Available from: https://www.researchgate.net/post/Can_we_call_it_a_non-inverting_summing_amplifier2 [accessed Jun 15, 2015].

I want to use an electronic odometer to sense speed of my instrument & that gets recorded into a data logger. I want to test that if I cut the power supply of odometer for sometime, but power supply to data logger is continued, would I see a blank/zero reading when data is retrieved from the logger?

Hi all,

I want to run my pi 24/7 and need some sort of battery backup.

When AC power is present the battery needs to be charged and the pi must be able to draw power at the same time.

When AC power is lost the charged batteries should take over to power the pi for as long as possible. A couple of hours would be nice.

I am thinking of a battery or super cap. Which one would be better and how i can connect these for automatic switching?

Looking forward for your suggestions!!!

Regards

Awais

Hello

I have few quires about modelling NBTI Trapping/Detrapping Model Based on Predictive Technology Model (PTMs) firstly for CMOS and then FinFETs for smaller tech. nodes such as 16nm/22nm/32nm/45nm.

Q1: What material PTM (CMOS and FinFETs) models used for Gate-Oxide (e.g. Aluminium oxide Al₂O₃ or Hafnium oxide HfO₂ etc...)?

Q2: Based on above material, what is the typical trap density (i.e. number of traps/cm^2) for 16nm/22nm/32nm/45nm PTMs?

Q3: What is the typical Activation Energy (Ea) value for trapped charge emission? and what is its' range?

Thank you.

Usman

is library set up time is always fixed, as it is store in our .db file as set up time vary from ckt to ckt and should we consider both while analysis?

Let a=1 b=1 c=1 are 3 inputs to exor gate then output  is 1 

(1⊕1)⊕1=0⊕1=>1

If the same inputs applied to exnor gate i am getting same output 

(1 exnor 1 ) exnor 1= 1 exnor 1 = 1

For all 8 possible inputs(3-bit) I am getting same output for exor and exnor gate.

My doubt is

1) Is  it possible to get same output for both exor and exnor gate for odd number of inputs.

2)Is 3- bit exnor gate exists?If exists is it obeys associative law? If obeys is it works similar as exor gate.

I have 9 electrode structures in an adaptive lens device that I am fabricating. All the 9 electrodes are covered by a single sheet of high resistance material (in Mohm range). According to device working principles, I am applying voltage to consecutive electrodes to induce voltage drops across the two electrodes and this translates to phase profile change. My question is when I apply voltage to say electrodes 1 and 2 and since the other electrodes (3 to 9) are floating, would there be a voltage drop across the other electrodes as well? On a side note, I separate low resistance electrodes which is common to all the 9 electrodes is grounded. 

We know in CMOS technology a 0 (LOW) is usually represented with 0V to 1/3 V_dd and 1(HiGH) is represented with 2/3 V_dd to V_dd where V_dd is the supply voltage. That means binary bits 0 and 1 has different voltage level. Now, if we want to transmit binary digits over transmission media (wired) using serial transmission then what are the possible effects of these different voltage level on power dissipation. For example, if we want to transmit "1111", "0000", "1010", "1000" then which sequence will consume more power and why? Or if they consume equal power then why the voltage level has no effect on the power consumption?

I have a cantilever steel beam of 1m length. I want to determine the strain near fixation due to the bending moment of a dead weight on the tip of the beam. 

I plan to place 3 strain gauges near fixation and close to each other on the same line level.

I have some doubts about managing the data. Shall I take the average reading and consider it representative of the strain on the beam? 

I believe that each strain gauge measures the strain in the zone it is placed on.

Any ideas?

I'm working on simulated based test pattern generators. and in MATLAB I have written code for ATPG which generates tests based on PSO optimization algorithm. I have written codes for fault simulation too but it does not work very well on very large sized circuits (in gate level). So I'm looking for a fault simulator which can be linked with MATLAB?