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Questions related to Digital Electronics
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Other than LATEX, is there any tool/software to write a technical book where we can add figures and write equations
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Best tools you may try
1. Microsoft word
2. LATEX
3. Scrivener
4. Freedom
5. Google docs (online)
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At schematic level design i need to add bitline capacitances in HSPICE Simulation. preferred model card is PTM.
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The bit line capacitance can be first estimated by making the lay out of memory cell array. It is determined by how many cells can be connected to this line which conveys the memory cell signal to the sense amplifier. The length of this line must be limited such that its charging must be sufficient to read the logic values of the memory by the sense amplifier without destructing them.
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RRAM device has metal/insulator/metal structure, in which insulating layer acts as an active switching layer. I am looking for any correlation between the crystllite size of the active switching layer's nanoparticles with resistive switching mechanism. Does the size of Nanoparticles control the switching mechanism?
Please share some relevant articles.
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I think the construction of such devices is metal amorphous semicondcutor metal
The amorphous material acts as insulator as its conductivity is very small. When it is it stressed by an applied voltage the current will not be distributed homogenously among the divide but the current finds the easiest path and it will be concentrated there. Such filamentation leads excessive heating of the material and melting where the resistance of the filament will be minimum and the device switches to the conduction state. when the current is reduced the material will be converted into polycrystalline material where its resistance will be much less than the amorphous sate. So, it is the heating effect which converts the material from the amorphous state of high resistivity to the polycrystalline state with low resistivity. This resistive switching is known in the chalcogenide glasses. Please see the paper in the link:
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When I teach bipolar junction transistor (BJT) in the classroom, I emphasize "Cut-off", "Saturation" and "Forward Active Mode" as the 3 operation modes of BJT useful in digital and/or analog applications.
Finally, I mention the 4th mode, namely "Reverse Active Mode", and reveal its properties to emphasize that a BJT is actually not symmetrical, i.e. emitter and collector cannot be interchanged in hope of a similar performance as in Forward Active Mode.
I also add that, although it is usually regarded as useless, I know of one specific application of Reverse Active Mode, namely TTL logic ICs (which have been manufactured/sold in > billions parts).
As many engineers familiar with digital electronics would know, input transistor(s) of a typical TTL logic gate (e.g. TTL NAND) operate in Reverse Active Mode for some input logic combinations.
I would be glad to learn other applications which benefit from Reverse Active Mode of BJT.
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Dear Ali Zeki sir, I read it somewhere that this configuration was used in chopper amplifiers earlier because of lower obtainable Vce,sat .
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RRAM device consists M-I-M (Metal - Insulator - Metal) structure and in most of the RRAM device insulating layer plays important role in resistive switching between HRS (High Resistance state) and LRS (Low Resistance State).
Thanks
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Hope you are well.
There comparison criteria between the different oxides are:
The ratio of the Ion/Ioff. As this ratio increases the device is better.
The value of the on current must be small for smaller power consumption.
The speed of transition from the on off to on state and vice versa.
The stability of device among the cycling among the sates.
The turn on voltage voltage called also set voltage must be small to reduce the switching power of the memory.
Ease of manufacturing.
please see the paper in the link:
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Can someone help me to solve this task below.
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What i can’t understundom you Kenechukwu Emmanuel Umeh
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Hi, a friend wants to publish an article related to the mobile robot navigation slam algorithm. Could someone please suggest a few journals with low impact factor?
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Hello Folks
I am a recent graduate and started my career in the Power Electronics field. It's really great field and I am lucky to get an opportunity to learn PCB design, control of power supply, reliability analysis. My study background more related to power engineering and I want to be an expert in Analog Electronics, Digital Electronics, and Embedded control systems. Can you please anyone guide me for each field (Analog, Digital Electronics, Embedded system) what resources I should use? It would be really great help
Thanks
Avi
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Hi Avi,
The best book I had during my university years was this one:
It covers almost every hardware topic from low noise analogue to digital and power electronics. It even touches on embedded software but that part might be a bit dated now. This will give you a really good overview of many topics.
The best book I found for embedded software is this one:
Chapter 13 takes you from the simplest of round-robin programs up to a real time scheduler in a few simple steps. Schedulers are the basis for most operating systems and they are essential if you want to do any real-time control of anything.
When you get around to designing PCBs then ignore anything you might read in data sheets and application notes. Look at any book written by Ralph Morrison, especially this one:
Despite the name it's an invaluable source of information on how to route a PCB to get your design to pass an EMC test. High power / high frequency switching circuit (like power electronics) need careful attention to layout and Ralph's theories on PCB design really work but are often contrary to other books on the subject.
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This project is related to transient states.
I want to study the behaviour of a circuit (like a current source) by suddenly increasing the resistance from one value (5 ohms) to another (10 ohms).
At first, I used Brick resistance, which I could not achieve to my goal.
Now I use Carbon resistance which has not worked.
Which resistance are used for high frequencies (100ns; 10 Mhz)?
If I use carbon resistors, is there a proposed circuit that I can increase their frequency?
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Dear Asadi,
Now I think I got what do you want to achieve.
You want to measure the TC of the solar panel or any PV array.
You defined the TC = FFT(I)/FFT(V)
So, you want to get the admittance spectroscopy of the twp port network under certain load and illumination condition.
It is clear to me that you do not yet developed such admittance spectroscopy y(f)
So, as I was a pioneer for the admittance spectroscopy of the solar cells i want to stress some facts:
y(f) depends on the operating point of the array. As the operating voltage increases the admittance will be smaller and vice verse. So, the admittance curve is not the same at all operating conditions of the solar panel.
As the panel is nonlinear such that I versus V is not linear, then one has to speak about small signal admittance.
Then one can conclude in order to use this method in diagnosing the panel, one has to keep constant the operating conditions of the panel such as the load and or the terminal voltage and the illumination intensity.
Now we come to the important question how we measure y(f)?
We apply a small signal ac voltage on the panel and measure the the drawn AC current in magnitude and phase.
The ac voltage source is coupled to the loaded and illuminated solar panel by a coupling capacitor. The ac current is sensed by either a sense resistance or by a hall probe. The use of sensing resistance is the most common method.
I made such measurements for the small signal characterization of large area solar cells. I developed a method to measure the ac admittance.
Really you can use them again for diagnosis of solar panels.
I would like that you follow the paper in the link:
You can use the measuring method brought in the paper or use a more advanced method for admittance measurement by following the paper:
Best wishes
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For a OFDM signal, after DAC with 12.5Gsa/s sampling rate, what is the bandwith?  How to calculate?
If the OFDM signal with Hermitian symmetry, what is the bandwith? The Hermitian symmetry will reduce the bandwith?
For a OFDM signal with DAC sampling rate of 12.5Gsa/s, after ADC with 25Gsa/s, what is the bandwith? After down converter, what is the bandwith?
I'm very  confused by the  bandwith calcluation of the OFDM signal? How to calcluate the bandwith?
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how to calculate minimum and maximum throughput in OFDM scheme?
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Forward Error Correction (FEC) schemes square measure a necessary a part of wireless communication systems. The number of symbols inside the availability encoded message is enlarged in an passing controlled manner thus on facilitate a pair of basic demands at the receiver one is Error detection and alternative is Error correction. In telecommunication and data theory, forward error correction (FEC) (also referred to as channel coding]) may be a system of error management for knowledge transmission, whereby the sender adds consistently generated redundant knowledge to its messages, additionally referred to as associate error-correcting code (ECC). In digital electronic systems, data is painted in binary format (1's and 0's).When binary data is passed from one purpose to a different, there's continually some likelihood that a slip-up are often made; a one understood as a zero or a 0 taken to be a 1. This can be caused by media defects, electronic noise, component failures, poor connections, deterioration due to age, and other factors. When a bit is mistakenly interpreted, a bit error has occurred. Error correction is the process of detecting bit errors and correcting them and can be done in software or hardware. For high data rates, error correction must be done in special-purpose hardware because software is too slow. A group of bits in a computer has conventionally been referred to as a "word.” Each bit can be thought of as one of two "letters,” 0 or 1. Error correcting systems add extra or "redundant" letters to computer words. The extra letters (bits) add a certain structure to each word. If that structure is altered by errors, the changes can be detected and corrected.
Papers:
Rolf Johannesson and Kamil Sh. Zigangirov. Fundamentals of Convolutional Coding. IEEE Press, 1998.
Zou Decai Nat. Time Service Center, Chinese Acad. Of Sci.Lintong, Lu Xiaochum; Wu Haitao; Xu Jinsong,“Implementation of convolutional code based on FPGAIn OFDM-UWB system” Industrial Electronics and Application, 2008. ICIEA 2008,Pp 1119-1122.
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The convolutional encoder does not present any challenge at all. The complexity with convolutional codes is the decoder. The complexity of the encoder is insignificant.
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I dedicate this question to my students from Faculty of Computer Systems and Technologies of TU Sofia (groups 44, 45, 46 and 47)...
A few months ago, I asked a similar question (surprisingly, still unanswered?) about the bizarre circuit of DRAM sense amplifier:
There I told how, in the past, I could not understand how a DRAM cell can be refreshed by simply reading. I was able to imagine how this could be done by reading and next writing... but I was not able to imagine how it could be done only by reading...
At the beginning of yesterday's lecture on DRAM, to motivate my students to reveal this brilliant circuit idea themselves, I told them my story. Then, with the help of analogous situations from our daily life (some of them a little fictitious:), we managed to explain it in a simple and spectacular way...
So we already know what the main function of the sense amplifier is in a DRAM - to refresh the contents of the cells. But what is its function in an SRAM where there is no need for refreshment, but only for simple reading? Why do we use there such an odd 2-terminal amplifier?
The conventional amplifier is a 4-terminal (2-port) device - it has an input (port) where to apply the input voltage and an output (port) from where to take the output voltage. Can not we read (and amplify) the contents of the cells with its help? What is the need for such a weird amplifier having only two terminals?
This morning, the answer to this old question suddenly emerged in my mind. I clearly imagined how to present it to my students to understand the need for such a unusual circuit solution in SRAM.
I will spend some time at the beginning of the next lecture on Thursday to unveil this need with the same success as we did in the lecture on DRAM.
I hope this time you will not remain impartial and will support us...
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Hi Dr. Cyril Mechkov,
I have a simpler answer.
Bit cells of SRAM are made very small to reduce the cost. Thus, turning bit-lines to logic 0 or 1 using small cells require much longer time.
To solve these issues both bit-lines are precharged to Vdd (logic 1). A single cell is electrically connected to bit-lines for a small time to make a small difference in voltages. Later, the sense amplifier senses that difference and convert that small difference to logic 1 and logic 0.
For more details please read my paper-
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Looking for any studies on the effects of Digital/Electronic Devices on health: including brain occupation when on or off, addictive nature of devices, family relationships including divorce rates, suicides (Belgium now calls this 'opting out of life'), depression, addictive nature of devices, impact on productivity, ROI, blood markers, eye health, incidence of cancer, careers and anything else you could make us aware of I'd not considered. Particularly valuable are studies with over 1000 subjects... but all gladly accepted. Thank you.
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Thank you for jour quic anser ans for the projection informations.
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I have observed that the picture of a chaotic strange attractor is much more beautiful on an analogue oscilloscope than on a digital oscilloscope.
When the FM radio in my car is replace with a DAB radio
I will observe fall out with no connection just as with my mobile phone.
When you travel by public transport you observe that all people are
looking on their mobile phones. People do not communicate in a natural way anymore. We are becoming robots in a modern world with artificial intelligence.
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It's probably not a good idea to use the word "always"...
There exist some aspects in the question:
* the digital era is demanded by the market - it's about the repeatability when manufacturing gazillion of devices which have to be produced at no time - more devices more money;
* in some areas the digitalization is impossible as the nature of some phenomena is purely analog - (electromagnetic) waves, temperature, pressure etc. - these would be firstly processed by the old fashion analog electronics and just then processed and stored digitally;
* even some analog "devices" can be thought of being digital in some sense. For example the human eye - why do we see images flickering if they update under about 50Hz or so; seeing a bicycle wheel rotating at the opposite direction from above some speed is a direct consequence of not following the Nyquist–Shannon–Kotelnikov sampling theorem.
* becoming a zombie is more social related issue but that's the reality... I think that at first the artificial intelligence will become ubiquitous (again because of the market). Then probably the next era will advertise "machines without AI" - just like today we search for a fruit juice without preservatives and coloring agents... :)
I think both worlds (analog and digital) will always complement each other.
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How can I connect a pico-ammeter to measure the current of several pico ampere? We have keithley source meter 2400. In case of nano ampere current, source meter showing the same but pico ammeter shows micro ampere current when pico ammeter connected in series with sample and source meter.
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I'm glad I could help you)
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the critical success factors that contribute to the successful implementation of digital/electronic records still not clear from the literature.  Although many studies have been conducted on the successful implementation of technology, they rarely consider the context of implementation. Given that the digital records management in most countries provides a complex environment for the implementation of technology, the context becomes highly significant.  
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There are two version of NAND and NOR cmos gate in dynamic gate design. One is N-logic based and the second one is P-logic based. Which one have to use for low power design requirement?
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N- logic blocks are normally used to implement dynamic CMOS logic. Only in case of single phase clock one has to use alternately P-logic blocks and N-logic blocks alternately.
The NMos logic is superior than the PMOS logic as the NMOS transistor is better than the PMOS transistor. The major advantage comes from the electron mobility is much greater than the hole mobility. un= 2.5 up. Therefore the nNOS transistors are much faster than the PMOS transistor which is very required for performing the logic operation. In addition there are two types of NMOS transistors: the enhancement and depletion where for the PMOS transistor there is only the enhancement type.
In fact the MOS transistor logic has evolved from the PMOS, then the NMOS, and finally the CMOS. With the introduction of the CMOS, one could reduce the static power consumption especially on the pull down state. That is both the pull up and pull down transistors are acting as switches.
For more precise compaeison between the different types of CMOS logic gates please refer the ppt in the link: vlsi-eda.cm.nctu.edu.tw/course/.../Lec%2012%20Dynamic%20Logic%20Circuits.ppt
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To build the most elementary storage cell (latch, SRAM cell) we take a non-inverting amplifier (Fig. 1) and simply connect its output to the input (Fig. 2). For some reasons, we implement this configuration by two cascaded inverting stages (Fig. 3):
In its simplest form, this cell is implemented by two transistors (SRAM - Fig. 4) or logic gates (RS latch).
So, naturally, the question arises, "Why do we need two transistors? Can not we realize a cell with only one transistor with positive feedback?" If possible, we would reduce the size of SRAM twice... and it would look like DRAM!
In fact, this issue comes down to the more general question, "Can we apply positive feedback to a single transistor?"... and even to the more primary question, "Can we make a non-inverting amplifier with a single transistor?"
It is interesting that the answer to the dual question, "Can we apply negative feedback to a single transistor?", is positive. Here are some examples:
  • "Active diode" - a transistor whose base is connected to the collector (parallel negative feedback)
  • "Current-stabilizing diode" - a FET with a current-sensing resistor in the source and gate connected to the other end of the resistor (serial negative feedback)
Then, once we can apply negative feedback to a single transistor, why can not we apply positive feedback?
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Dear Cyril,
Assume you have such amplifier with one transistor say NMOSFET whose drain is connected to VDD through a pull up resistor and also its drain is connected to its source by a feed element say a zener diode with VZ smaller than VDD. The gate is kept at VDD for controlling the transistor.
The input is through the source.
If we want to write logic one we apply VDD to the source, the transistor VGS=0 and the transistor gets off. and the the drain becomes at VDD , the one is written at the drain of the transistor. If we remove the bit line source and make it open nothing will happen since the transistor is already off.
So, the logic one could be written and sustained.
Now we come to the logic zero we want to wright logic zero by applying zero voltage on the source, since VGS= VDD, then the transistor gets on and the drain potential gets low and the zero is written at the drain node.
Now let us test if the circuit will keep the drain mode at the low state when we open the source as we did with logic one operation. That is we make IS=0, and also ID will be zero and the drain pulls up to VDD. This means that the circuit can no sustain the on state of the transistor with partition procedural.
And this what i said in my previous post that the off sate is one natural state in a single transistor circuit while the one state must be forced or imposed as the transistor is a fully controlled device.
However there is a mode of operation where one can make the default of the circuit is the zero by operating write input source at only two states the zero and VDD while making the gate high when we want to write or read the bits other wise its gate is low.
Let us verify the operation of this mode:
write one , VS=VDD, VG=VDD, then VGS=0 and the transistors is off and its drain will be high= VDD,
Then let VS=VG=0, VGS=0 and the transistor remains off keeping VD= VDD,
write zero,
VG=VDD, VS=0, VGS= VDD AND THE TRANSISTOR GETS ON AND VD=low
and so a zero is written.
Let us make VG= 0 and VS=0, THE TRANSISTOR WILL GET OFF AND THE ZERO IS NO LONGER SUSTAINED.
The only possibility to keep the transistor on is to keep the gate voltage high and the source voltage zero so long the content of the circuit is zero at the drain.
So, in conclusion accordion to these analysis, the single transistor cell alone is not working. Even here the circuit here has two elements not only one. Normally the area of the resistor in the chip is much larger than that of the transistor and still it is not working.
I think the best and natural information storage element is the capacitor!!!!!!!!!.
In case of static ram one has only to keep the charge constant during the bit storage time. The work in this direction will bring more benefits.
Best wishes
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After two days, I will have a lecture about SRAM (on the subject of Digital and Microprocessor Devices). At the beginning of the lecture, I have to uncover the basic idea of the elementary SRAM cell by making a connection with the previous lecture on latches (flip-flops). Fortunately, I remembered that, three years ago, I asked such a question in the RG forum...
... and decided to see what was going on there...
Then I revealed this idea with great care, enthusiasm and inspiration... and I was very much helped by the exact professionally written comments of Prof. Abdelhalim Zekry. The topic was (and still is) very relevant because this memory element is the basis of modern computers... so I was expecting now to see a lot of registered visitors and comments... which I could show to my students to motivate them...
But what was my surprise when I saw a zero interest in all these three years - no more visits, no followers... no comments! Even Google had not indexed this page... and maybe that was one of the reasons for the lack of interest...
So I decided to renew the topic by expanding it with even more aspects. For example, once cells are claimed to be RS latches, where are then their (total four) inputs and outputs? How so here they are reduced to two? Does not this cause any problems? What are these terminals - inputs, outputs or both?
To enhance students' interest, I intend to make a "shocking" experiment with the elementary cell built of two bipolar transistors (see the attached photo and movie). I will try to "burn" the turned-on transistor by "brutally" connecting the +VCC rail to its collector. If it does not want to "burn", I will break the feedback (for example, by removing the black wire)... and will repeat the experiment. Interesting, will I succeed?
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Dear Glen,
Irrespective of its physical construction, a binary memory cell must possess two stable states such that one can assign logic 1 to one of the states and logic zero to the other state. For example in the SRAM the logic zero is keyed in low voltage levels and the logic one is mapped on the High voltage levels. In the magnetic memory the logic one is mapped on an oriented magnetic field of the domains while logic zero is mapped on nonoriented magnetic domains in the magnetic material which means zero resultant magnetization. Another alternative is the case brought by Cyril of magnetic core memory where logic one is mapped on +M magnetization state and logic zero is mapped on -M magnetization state.
In case of DRAM the zero is mapped on zero charge stored on the capacitor of the DRAM while the one state is mapped on the full charge at the capacitor with normally a voltage of VDD.
In case of the ferroelectric memory the ferroelectric capacitor retain specific polarization charge in case of logic 1 and zero charge in case of logic zero.
From the principle point of view any bistatble device can be used as binary memory cell. The bit values can be written by changing the states of the bistable device. Also the logic values can be read by accessing the cell content. Also the cells mus be addressed by the process of selection.
It is required that the energy consumption by the memory must be as small as possible. The energy may be consumed in retaining the data written in the memory, reading and writing the contents of the memory. In addition the memory access time must be as small possible.
The last performance parameter is the size of the memory cell. It must be as small as possible.
These are performance criteria of the memories.
Best wishes
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I have a modulator that through an inductive link, I send my ASK modulated data to the secondary coil and on the secondary part, with some circuit I detect my data, now I want to compare two transmitted data and received data together and calculate bit error rate, as a transmitted data I put an LFSR circuit in the transmitter circuit and use PBRS5 (a pattern of random data producer) .I think that I need some digital electronics information that determine to me how to get data and compare it to the transmitted data. I used serial port for example RS232 to get data. but because of start and stop bit of serial port it was not true(because my random data is not in serial format, it is millions bits of random). so what port should I use and how calculate the bit error rate. I want a true and simple method to calculate this parameter practically.
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Hi,
if I understand your experiment, you want to send the generated data using a serial port. The RS232 mentioned by you has its own protocol. The start and stop bit do not the transmitted data. The workflow of the RS232 port generates these bits themselves and, on the receiving side, the receiver protocol again removes the start and stop bits from the transmitted data.
The problem may be the speed of data generation and RS232 bandwidth (limited speed).
You can compare the input and output data of your experiment with the XOR circuit. If the coincident input and output bits are different, the XOR circuit will generate logic output 1. If you divide the number of logic 1 at the XOR output by the number of tranferred bits, you get the percentage of error tranferred bits.
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Hello,
I implemented a fully-differential RF down-conversion mixer on-chip. I have differential RF input signals, differential LO input signals, and differential IF output signals. So I have 6 PADs and I didn’t implement balun circuit to convert single-ended to differential due to area limitation.
My questions are:
* What should I suppose to do to measure such a design?
* Is there any method for measuring differential signals?
 * What kind of equipment should I use?
OR
* Should I implement on PCB balun circuit?
Note: We just have a 4 channels vector network analyzer.
Thanks in advance and I really appreciate your help.
Best Regards,
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You can measure nonlinearity of the transfer function for each mixer by using one and two harmonic signals. After this expediently compare two destorted signals.
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Hello everyone,
I would like to know how select the value of the delay time between the complementary pulses during the pwm control of an inverter in order to be safe and not to short-circuit the power supply of the single-phase  inverter. Here is the datasheet of the mosfet i chose for the inverter. Moreover, I use the dspic30f4011 for the pwm control (25kHz pwm frequency). Here is the code I use:
#include <stdio.h>
#include <stdlib.h>
#include "p30f4011.h"
// Config
_FOSC(CSW_FSCM_OFF & FRC_PLL16);
_FWDT(WDT_OFF);
_FBORPOR(MCLR_EN & PWRT_OFF);
_FGS(CODE_PROT_OFF);
#define FCY 29480000 // clock's freq
#define FPWM 25000 // switching freq
void main(void) {
PWMCON1=0; //Clear PWMCON registers
PWMCON2=0;
OVDCON =0; //Temporarily disable PWM outputs
PTPER =0x024D; // PTPER=589 // Frequency - approx.25KHz
DTCON1=0000000000000001; //Deadtime 
PTCON = 0x8002; //PWM time base is ON and in paraller PWM
//time base operates in a continuous up/down counting mode
PWMCON1=0x0033; //Enable PWM output pins and enable complementary mode
PWMCON2=0x0004; //Updates to the active PDC registers are immediate
PTMR = 0x0000;
OVDCON = 0x0F00; //Output on PWM 1L-1H-2L-2H pin is controlled by
//the PWM generator
PDC1 = 0x024D;
while(1){
}// infinite Loop
}
Thanks in advance!
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Hello Valentina,
I agree with Rujun Chen: In order to take any properties of your driver etc. into account, you should measure how your circuit behaves.
For a rough estimate: On page 5, the datasheet lists the switching times. According to these, the time from bringing Vgs below 9 V to Id reaching 0.7 A is 44 + 10 = 54 ns (see Fig. 22 to 24). On the other hand, the delay time for switching on is 19 ns; so switching on 54 - 19 = 35 ns after switching off would result in an additional "cross current" pulse of about 10% of your load current.
But: The switching times are typical values; your actual samples might be slower. Your driver outputs might provide less than 2.1 A (Ugs / Rg), so it takes longer to charge / discharge Ciss and Crss. BTW, how do you drive the gates?
So, if a current probe with the necassary bandwidth (>= 40 MHz) isn't  available to you immediately, I would start with a delay time of at least 100 ns. With 25 kHz, the maximum pulse width is 20 us, 100 ns being only 0.5%. Then you could measure the supply current, play carefully with the delay time, and find the point where the supply current begins to increase (and afterwards choose a delay time 10 or 20 ns above that point).
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If no, what is the difference between capacitance type transmitter and intrinsically safety type transmitter?
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Just a quick search on the internet seems to yield some possible solutions. Look at
The first link is to an instrument from the SOR company. I've not used this product, but I've used other products from that company, with good results.
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I'm equipping a home analog/digital electronic and telecommunication laboratory.
I listed some basic components/parts and tools & devices but i'm looking for a semi complete list of elements and tools/devices needed for such a laboratory.
can anyone suggest me a list of components/parts and tools/devices i need to supply for my lab?
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@aparnma , it would be nice if you provide a part number list for each category mentioned.
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I have a transistor level schematic of 4x2 encoder and i have applied rectangular pulses at all the 4 inputs. Now how to find the delay of both the outputs with respect to four inputs i have applied. There would be 16 input combinations and 16x16=256 possible input transitions. So logically i should apply all the 256 input transitions and should find Tplh and Tphl of both the outputs and worst case Tplh or Tphl among all cases should be the delay of the circuit. But i cant apply all 256 transitions just by using rectangular pulses and i dont have any other source. Please tell if i am wrong or not and tell a general way to find delay of the circuit?
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Sorry, thomas but i didn't understand what do you mean by reset. Its a 4x2 priority encoder with a validity bit as one of the outputs.  
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What are the applications of "Active filter tuned oscillators" ?
What are its advantages over other oscillator circuits?
Can we call other oscillators "amplifier tuned oscillators" ?
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The oscillators can be built by a positive feedback amplifier which satisfies the Parkhausen criteria. The oscillating open loop gain AB must be equal or greater than one, which means magnitude AB=1 and the phase= 0, 2 pi,..etc. Whenever this condition is satisfied the circuit will oscillate. It remains that one has to make the circuit oscillate at certain frequency. This is normally accomplished by frequency selective circuit where the above condition is satisfied at certain specific frequency. These circuits are called timing circuits of the oscillators. It is so that the amplifier odf the oscillator is made flat which means that its gain is independent of frequency. Then the feed back network which is called the B network must be frequency selective. This means that it acts as a narrow band pass filter with the center frequency is the most preferred frequency for oscillations. This filter may be passive like an LC tuned circuit, or a phase shift network or a lag lead circuit. An alternative, one can use an active B-network, say acting also as a band pass filter.
The active filters themselves are used preferably at low frequencies where using the LC components will  make the filter bulky and lossy.
So, the active filter tuned oscillators are advantageous at low frequencies and extremely low frequencies.
Best wishes
.
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I'm looking for the simplest way to rectify and collect electrical energy from an electromagnetic vibrational energy harvester in two different cases:
1) for immediate utilization (a supercapacitor..?)
2) for further utilization   (a battery..?)
I'm assuming the harvester to produce way more power than that requested from the load, so I don't need great efficiency, I need the simplest, valid solution that is actually usable to supply a certain DC load replacing its primary battery as a power supply.
I've studied a lot of cases and solutions that vary from a simple full wave rectifier + capacitor to very complex power management circuits, but this field is huge for an inexperienced person like me.
So my question is (assuming I DON'T need great efficiency and therefore a taylor made solution):
should I realize the circuitry on my own? If yes, is there anyone that did it before and could tell me where to get an example of a practical realization or some kind of guide?  
Is it better instead to get some off-the-shelf circuitry?
Thanks in advance
J.B.
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Since you have researched, you are aware of many possibilities so you don't need help that way. I don't think you can get good suggestions without more information as to your system parameters and application.  i.e. details on the energy harvester, what is its output? What is the duty cycle for how long it will be operated or not. What is the load you want to power? What  are its power requirements? How often and how long do you need to power it for.   How long does the energy need to be stored?   What is the physical environment like for the power storage and conditioning? Are there any size/weight limitations? etc., etc.
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I want to know how I can make a circuit if I have input 0-6v an analogue to digital conversion with maximum quantization error 0f 0.1%
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I agree with Henri, in order to convert  a voltage greater than the maximum input of your A/D converter, then you need to divide it by a potential divider. Here you can divide your 10V by 2 which means that you extend the range of your A/D converter by 2. Division by two means to shift your digital number by one digit to left. This is for the net result you get after division by 2. As for circuit you need, you can use two equal resistors which draw negligible current from your circuit.
Best wishes
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In Xpower 7.1i, when I calculated power of a 2-input AND gate, it gave me the total power as 120mW. For a 32bit carry skip adder, it is 124mW, which is totally wrong in my opinion as a 32 bit adder will have many transistors when compared to AND gate. What might be the problem in this. Can anyone, suggest me the correct way of calculating power in Xpower from Xilinx ISE 7.1i
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power consumed in individual circuit cant be calculated in xilinx it always gives power consumed  by whole chip . better to go for full custom design in order to get optimum power consumption result
thanks
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Hi there
I am trying to connect a resistive ladder network to an 16X1 MUX in Cadence UMC-180nm CMOS process. My MUX is basically made of a transmission gate type. I am unable to obtain the exact voltages at output of the MUX after voltage division from the ladder.
The MUX voltage would be then connected to the input of the comparator. I am looking for exact voltages as obtained in the resistive ladder network
I suppose the impedance matching could be one of the basic reason
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Dear Anush,
Welcome,
Since your multiplexer is a transmission gate type, it inserts an effective resistance in the path of the signal to the comparator. If the input impedance of the comparator is relatively low, then the resistive divider network will be upset due to this loading.
There are two solutions;
You have to increase the input impedance of the comparator while decreasing the divider resistances.
or you add abuffer at the input of the comparator or even you can buffer the divider from the multiplexer by buffer amplifier.
Best wishes 
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In cochlear implant products, Class D power amplifier is a really good option to use, I think class E power amplifier can be used too, but I am not sure that in cochlear implant products which of these amplifiers is used.
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 Thank you so much 
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I try to switch the pin of a quartz crystal resonator XTAL1 and XTAL2 between an oscillator driver circuit and a scalar network analyzer circuit
The quartz crystal oscillator circuit is a Pierce oscillator based on the driver sn74lvc1gx04 http://www.ti.com/lit/ds/symlink/sn74lvc1gx04.pdf
The circuit design is the same reported in the datasheet and in the fihure attached (pierce oscillator)
The scalar network analyzer is the one developed and shared by Brett Killion on hackaday, network analyzer on an arduino shield which covers from 0-72MHz
The schematics file of the network in attach (ArduinoSpecAn)
I'd like to switch the quartz crystal pin between the Pierce oscillator circuit and scalar network analyzer one after the other. I've tried to use CD74HCT4053B High-Speed CMOS Logic Analog Multiplexers and Demultiplexers for switching the quartz crystal pin between the two electronic circuits. Each control of the mux select one of a pair of channel which is connected in a singlepole, double-throw configuration.
The pin configuration I have used is:
Q1 BN pin 15
Q2 CN pin 4
XTAL1 B0 pin 2
XTAL2 C0 pin 5
SMAJ2 B1 pin 1
SMAJ1 C1 pin 3
the switch controls are
oscillator > S0=S1=S2= LOW
network analyzer > S0=S1=S2= HIGH
Using this configuration the network analyzer still works but the Pierce oscillator does not work, that is the oscillator is not able to drive the quartz crystal in stable oscillation. I do not understand why it does not work, maybe I have used a wrong configuration or my idea is not so straightforward to implement.
thank you in advance for suggestions
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Dear Marco,
Theoretically speaking this solution is okay. It works with the network analyzer but it does not work with the oscillator. Most probable because of the parasitic on resistance of the analog switch Ron. After the data sheet the analog switch Ron= 45 Ohms. So, you added two  forty five ohm resistors in series with the crystal which may quench the oscillator. If this is true, one can demonstrate this effect by adding two equal resistances tn series with the crystal and observe the operation of the oscillator. If the oscillator could not start proves the diagnosis.
The solution is to use analog switches with very small on resistor. Even you can use relays as analog switches. Relays have metallic contacts and very small on resistors.
On the other side you have to take the on resistance of the analog switches when you make your network analysis for the xtal.
Best wishes 
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IIL=Integrated injection logic
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HI, 
  • DTCL has the problem of current hogging, which can be understood by the following link-
  • whereas, in IIL logic family avoids the current hogging by using current injection which is more clearly explained in the following- 
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Hello my working is on Atlys Board (Spartan 6 ) i want to generate 400 MHz clock , How i can do it ?
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2
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Hi,
A part of my project in Signal Processing is to generate a sine signal with the cordic algorithm in VHDL and put the VHDL Code on a board and test it. Do somebody have an idea for a VHDL code example?
Thanks a lot
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The SIMON simulator cannot calculate delay of a Single Electron Transistor (SET) based circuits? How can I do that?
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Dear Farid And Balaji
Thanks alot for the answer and the files.
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Master slave flip flop is used to eliminate race around condition. So where do we use this configuration.
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The IC's where consists of a lot of stages of digital circuits where timing of data appearing at the input of FF (Flip Flop) and obtaining the output from FF is very much vital. So, master slave flip flop can play a vital role in performing those critical performance of successive stages of digital circuits. "Hold time" and "Set up time" are some of the key parameters to analyze in those aspects.
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In 8085 microprocessor, we have conditional jump instructions. If condition is not met, it requires 2 machines cycles to execute the instruction. One machine cycle is for opcode fetch and why do we require another machine cycle?
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Conditional Jump instruction normally requires 3 machine cycles(10T), if the condition is true. 1st machine cycle is for opcode fetch another 2machine cycles are for memory read.
If the condition is false it requires 2 machine cycles(7T). One machine cycle is for opcode fetch, another one is for memory read.
Refer the link for more details:
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I am trying to Implement the design to detect the pulse and according to that measure the frequency of that signal. But I am just in learning phase of VHDL coding, So I am having trouble in this. Any answers related to the topic are Welcomed. Thank you.
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Aparna Murthy, This is really helpful. Thank you.
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I have an analog electrical circuit that generates many frequencies in a weak field, but its signals are unique when they are observed.  I do not mind sampling the 'sum' of those frequencies, nor each separate frequency that it generates.  
This is easy, but it gets very difficult when there are thousands of them.  These boards are NOT fed by a common clock cycle.
How would I isolate just one of them, and read any signals unique to that board?  I cannot touch them, or hook anything up to them.
I am looking for concepts only.
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At my university, In 1977, I had a project involving gathering small signals from muscle behavior signals in Cerebral Palsy clients. This was a study of myographic signals from partially responsive patients.    
We had radio interference from three radio stations.  The signal was rock-and-roll and extremenly strong as we were directly in the antenna beam path.  This was a second floor lab and we could see the antennas. .  
Our Spectrum Analyzer showed extremely low S/N ratio.
All efforts at simple shielding and groundind failed. 
In 1977, I only had Analog design options, 
( no Digital Signal Processing ). 
Simple Faraday Shielding of the mother-board was not effective. 
Basically, we blocked all unwanted signals, 
and captured only the target signals. 
All this was in Analog Design mode. 
The ultimate method was a multiple approach.
First, we built a 8' x 8' x 8'  Faraday Cage room.  The walls of this shielded "cage" was grounded via #4 AWG copper to a 10' ground rod outside the building. ( Various other electrical "grounds" were far from effective.)
Secondly, the electronic amplifier I designed was based on the  Instrumentation Amplifier  (IA)  approach, with an active ground presented to the IA .   I designed that instrument from scratch, using high performance OpAmps.  Now days, "Analog Devices, Inc."  has some beautiful devices that could speed up the design time greatly.  
(1) our IA circuit had a common mode rejection of > 90 dB, which virtually eliminated the outside noise which was common to all leads entering the equipment.
Since we used eight pick-up leads, we had eight IA devices, attached to the pick-up leads about 1 foot from the sampling point on the patient. 
(2) Each mother-board had a ground plan covering everything, and all grounding was equi-potential to a single point.  
(3) All leads, incoming and outgoing, were threaded through ferrite beads, further blocking the outside noise.
(4) Each was a very tightly built cabinet. 
(5) This equipment was placed inside the Faraday Cage, 
and all leads were kept as short as possible, directly beside the patient. 
Ours solution was not simple, 
but it was very effective in blocking 
the Amplitude Modulated Radio Signal ,
and capturing only the target signal.  
In looking back, it is still evident that
(1) the Faraday Cage 
and
(2) the Instrumentation Amplifier design
would be required to drive
any modern Digital Signal Process computer program.  
Young folks, there is NO magic in the world of research, 
only magical researchers who know how to design. 
Study well, and good luck. 
 
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What is the role of EDA tools in signal Integrity?
Please reply with  some technical Data and personal experience if you have.
Thanks.
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the best one is the one your company bought for you :)
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Hello Every one,
This might b a silly question but i am bit confused about it.
I have the following scenario:
I have adc outputs stored in variables a, b, c, d.
I want to pass these inputs through a filter made in a function in C.
My question is: how i can pass these 4 parameters through a single filter function and get there result.
Looking forward for your reply!
Regards
Awais
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I Awais,
If I understood well your question, I think a good option is to use pointers of structures.
You first declare and initialize (with a calloc for example) a pointer on a structure. And this structure contains all the variables you need in your function, the inputs and the outputs.
In your main program, you attribute the values you want to the parameters that are inside the structure.
Then, the entry of the function is the pointer on the structure. Thus, in the function, you can access all the variables that are defined inside your structure. And also access them out of the function.
I hope it helped!
Julien.
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Hello Everyone,
I am doing the Aging Analysis of the circuit using the relxpert tool of cadence. i am using the free version if the UMC/TSMC provided by them for academic use. For aging analysis we require a reliabilty file which is not included in free version. Anyone here have worked on this topic. Please suggest how to write that file for againg analysis.
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hi
add aging files in the model library instead of  previously existing .scs or .mdl file.
then go to ADEL -> simulation:reliability set up->
set Rel Xpert tool there
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my gate driving circuit of IGBT needs 5V volt where as my FPGA board can supply max of 3.3V .So i need to amplify the signal.
If I am using HCPL 3101 with 5V supply then  I can amplify but my signal is getting distorted.so please help me to know is there any other means, I can do so.
thank you 
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You can also use something like this - it gives you the ability to arbitrarily set logic levels on each side of the translator - slight modification on the above circuit I mentioned.  While op amps can work - its total overkill.  These kinds of transistor solutions are simple and very cost effective.
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I am in a situation where all the possible 22 digit binary number are required. Also, the number must be sorted from smallest to largest.
Kindly, suggest me the fast and the efficient way to get this all the binary numbers.
I mean to get the list of all the binary strings between
00 0000 0000 0000 0000 0000 
to
11 1111 1111 1111 1111 1111 
Thanking in advance..
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Dear Mr. Mahamad Nabab Alam,
Further, you may use Verilog HDL. Also, why not to use 22-bit up-counter?
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I can't understand for a 64 QAM it will take 6 bit input and produce ! and Q values that will need 4 bits for representation(for + and - 1,3,5,7)...
How will we then perform IFFT on I and Q to get a the data to be transmitted by the OFDM transmitter...
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Dear Sir,
I think the part you are referring to is the 'constellation translation'. The points, both on i and q of {7,5,3,1,-1,-3,-5,-7} are the constellation. In i , there are 8 such point, in q also 8, in i and q combined, there are 8*8 = 64. The 6-bit input has also 64 possible values (2**6), and there is a 1 to 1 correspondence (given by the constellation diagram), mapping the 6-input to a point of the 64-point constellation diagram.
The IFFT is done after the constellation mapping. You need ample SNR, however, in any case, more than the 4 bit/i,q of the constellation diagram.
Cheers,
Henri.
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Can anyone help me to find the method for identification of IR drop in a electrochemical capacitor using charge discharge profile?
Is there any standard protocol to determine IR drop?
Please provide related literature if any?
Thank you.
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Dear Santimoy,
Immediately when you stop to charge at constant current (I) and during the discharge process two parameters, you should consider. The drop in voltage (ΔV) due to internal resistance, and drop in voltage due to capacitance.
The IR drop can be calculated from ΔV/current (Ohm's Law), unfortunately at high currents, you can not deduced IR drop by this method. Additionally, the IR drop should increase linearly with the current so that the slope gives you equivalent series resistance.
I hope a links below will be helpful for you.
Yours sincerely,
Mouad
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Hello! I am simulating cmos circuits in Tanner (T-Spice) by importing to it, PSpice Netlists While in PSpice everything is successfully simulated, in Tanner I get a fatal error.
The line in which the error is referring to is the following:
.FUNC ROUND(x) { x-IF(cos(PI*x)>0,arcsin(sin(PI*x))/PI,-arcsin(sin(PI*x))/PI) }
And the error that it generates is:
Fatal Error : syntax error, unexpected unary function call, expecting ) (right paren) or device or node name ["ROUND(x)= (x)-IF(cos(PI*x)>0,(arcsin(sin(PI*x))/(PI)),(-arcsin(sin(PI*x))/PI)) " at column 42]
Does anyone know how can I resolve this? This is not a parenthesis I am missing. It is more than that. It has something to do with how ROUND(X) is perceived by Tanner, but I don't have a clue what is it... Any ideas?
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Try spice Level 8 models , which I pointed to in this post, in this thread of yours.
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I am using the ADS for my simulation but I find it hard to choose for the appropriate active device to be used in 90nm CMOS process. Please help.
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you must have the model library of your technology in ADS
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Effects of acceleration on RAM and ROM.
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Arpit,
I would be surprised if any commercial memory device would fail at these modest accelerations. At approximately one thousand times this level you will start to exceed the physical strength of the packaging material - it will crush under its own weight.
But 90gee? Not a problem.
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What are the various applications of digital electronics, embedded systems and wireless sensor networks in Healthcare?
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Heart monitoring to prevent heart failure or in the case of sport parctice, blood test for Glycemic insufficiency, ....
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What method can I use for accurate measurement of dielectric constant of non-metallic materials? How can I put this together with a proximity sensor?
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Hello David,
I partially agree with Mustafa. You have to use the "Concept of Capacitance" with a known or standard/fixed area of conductor plates/PCB Copper area and then apply the equation as Mustafa has stated. But I shall go a step further - Use this "Sensing Capacitor" in an AC circuit or an Wien-Bridge circuit to generate sine wave. Now, as you change the material inside this "Capacitor" its frequency would change. Now you calibrate your output against the dielectric constant of know materials and this frequency output. Then map the dielectric constant of the unknown material from this curve or through software.
I hope that this would be more useful way for your experiment.
Thanks and best wishes!
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Hello Every One,
I am making a readout circuit for sensor data measurement. I am using a quarter bridge with AC excitation.
My line are approx 2m long which results some capacitance in the line that has to be compensated. This is causing offset into my signals.
How i can compensate this?
Looking forward for your suggestions.
Regards
Awais
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Dear Muhammad,
would you please display a drawing of the circuit?, in order to see the effect of the connecting wires and consequently propose a method for the compensation.
From the conceptual point of view, a capacitive reactance can be compensated by an equal inductive reactance. Which means that one can shunt the wire line with a lumped inductor at the point of compensation. 
May be more methods when you show you circuit.
wish you success
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Hello everybody
How can I replace the Artificial Neurons (ex.:Stochastic Binary) with a Spiking Neuron (ex.: lif or HH or ... ) in an architecture (ex.: RBM)?
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Hi,
some aspects to start with are the following questions:
- what is your desired firing rate? --> set the refractory time (in LIF) to set the maximum firing rate and leakage current/conductances accordingly; many other parameters determine the range of firing rate in spiking neurons (including the connection weights)
For a minimum (base/resting) firing rate, you may need to add some input current / background noise which drives the cells constantly / randomly.
- does your model require some specific temporal firing patterns (if so, you may want to have a look at "Which Model to Use for Cortical Spiking Neurons?" by Izhikevich 2004
- how many neurons do you need and which simulator do you want to use? This is important for the computational costs and complexity. You may want to have a look at: Brette et al. 2007 "Simulation of networks of spiking neurons: A review of tools and strategies"
I'm sure this does not answer your question completely, but since I'm not an expert in implementing RBMs these should merely be some points to start with.
Best regards!
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Hello Every body,
I am generating 3Vp-p from DAC inside PSOC 5LP. It looks very nice as long as i do not connect it with bridge (in order to excite the bridge). When i connect it, the voltage drops from 3 to 1/3 of that. I tried to place a voltage follower externally at the output of the DAC but as a result my signal becomes very noise and drops too (but not much).
I am failed to find the reason. Can any body have any idea?
Looking forward for your suggestions.
Regards
Awais
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Hi
I think that your first instinct was right, you must be draining too much power from the DAC, but you should still verify that. Try placing resistance at the output and measure the voltage. Look in the output impedance of the DAC and see that it respect the voltage divider.
As for the follower circuit, make sure that is has a nice clean voltage supply, and don't use a 741 OP-AMP, this hardly work in the lab, so it has a hard-time in real-life.
Finally, make sure that the frequency of your DAC is well within the bandwidth of the OP-AMP
Good luck
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Here you can find a question from Barrie Gilbert, from another thread:
======
As long as we're thinking about its problematical
behavior using the notion of infinite bandwidth,
I must note that the "capacitively-loaded resistor"
does not have to be represented as an infinitely-
distributed line.The attached jpg shows a simpler
feedback network which not surprisingly will also
cause the system to oscillate; and of course, the
actual value of the time-constant(s) doesn't have
any bearing on the maximum permissible gain --
though it necessarily will alter the frequencies of
oscillation.
.
Here's what I found: Using first an AC analysis in
which the scalar gain parameter A is varied over
some range while the magnitude of the response
maxima are noted, the value of A resulting in the  
maximum gain is (about) A = 20.9690082650087
and it is 220 dB  -- equivalent to an impedance of
j1011 ohms, at a frequency of 3.272960203..MHz
'
However, in further simulation experiments, now in
the time domain, in which the circuit was hit with a
2 ps-wide 1 Amp stimulus, the critical value of gain
at which the oscillation magnitude neither grew nor
decayed, was found to be substantially greater, at
(roughly) 21.1719. The oscillation frequency at this
value of A was (about) 3.2847944982971781 MHz.
.
This discrepancy in this critical value of A is larger
than I'd expected. Note that as a matter of general
practice I typically set unusually tight convergence
tolerances. In these experiments chgtol = 1e-22 C,
abstol = 1e-15, vntol = 1 nV and reltol = 1n. I have
qualified the accuracy of this particular simulation
environment over many decades of its use and as
contributor to its capabilities.
.
So... I am puzzled by this anomaly. Can someone
out there "can explain it away"?
Barrie
=======================
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dear Barrie,
I have modified the Matlab script so that the last RC section is a half-section (being N the number of sections and C the total capacitance, Ci=2*C/(2*N-1) for i=1...N-1 and C_N=C/(2*N-1) for the last section, similarly for R). The modified script is in the attachment. The convergence of A0max to cosh(pi) and the minimum in f0 can be observed as before, even though the minimum is now for N=8,9. I just report the values of f0 and A0max up to 10, where the values for N=4 match with the results you have obtained from AC simulations.
I do not have any intuitive explanation for the minimum in f0 (at least so far). I have just observed that it interestingly does not depend on the values of R and C.
By the way, it is not completely clear to me the reason why the whole last section should be with half-valued elements. Is it related to the open-circuit termination?
I fully agree with your comments about designers and researchers rushing to dead-lines and probably research is just what can be done between one dead-line and the next one, and often this time interval tends to zero...
N=3  f0=4101329.007544  A0max=37.250000
N=4  f0=3272960.203526  A0max=20.969008
N=5  f0=3067382.667517  A0max=16.714421
N=6  f0=2997286.482791  A0max=14.904838
N=7  f0=2971406.351085  A0max=13.939846
N=8  f0=2963261.941398  A0max=13.354938
N=9  f0=2963041.937718  A0max=12.969932
N=10  f0=2966534.406279  A0max=12.701430
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I want to use an electronic odometer to sense speed of my instrument & that gets recorded into a data logger. I want to test that if I cut the power supply of odometer for sometime, but power supply to data logger is continued, would I see a blank/zero reading when data is retrieved from the logger?
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Hello,
you've still gotten some work to do :)
the problem is that I know nothing about YOUR odometer and especially its speed sensor. Typically 2 types of speed sensors are 'standard': tacho generator (primarily delivering an AC voltage whose amplitude is proportional to the speed) and 'pulses' - meaning that you get 1 or more pulses per round.
Theses pulses may come from a simple reed switch (as with bicycle odometers) or from some kind of electronic sensor (normally a an inductive sensor or a hall sensor or something alike if talking about odometers from cars). Talking about cars the odometer may not even attach to the sensor itself - simply processing a signal generated nowadays by the ABS unit and delivered via CAN.
So, the first thing is to find out which type of speed sensor you've got. This means tapping the sensor interface (preferably with an oscilloscope) and monitoring the system during normal operation. Talking about pulse output sensors you may find out that the signal looks somehow 'disturbed' - meaning that the signal is missing pulses on a regular basis. This is normal for a lot of automotive sensors.
Not to handle too many alternatives in this reply: please come back when it's clear which type of speed sensor you've got - preferably with some kind of schematics and measurement plots. (If you can get documentation for the odometer this would also help.) Then it will be easier to assess how to proceed.
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Hi all,
I want to run my pi 24/7 and need some sort of battery backup.
When AC power is present the battery needs to be charged and the pi must be able to draw power at the same time.
When AC power is lost the charged batteries should take over to power the pi for as long as possible. A couple of hours would be nice.
I am thinking of a battery or super cap. Which one would be better and how i can connect these for automatic switching?
Looking forward for your suggestions!!!
Regards
Awais
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Dear Muhammad,
If you are looking for an off-the-shelf solution, I think that this product may suits your needs (just follow the link).
Bests
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Hello
I have few quires about modelling NBTI Trapping/Detrapping Model Based on Predictive Technology Model (PTMs) firstly for CMOS and then FinFETs for smaller tech. nodes such as 16nm/22nm/32nm/45nm.
Q1: What material PTM (CMOS and FinFETs) models used for Gate-Oxide (e.g. Aluminium oxide Al₂O₃ or Hafnium oxide HfO₂ etc...)?
Q2: Based on above material, what is the typical trap density (i.e. number of traps/cm^2) for 16nm/22nm/32nm/45nm PTMs?
Q3: What is the typical Activation Energy (Ea) value for trapped charge emission? and what is its' range?
Thank you.
Usman
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Dear Usman,
This question attracted me to carefully read it. I think the best people who can answer your question are the founder of the Predictive Technology models.
However interface state description and modelling is not a new topic. It started intensively with the advent the MOS and the MIS devices and transistors. The best studies made on the interface state and their effect on the material and device performance were made with the start of the MOS technology. The field effect could  be demonstrated first when the interface states between the silicon and silicon dioxide  are technologically controlled. The story of the interface states and their understanding and control is an appreciable part of the success story of the surface field effect devices.
So, to predict the scaling effect on the interface state in the field effect devices you have to follow the performance of the MOS and MIS capacitor and the their control on the FET transistor among the different MOS generations. Prediction is an extrapolation process based on the tendency of performance with time and the basic physical laws. So, one can discover the properties of the next node before it is realized in experiment.
 The interface states themselves are due to unsaturated dangling bonds at the surface of the material.
They can act as traps of a type of charge and also they can act a scattering centers impeding the motion of mobile charges and also they can act as recombination centers for the minority carriers.
Interface states are reduced by a process called passivization such that their effect is has little or acceptable effect on the device performance.
Yes this is not a direct answer on your question but may be helpful to consider some concepts and principles relating to it.
wish you success.
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is library set up time is always fixed, as it is store in our .db file as set up time vary from ckt to ckt and should we consider both while analysis?
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Yup, Both have to consider while analsysis
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Let a=1 b=1 c=1 are 3 inputs to exor gate then output  is 1 
(1⊕1)⊕1=0⊕1=>1
If the same inputs applied to exnor gate i am getting same output 
(1 exnor 1 ) exnor 1= 1 exnor 1 = 1
For all 8 possible inputs(3-bit) I am getting same output for exor and exnor gate.
My doubt is
1) Is  it possible to get same output for both exor and exnor gate for odd number of inputs.
2)Is 3- bit exnor gate exists?If exists is it obeys associative law? If obeys is it works similar as exor gate.
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Yes... for all odd inputs ..Exor and Xnor will get same output.... Exor =(Exnor)' is valid for even number. for add number both are equal....
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I have 9 electrode structures in an adaptive lens device that I am fabricating. All the 9 electrodes are covered by a single sheet of high resistance material (in Mohm range). According to device working principles, I am applying voltage to consecutive electrodes to induce voltage drops across the two electrodes and this translates to phase profile change. My question is when I apply voltage to say electrodes 1 and 2 and since the other electrodes (3 to 9) are floating, would there be a voltage drop across the other electrodes as well? On a side note, I separate low resistance electrodes which is common to all the 9 electrodes is grounded. 
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Yes of course I assume you are driving the electrodes through a multiplexer or switch ie 74HC4066 or hi volt analogue devices version .If not closed there will be about 7pF of less left of cap on the pad and a 10^12 ohm Resistance across the switch to whatever voltage is there. So you probably want to decide what voltage you want there.
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We know in CMOS technology a 0 (LOW) is usually represented with 0V to 1/3 Vdd and 1(HiGH) is represented with 2/3 Vdd to Vdd where Vdd is the supply voltage. That means binary bits 0 and 1 has different voltage level. Now, if we want to transmit binary digits over transmission media (wired) using serial transmission then what are the possible effects of these different voltage level on power dissipation. For example, if we want to transmit "1111", "0000", "1010", "1000" then which sequence will consume more power and why? Or if they consume equal power then why the voltage level has no effect on the power consumption?
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Actually the power consumption is composed of static and dynamic power consumption in general.
By advancing technologies the importance of static(specially leakage power consumption) is getting important. By the way i assume you are curious about dynamic power consumption here. 
Theoretically the worst pattern over a wire which consumes more power is something like 010101010101............ or 10101010101010........... In other words in each transition from 0 to 1 and to 0 again  a capacitor should be charged and again discharged which imposes a big power consumption. In one of my articles with the name of
"TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip"
the current flow of a TSV (which you can assume it as a type of wire), the concept of a current flow in a wire connected to two not gate in transistor level is illustrated. So if the current flow in a wire switches couple of times, it results in more power consumption. 
Consequently, back to your question, the best data transmission in terms of power consumption is the one which has less transition between 0 and 1.
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I have a cantilever steel beam of 1m length. I want to determine the strain near fixation due to the bending moment of a dead weight on the tip of the beam. 
I plan to place 3 strain gauges near fixation and close to each other on the same line level.
I have some doubts about managing the data. Shall I take the average reading and consider it representative of the strain on the beam? 
I believe that each strain gauge measures the strain in the zone it is placed on.
Any ideas?
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Actually a strain gage gathers data about the exact place that you attached it on. So the data of a certain strain gage is the strain of that exact point. Even a strain gage also averages the strain over a finite length due to its own dimensions. So averaging three results might not be a good choice, maybe you can use results seperately and then you can have a strain distribution over the axis of your beam. Sincerely.
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I'm working on simulated based test pattern generators. and in MATLAB I have written code for ATPG which generates tests based on PSO optimization algorithm. I have written codes for fault simulation too but it does not work very well on very large sized circuits (in gate level). So I'm looking for a fault simulator which can be linked with MATLAB?
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In addition to trying ProVER -(Free Download for Xp) as Suggested by Sdhakar Akki,you may refer to the following items.
1.International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011DOI : 10.5121/vlsic.2011.240661
FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER
TRANSFER LEVEL
M.S.Suma  and K.S.Gurumurthy
ABSTRACT
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage
with the RTL fault model is comparable to the gate level fault coverage.
KEYWORDS
Automatic test pattern generation (ATPG), fault coverage, fault simulation, stuck-at fault, RTL.
2. Fault Modeling for Verilog Register Transfer Level
Namita Palecha et al
ALSO
The following link gives you some ATPG work using Matlab/Simulink S/W.
A simulation model based on Matlab/Simulink is ... MATLAB/SIMULINK. Analysis of EVE tests proves ... Particle Swarm Optimization (PSO) based Fuzzy PI ...
P.S.
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I am working on a project that deals with signals with rise time as low as 1-2ns. To digitize the signal (so that it can be stored in digital computer for future reference) i needed a low power consumption ADC. During the literature survey i came across DRS4 chips that are wavelet samplers having analog bandwidth of 950 MHz and up to 5 GSPS sampling rate, but output is fed to a small speed Flash ADC. I did not understood then what is output of DRS4, and if you can please refer me a book also for practical application of wavelet sampling.
why 1024 capacitors are needed?
If analog bandwidth is only 950MHz then is it needed to sample it up to 5 GSPS?
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Dear Purnendu,
Yes,one samples 1024 samples in a time of Tsx 1024 and  convert them from analog to digital in Tcx 1024. Ts= i/5GHz and Tc= 1/ 33MHz. It turns out you can acquire only a portion of  the waveform  during the sampling time and overlook the rest of the waveform till the end of the conversion time. Then what do you deduced is okay.
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I studied that NAND gate occupy less area than NOR gate. I need explanation or proof why it so?
Although in NAND gate pmos are in parallel and in NOR they are in series, so NAND gate is faster than NOR. 
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It depends on your desing or gate library....
1) Both NAND2 and NOR2 gates have four transistors each one. Therefore, if you set equal W and L for all transistors, both gates will occupy exactly the same area. However, timing behavior would be very different (for rise and fall transitions).
2) To make lage digital circuits, ussulay a gate library is used. The gate library has information about each gate that can be used in the circuit along with its timing behavior (delays) . To design (set W and L of transistors in each standard gate) the gate library, an inverter gate  with minimum area but...  that has balanced (equal)  rise and fall delay is taken as design reference.  This means that the other gates (including nand and nor gates)  are designed in such way that their delays match with  this simetrical inverter.
3)  Remember that mobility of PMOS  is less than mobilty of NMOS, thus, to match rise and fall delays in the inverter, on-resistances of each transistor should be similar:   Tfall=RnCL   =  Trise= Rp*CL. The mobility differences is conmpenstated making Inverter PMOS greater than NMOS (lets said twice).
Then, simetrical inverter has:  Wp=Wmin x 2   ;   Wn= Wmin  
4)   The NMOS  stack arrangement in NAND gate and the PMOS stack arrangement in NOR gate are  sized up twice to match NAND and NOR gates delay with reference inverter delay.   Therefore, we have:
for inverter (ref):   Wp=Wmin x 2 ; Wn= Wmin
for nand:                Wp=Wmin x 2 ;Wn= Wmin x 2 
for nor:                    Wp=(Wmin x 2) x 2   ; Wn= Wmin
5)    Areas are:  
  Ainv= (Wp+Wn)* L  = 3 Wmin L
 Anand= (2Wp+2Wn)* L= 8 Wmin L
  Anor= (2Wp+2Wn)* L =  10 Wmin L
As can be seen,  NOR area is greater than NAND area  if a balanced timing behavior is required.
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There are many research papers on process variations  and aging affects on CMOS and FinFETs. However, I would like to have an opinion on this forum about what are the significant process parameters which can affect the circuit reliability? In my opinion: Fill in the blanks with your valuable comments:
For CMOS Process Parameters: TOXE, Leff, Weff and ___,___,___?
For FinFETs Process Parameters: TOXE, Lg, HFIN, TFIN, PHIG and ___,____,_____?
If the above are wrong in your opinion please comment on them as well.
Thank you.
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For CMOS devices, effects such as Random Dopant Fluctuation (RDF)  which impact on threshold voltage are of interest. Due to the uncorrelated nature of such effects devices may age different.  
For CMOS devices there is other random mechanism called Random Charge Fluctuation that  is related to the formation of a random number of trapped charges. These fluctuations increase as a function of stress time. 
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I have designed a micro strip antenna integrated with a DRA antenna. The micro strip antenna gives a UWB range and DRA gives a narrow band width. I have got isolation between antenna port 1 and port 2 which is  -10 db. how can I improve the isolation between two ports.
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There are many techniques discussed in the literature to improve the isolation between the antennas like using EBG structures, DGS structures, polarization diversity, changing shape of the antenna etc.
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I want to measure the amount of current (both dynamic and leakage) my logic sits in FPGA draws.
I want to measure the current to detect whether any hardware trojans is present in it or not.
For that, I want to design a custom board which only some FPGA with I/Os and particularly resistor in the power path, so I want to know is there anything ready made available only with this components?
Note to people that work on hardware trojans: How can I measure power (both dynamic and leakage) and delay of circuit to detect whether trojan has been inserted or not?
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There are s