Digital Design - Science topic

Hi Peter,

The "symbolic variable" technique is according to me as follows:

--> It means we will take one signal(free variable) and let the formal tool drive it on its own and we will use that variable in our formal (sva) property In that way we can verify a block that has repetition or multiple instances and makes FV engineer work easy.

Why I am asking about Nondeterministic Verification:

I was discussing data integrity check for memory(FIFO) verification with one of my colleagues with specifications as follows:

(1) Two port Memory is 1k Deep with a 16-bit width of each location

(2) Simultaneous Read and Write is possible

(3) All addresses are accessible without requiring to read/write in order

(4) When data is read out, output data == 0.75*read_data

Port 1 --> Write Port

input valid_wr

input addr_wr

input data_wr

Port 2 --> Read Port

input valid_rd

input addr_rd

output data_rd

--> I proposed creating a local variable reg [1023:0] data_store[15:0], and when data is read out we can check as follows:

valid_rd |=> data_rd == data_store[addr_rd]*0.75

without storing any data to local variables(reg), can we verify the data integrity between read and write data?

So I came across the term Nondeterministic verification which can do this verification without storing the data in the FV testbench.

I am not sure how it can be done without storing the data locally, if it is possible then please help me understand how it can be done.

Thanks,

Regards,

Viraj Rawal

Thanks for sharing. Wishing you every success in your work.

Tereza Zichová Tereza, I have an alternate idea. Use what you have, test it on a small group and try and observe what happens when the try to use the portal. Assume there's a lot you won't fix all at once. Fix what you can. Then do another test.

In other words, ignore what I said, ignore all the books about interfaces and user experiences and develop ideas for the tax portal from what you observe. --- Same with accommodating a wide variety of people. Test and fix things based of what you observe.

It allowed us to pack more punch in smaller spaces, considering one video card back then had 100s of dip chips and now all of that can be packaged into one qfn packaged chip.

You can see:

Input CM range can be an operating condition of your circuit. It serves to design the circuit that you want to observe with the comparator to operate in the region where the comparator behaves as specified.

Your understanding is almost correct. The ICMR is the DC range at which the input voltages are allowed to be, such that all the other specs of the comparator are still fulfilled. In the design you show, it applies to the DC gate voltages of M1 and M2. If it is lower than Vdssat(M5)+Vgs(M1/M2), the current source M5 will struggle and e.g. your slew rate specification would be compromised.

On the other hand, ICMR can also be a requirement for your circuit, if the inputs you want to observe are already defined. If it is e.g. stated as rail-to-rail ICMR, it means that your circuit must accommodate that range, in which case you'll have to make your design more complex, in case of the example, by providing the input circuit (M1-M5) in its flipped version (upside-down with all NMOSTs replaced by PMOSTs and vv), as well.

Seems nice. Make sure to keep it up to date, keeping in consideration all that is happening about topic at time, as well as how it may be improved further.

Dear Ajay Rupani ,

It is so as the logic value gets higher the number of interconnects become smaller. So, quaternary is more effective than the ternary. The other issue is that the quaternary logic can be easily converted into binary logic.

But as the value of the logic increases the power consumption may get larger as the power is proportional to the amplitude square.

Best wishes

Dear Ali Zeki sir, I read it somewhere that this configuration was used in chopper amplifiers earlier because of lower obtainable V_ce,sat .

Start with google. The keywords you want are "freepdk45 nangate"

this can be accomplished by designing low pass all pass filter by connecting the input to an R-C passive low ass filter whose output is connected yo the noninverting amplifier input. The filter input is connected at the same time to a feedback potential divider with equal resistor.

It results in a transfer function having the following form:

H(s)= (S-Z0)/(S+P), eqn 1

where z0 is a zero and P is a pole.

both Z0 an P are real. Also Z0and P are equal in magnitude.

It results that the gain of the filter is eqaul to 1 at all the pass band frequencies.

Using binomial transformations to transform H(s) to H(z), one can can get the equivalent low pass all pass filter design.

The binomial transformation are:

s= (z-1)/(z+1),

the analog frequency wa= tanh wd/2

wd= 2 pi fc/fs

fc is the cut off frequency

and fs is the sampling frequency

fc= p/2 pi

Using these expressions you can transform eqn 1 to H(z) form which are digitally implementable.

For more information please follow the handouts in the link:

By searching the web you can get a digital implementation of such circuit. Best wishes

Nice Dear Chris Rhodes

Hi Marnier Bate,

Can you please provide the circuit diagram for the cascaded inverter, I am working on a similar project.

Regards,

Mohammed

The problem in ECG is the 60 Hz interferenc. You can use one pole low pass IIR filter to solve this.

please read my book ( )

Proakis book (DSP) is very good on this.

Hi Fateh,

I certainly think so - that is my approach to Service Design Operations.

I have a question , can you let me know how to generate above power report.

Manish,

welcome,

The colleagues above have pointed out some techniques to filter you ECG signal.

You have to determine at first how your signal is contaminated by noise by comparing your real signal with the desired one. Knowing the difference, one can device the specifications of the filters one can use to clean the signal.

One practical way is to make FFT of your signal and discard the extreme frequency components  at lowest frequency and that at the highest frequency successively and reconstruct the signal again until you get satisfactory waveform of the ECG signal. This is some iterative method of low pass and high filtering.

Best wishes

Hi, I never used Virtuoso, but I used to work with real signals :)

In the Vernier delay line, one uses two sets of cells with slightly different delay times and counts the number of "flipped" flags, right? The measured time interval is equal to N*(tau_1-tau_2). Please, correct me if I'm wrong, but in my understanding  the uncertainty is within 1x(tau_1-tau_2), regarless of the software and representation.

power consumed in individual circuit cant be calculated in xilinx it always gives power consumed  by whole chip . better to go for full custom design in order to get optimum power consumption result

thanks

4

Feng, Find the attachment of the previously mentioned thesis.

Really i answered your question indirectly in the first comment. Assume you have a circuit under test and you want to determine its speed of operation which is the highest clock speed of the circuit. This speed for sure depends not only on the core of the circuit which perform the operations but depend also to large extent on the off chip load CL. If you drive CL directly from the output of the processing circuit you will slow down the operation of the circuit because the on resistance ron of the processing transistor is relatively large and so the propagation delay times will be large and the maximum operating frequency will be much less. So to speed up the the logic transitions at the output one has to add buffers characterized by their large driving capability which means that the their on resistance is much less than that of the small processing transistor.

This is common technique and there are many buffer circuits. The most important thing that the buffer must be capable to drive the CL with the required speed such that it will not limit the speed of the operation. 

The driver transistors have normally larger W/L ratio to decrease their on resistance which is inversely proportional to L/W ratio. So you keep L minimum and increase the width of the transistor. Normally buffers are cascaded transistors with increased W/L ratio.

To increase the drive ability of the transistors one can use the the BICMOS technology where one utilizes bipolar transistors fro the driving purposes at the output of the circuit while using cmos transistors for the logic.

In specifying digital circuits one has to give the maximum CL that can be driven by the circuit to achieve the required speed of operation.

WISH YOU SUCCESS

clear;

clc;

printf("\n Example 2.2\n");

// String insertion.

s="auto";...............//1st string or character array.

x="mobile";...............//2nd string or character array.

z=s+x;..........//concatenation of 2 strings.

printf("\tstring s=");

disp(s);

printf("\tstring x=");

disp(x);

printf("\tconcatenated string z=");

disp(z);........//dispalying concatenated string.

you must have the model library of your technology in ADS

    Insert some LUT after the wire,  the remain inputs  of LUT as input of the function,  using LUT to enlarge  the fan-out.    

High Speed Current Steering Logic (HCSL) outputs are found in PCI express applications and Intel chipsets. HCSL is a newer differential output standard, similar to LVPECL, with a 15mA current source being derived from an open emitter or source. Being un-terminated drains, they require external 50 ohm resistors to ground.

HCSL is a high impedance output with quick switching times, in can be advantageous to use a 10 to 30 ohm series resistor to help reduce overshoot/ringing. HCSL provides the quickest switching speeds, power consumption is between LVDS and LVPECL, and phase noise performance compares well with the alternative technologies. As always it is best practice to understand a receivers input structure.

I have already gone through these papers sir... I am expecting any such attack scenarios in practical experience.

Thank you again. 

If your design is integrated in FPGA, you can count the number of LUT/gates/interconnect. However, if you design a digital ASIC, the achitecture of the design is also a great parameter. The area and the excecution delay is also anothor parameters. Moreover, you can show the clock tree...etc You have a lot of parameters

So the question is how to design for high clock rate ... not how to set up one of the PLLs to generate the clock?

Getting the absolute max clock rate may not really be possible in any practical design.  But here are some techniques:

In the constraints editor, set a clock rate.

Pipeline the design.  By that I mean, divide the computation into very small pieces with very little serialization in each piece, and latch the results, going on to the next piece in a different clock cycle.  You need to have a function which can be handled in a single LUT (look up table) in order to get maximum clock rate, because that is basically how they define max clock rate.  It is the inverse of the delay of one LUT. 

So for even a simple adder, you cannot propagate a carry.  You would have to do it one or two bits at a time (you can add 2 bits + 2 bits with a 4-input LUT).  You would have to save the carrys.  But even that might require routing them to another LUT.  And none of this allows routing to distant LUTs which takes more time.  In other words, you can't really operate at max clock rate.

In my view, capacitance and resistance parameter of the net also play major role in digital design. So, you may think about RC value in you design

The following page might be helpful

from which paper is this plot? May be we have the datapoints.

Cheers, Rainer

Dear Yu Kun Wu,

Look the link. May be useful.

Regards, Shafagat

I would think that if you know the array size, you can do an estimate of the bit line and word line lengths. You can assume minimum width.

An important question, It is very required to get the temperature profiles in chip. 

Here i will introduce how to solve the problem.

In order to solve this problem you have to calculate the power dissipated in every gate say at the the location x,y in the chip. Assume that the obtained power is P (x,y) which is the power profile. The power profile may be dependent on the time but let us assume that its constant other wise the problem will be more complicated since it will be three dimensional. 

-Then you have to work out a thermal model for the chip. You have to take into consideration the heat flow through the encapsulation. For example the chip is bonded to a metal frame with a metal legs. That is you have to model also at the same time the environment of the chip as it affects the disposal of the heat from chip.

- The model is approximately based on thermal conduction and storage by the materials conducting the generated heat flow to the ambient. It is so that every elemental volume is represented by a thermal resistance in parallel with  a thermal capacitance. So, you can discretize the volume and model it by a lateral and vertical Rth-Cth network. Rth and Cth can be calculated as

Rth= delta x or delta y/ kth * area element

Cth= The specific heat csp * area element * delta x or delta y

where Kth is the thermal conductivity of the material

The network will be driven by the power sources P(x,y) calculated before acting in the nodes at the surface of the chip. Every point, in the network has a temperature relative to the reference node which is the ambient.

- there is a complete formal analog between the heat flow and the current flow 

- You can solve this network by any network solver like PSPICE.

Since the properties of the materials are known, the dimensions are also known, then one can solve to get the rie in the temperature of every node relative to ambient.

Other solutions can be obtained by solving heat transfer equations. 

The engineering approach is what i introduced here,

For more information please refer to the link:http://cache.freescale.com/files/analog/doc/white_paper/BasicThermalWP.pdf

wish you success

Hello Bhaskar,

You can also think of a single-opamp differential amplifier with unity gain or even higher. Feed the differential output from your INA to this DIFF-AMP  and then get the single ended output without compromising your signal swings and supply voltages.

Hope this works exactly as what you want to do!

Best Luck!

One more thing

Timing report after synthesis is not very accurate.

It would be much better to take timing results after place and route. these values tend to be more realistic, as it is estimated after implementing the design routing for the target FPGA.

Good luck

The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays

According to (M.S. Hrishikeshi et. al. the 29th International Symposium on Computer Architecture)

The difference between pipeline depth and pipeline stages; is the Optimal Logic Depth Per Pipeline Stage which about is 6 to 8 FO4 Inverter Delays. In that, by decreasing the amount of logic per pipeline stage increases pipeline depth, which in turn reduces IPC due to increased branch misprediction penalties and functional unit latencies. In addition, reducing the amount of logic per pipeline stage reduces the amount of useful work per cycle while not affecting overheads associated with latches, clock skew and jitter. Therefore, shorter pipeline stages cause the overhead to become a greater fraction of the clock period, which reduces the effective frequency gains.

I do not think it is possible to download them for free. But many be you can interact with the application engineer and get some help from them.

As far as know there are no proved solutions yet to perform ab initio calculation. It is not an easy task since it needs accurate analog knowledge of the circuit and its digital activity. But of course it can be estimated: you may proceed performing accurate analog simulations on your digital gates to estimate power consumption per glitch and how it depend on loading capacitance. If possible make analog montecarlo simulations to estimate average values. Once you know average power consumption per glitch, you should estimate the rate of glitches per second on the specific circuit by providing custom or random stimuli in digital simulation of the concrete circuit.

Cost and power dissipation are the two main reasons. Scan clock is only a couple of 100 MHz so as to keep the test power dissipation in check.

Multiplexing was initially developed for telegraphy, and later telephony, originally by Jean-Maurice-Émile Baudot, 1870, patented 1874. So you have to go way back, and it looks like the earliest research papers were in German (common back then). The article below has an extensive list of references.

Looks like an early article was by "anonymous":

[32] Anonymous, On the synchronous-multiplex telegraph, Proc. Am. Philos. Soc. 21(114) (1883), pp. 326–328

There's a start for you, eh?

Use an oscillator and feed the clock cycles. you can obtain these in different configurations. I use a 16MHz clock for ATMEL boards.

This can be quite easily obtained with fractional division PLL solutions. See e.g. http://www.silabs.com/products/clocksoscillators/clock-generator/Pages/default.aspx

I deeply thank sir, Mr.Christopher Topping.

The most common way to achieve this is using an FFT implementation or Polyphase filtering architectures. From an implementation point of view, the WOLA filter based on an FFT is the most efficient and flexible. The output carriers can be multiplexed into an FDM stream using simple time multiplexers.

"""" What are the areas where FPGA (Digital Design)/ CMOS Analog Design comes in Control Systems? """""

--->I would like to know the areas where FPGA / CMOS Analog Design and Control Systems are related?

--->I am a beginner in FPGA and thus planning to learn Verilog. And would like to apply it in Control Systems. (I am doing my Masters in Control Systems). I would also like to know if CMOS Analog Design is related to Control Systems and the areas too.

-------OKKKKK seeee below

DIGITAL DESIGN AND IMPLEMENTATION ---- FPGA or Microprocessor or MIcrocontroller

Digital design what where why ???? whenever you want to process(manipulate), store you will be doing Digital design and all algorithms whatever may as all are add ,sub can be viewed as Digital CIRCUITS using logic GATES(Universal gates) using specific logic FAMILIES (RTL,DTL,CMOS,TTL and more ....)

ANALOG (IC)design : --- Using Discret analog IC or specifically made Analog Circuit and IC from silicon level (VLSI@microelectronics) using Transistors (BJTor MOSFET or BICMOS ------> ur designing the transistor itself for your specific criteria at SAND-silicon level)

Analog Design (CMOSorBJTorBICMOSor.....)what where why????? when High speed(Actual speed of signal involved real world) and high precision or accuracy (Actual signal accuracy of signal involved as it is as present in real world )

MIXED signal IC design --- dont like to over fill your cup it may spilll

just example: ADC- in that circuits it contains both where comparator , FLIPFLOP (Digital)and Opamp (Analog)

NOWWWWW-- FPGA,MICROPROCESSOR <MICROCONTROLLER<IC DESIGN SILICON LEVEL or implementation Platform ----JUST PLATFORM TO MAKE IT

CONTROL SYSTEM algo , DSP algo , or any mathematical works have nothing to do with either of above

control system or DSP have its won research areas or limitations to overcome or diificulties to be reduced

u msg what is the actuall problems ur facing in that , then i will suggest

if clock shouls not used , then use a oscillating circuit or a stable multivibrator internal to that as part of circuit

regarding applying same input(output of previous stage) for driving many other cqt input cause ----- low speed or low reduced driving ability (V and I decreases)at the input , there are options to overcome u mnetion actuall more precise about the criticalities ur facing

LTC3108 from Linear Technology is a good candidate.

I use it for energy harvesting applications.

Design in paper you referenced requires input voltage 700+-100 mV. It is current state-of-art of charge pumps.

Dear afaq ahmed there are simple current comparators which use the process of current mirors ahich could be used for current mode comparision purpose

Dear Nandan Kumar Jha,

"50% duty cycle" concept is ('high' time = 'low' time). And this is in general in order to obtain a count sequence where each and every step pauses for the same amount of time.

However, duty cycle can be modified according to the requirement. And the procedure and the basic concept is that "the basic square wave generator signal can be modified to obtain an adjustable duty cycle pulse generator, by providing a separate charge and discharge path for capacitor hence the difference in rise and fall".

And in many situations we use duty cycle less than 50%.

for digital hardware, the natural numbering system is binary (base 2). but expressing anything in binary causes way too many bits to be used, so , it's not practical. hexadecimal allows us to use 4x fewer bits, so, it is very useful. besides no processor uses anything less than 4bits, so, hexadecimal is the most common when expressing numbers in a way that is most suitable for digital hardware.

example 1101 1010 is the 8 bit numbef which can be expressed a lot more cleaner as the he equivalent DA.

on the other hand, humans are most comfortable with DECIMAL which is base 10, as opposed to HEXADECIMAL which base 16. In DECIMAL , 1101 1010 would be

218

Karnaugh Maps (K-Maps) and Quine-Mc Clusky algorithms remain the best ways to reduce the digital designs in their minimum forms ( Sum of Product ) or (Product of Sum). However, I don't like the use of don't care terms as being arbitrarily logic 1 or logic 0. Don't care terms create spurious outputs if they are clubbed with 1s in KMAP minimization. Different computer programs have been developed to do the logic reduction for KMAP or Quine Mc Clusky.

Hi Srinivas,

I haven't used Xilinx SysGen for partial reconfiguration. However, I have used partial reconfiguration tools extensively for my research. You may wish to read my paper on partial reconfiguration "FPGA-Based Reconfigurable Hardware for Compute-Intensive Data Mining Application", which describes how it is being done. This paper received the best paper award.

Hope this helps.

Darshika

Buffering incoming data is one way, but there are limitations on buffer size and on high-speed, it will be difficult to buffer all the data passing by in milli-seconds.

Another way to do it is to have two PDR regions/modules. Data is MUXed in between the two, so that until the newer one is not configured, data is processed by the previous unit. This ofcourse assumes that some of streaming input can tolerate being processed with the old unit.