CMOS - Science topic

Hello everyone.

I am a graduate student working on a CMOS photo sensor (PGSPAD). My sensor is almost similar to a CMOS MOSFET. My question is,

I want to plot drain voltage vs drain current at different gate voltages. But I am confused about which one to use for the drain voltage "innerVoltage" or "OuterVoltage"? And what is the difference between the "innerVoltage" and "OuterVoltage"?

please give me the answer how to calculate the W/L ratio in analog circuits designing

Is it possible to build two or more kinds of doped silicon on each other? For example, building a 1 um p-doped silicon on 1um n-doped one? while they have been separated by an insulation layer?

Dear Professors, Scientists, Researchers, Academicians, and Industry Professionals, Greetings of the day!!! We hope you are doing well! We would like to cordially invite you as chapter contributors. Please see the attached PDF file and the following information. CALL FOR BOOK CHAPTERS (No Publication Fee) CRC Press (Taylor & Francis Group) (Scopus Indexed) We are editing the book entitled "Circuit Design Approach for Modern Applications” to be published by CRC Press.  I would like to take this opportunity to cordially invite you / your team to submit your book chapter proposal that aligns with the title of the book for consideration for publication. Your proposal (Minimum 2-3 pages) should be submitted as an email attachment to e-mail:  cdamacrc2024@gmail.com Book chapters for the following themes with advanced devices like TFET, NCFET, Nanosheet FET, GFET, HEMT, FinFET, and AI - ML applications (but not limited to) are welcome: • Conventional CMOS Circuit Design: Challenges and Scope. • Models for CMOS devices • Operational amplifiers • Linear voltage regulators with low dropout voltage • Sinusoidal oscillators • Wideband amplifiers • Analog phase-locked loop circuits • Digital-to-analog converters • RF receivers • Telecommunication circuits • Optimal approaches for enhancing energy efficiency in circuits • Low Power ICs • Methods for enhancing signal integrity in digital circuitry • RF circuits for modern Internet-of-Things devices • Differential and Instrumentation amplifier • Low Noise Amplifiers Furthermore, the submitted proposal must include the following details: 1. Title, 2. Authors with affiliation, 3. Table of Contents, 4. Abstract and Keywords, 5. Nature of work: Review/Research Kindly acknowledge editors via email in case you are interested in contributing to any book chapter. Important dates and other information Proposal Submission Deadline* December 25, 2024 Proposal Acceptance Decision: January 10, 2024 Full Chapter Submission Deadline: February 28, 2024 Review Reports to contributors: March 10, 2024 Revised Full Chapter Submission: March 20, 2024 Final decision: March 30, 2024 For any inquiry email:  cdamacrc2024@gmail.com Details and guidelines for full chapter submission will be provided after acceptance of the proposal. Note: - Plagiarism in the chapter should be less than 10%. The contribution must be original and not submitted for publication elsewhere. Chapters must be in good English. Kindly forward it to your circle for wide circulation. With Best Regards, Editors:-s4 Dr. A.Andrew Roobert , Associate Professor, Department of ECE, Francis Xavier Engineering College Tirunelveli, Tamilnadu, India. Dr. M.Venkatesh, Assistant Professor & Research Head, Department of ECE, CMR Institute of Technology Bengaluru, Karnataka, India Dr. Shiromani Balmukund Rahi, 1Assistant Prof, Gautam Buddha University Greater Noida, UP, 2Senior Scholar, Indian Institute of Technology, Kalyanpur Kanpur-208016, India. Dr. G.Lakshmi Priya, Assistant Professor (SG II), SENSE, VIT University, Chennai  Tamilnadu, India Mr.Samuel Tensingh, Associate Lecturer, School of Biomedical Engineering, University of Sydney, Australia

I am looking for a PhD candidate for integrated analog and mixed-signal CMOS circuits design in the research field of integrated optical transceivers and artificial intelligence systems. The field of research is circuit design for optical communications transceiver and the usage of AI  systems to enhance the optical communication link performance. The research contains design,  simulation, layout, integration, realization and characterization of integrated circuits and systems. Required Tasks: ● Design of analog and mixed-signal integrated circuits using CADENCE. ● Design and Synthesis ANN models on FPGA or deployment on MCU. ● Involvement in high quality research projects under professional supervision. ● Presentation of project results at international conferences. ● Conduct a PhD thesis under Dr. Mohamed Atef supervision at UAEU. Applicant Qualifications: ● Above-average abilities in your studies. ● A master’s degree in electrical engineering or a similar degree. ● Motivation, initiative, flexibility, and the willingness to work in an international team. ● Experience in integrated circuit design would be ideal. We Offer: ● Participation in international conferences. ● An interdisciplinary research unit with a young and motivated team. ● An international scientific network. ● A friendly, helpful, and international work environment. ● To do a PhD thesis at United Arab Emirates University (UAEU). ● Fair pay according to the international standard and UAEU rules. Application Submission: Please send your application documents (Motivation, CV, academic transcripts, publications, possibly internship/work references, MSc. Thesis) to Dr. Mohamed Atef, Electrical and Communication Engineering Department, United Arab Emirates University (moh_atef@uaeu.ac.ae)

Dear authors,

Does anybody know what the minimum allowable width of transistors at 22nm CMOS process technology is? Is it 22nm or 44nm or something else?

What about constructive widths? I mean, is it possible for manufacturers to build a transistor which its width is W = 2.34*Lmin or W = 1.37 or ... (Lmin = 22nm) or the width of the transistor must be N*Lmin, where N can be just 1,2,3,4, ...?

Hi,

I am getting negative capacitance values for Finfet, when I am plotting the data files. I did AC analysis at a constant frequency of 1e6 and swept Vg from -0.7 to 0.7.

What can be the reason for it?

Thanks & Regards,

Parshant

Design of CMOS circuit to create the signal Vsig. The supply voltage is Vdd and t1 is a delay which is equal to 5ns. The picture is attached.

Is system operating with low frequency dissipates higher leakage power than system operating with high frequency?

Both SRAM and Flip-flop are volatile memory element. Is there any applications where both are used?

CMOS,PIN,Lateral,verticlal

See the symbol attached. However, while examining internal architecture of CMOS based CCII, both the current direction i.e. Ix and Iz should be in the same direction. Why does this happen?

I wonder if the following "image amplification" idea would work.

For instance, imagine observing the sky and you are interested for the H-alpha at 656nm wavelength. As there is low signal level, you have to do a long exposure and would also eventually get a high background noise..

Add an array of amplification medium (656nm laser diode array without OC and HR mirrors) to the front of every CCD/CMOS pixel. Every time a 656nm photon hits the given array element, it will be amplified, so you get a larger signal on your sensor. Other wavelengths wouldn`t be amplified so it works also as a very narrow band pass filter.

Using a similar design but somewhere at the night sky glow wavelength, one could build a night vision kit.

There must be a lot of practical or theoretical issues, I wonder what these are. Let me know your thoughts.

I want to calculate and design a CMOS SR-Latch built from 2 cross-coupled NOR gates. However, I have problems with finding a source, that has a step-by-step explaination of the design procedure to find the adequate W/L ratios of the transistors.

Can you recommend some litereature or other sources where such a design procedure is explained in detail?

Thanks in advance :)

Hi,

I am currently designing a two-stage open loop comparator (differential amp + current sink inverter output stage) using Cadence.

In order to ensure a "safe" and error-free operation of the comparator, it is said that the inputs of the device should lie within the defined input-common mode range (ICMR). To my understanding this means: If both inputs are within the ICMR, then all transistors should operate in saturation mode. Saturation mode, NOT just turned-on (i.e. saturation OR linear)?! Is that true? Correct me if I am wrong.

Maybe somebody could give a definition of the ICMR with respect to my specific application. i.e. Why does it matter?

Moreover, I encountered an issue when shifting one of the inputs to the lower ICMR-range and kept the other exactly in the center of the range. In the DC-simulation, one of my input transistors switched into linear operation mode. Is this behaviour normal or did I possibly calculate something wrongly?

Your help and hints are well appreciated :)

P.S. How can you "simulate" the ICMR in Cadence and verify you calculation results?

Does anyone know a software I can use to make process flow diagram of CMOS or MEMS? Right now I'm using Word or Excel but I'm wondering if there's something better.

Just to clarify I'm not looking for simulation software but instead drawing software.

I found that, latches can capable to hold the correct data even the data changes slightly before the falling edge of the clock.

What is the major difference between the pre-layout and post-layout simulation?

In the passive mixer section of the CMOS RF Receiver front-end, I am unable to obtain the expected voltage conversion gain, which is coming in negative dB. In simulating a mixer, which operational region should it represent, and can anyone make suggestions?

I have designed a CMOS image sensor device in TCAD and need to convert its equivalent model in a SPICE simulator to obtain the overall read noise of the designed pixel with backend electronics. Would I need to build the photodiode model from scratch in SPICE or can I use some already available PDK for the purpose?

how one can estimate the drain area?

preferred tool is HSPICE

In SPICE simulation, i found power dissipation in hold mode gives negative values.

I want to draw a circuit with CMOS where for an input Voltage of (+-)Voltage I obtain a output of +Voltage?

Does the -31dB sensitivity CMOS rectifier circuit collect, energy from surrounding RF waves?

Hi,

I am designing a CMOS inverter in the cadence tool, can anyone please tell me how to measure its voltage gain?

Thanks

I need a comparator with an offset of less than 5 mV. It is better to be designed in 0.18 um CMOS technology and the dimensions of MOSFETs should be clear. Thanks.

I would like to design an RF rectifier based on 0.18um CMOS technology.

if any one recommend me a high impact paper I could start with, I would be appreciate.

Dear all friends,

Please suggest, Is tunnel FET practically over take the limitations of Conventional CMOS Low Power Technology Limitations?

Generally, we always try to give low input to operate a device. What are the minimum values of voltage for CMOS technology and magnetic field for spintronics technology?

What are the commands used for PVT variation analysis for CMOS circuit in LTspice?

I am trying to extract series resistance (Rsd) of MOSFETs based on FDSOI/Bulk Technology, size range of these devices are 22nm/28nm to 40nm/100 nm respective of the technologies mentioned above. I am following these research articles:

1)

2) https://ieeexplore.ieee.org/document/4509332

These articles follow similar method for finding total resistance, even though they don't explicitly say how they figured it out. From my understanding (I might be wrong!), I chose single Id-Vg curve for Vds=~0.1 V and find Rtotal= Vds/different Id (for a specific range say when Vg>>Vth). Is this the correct approach?

I also have electrical characterization data at different temperature (Cryo to Room Temperature). My ultimate goal is to have a plot showing Rsd Vs Temperature for different technologies. With Article 1 and 2, I am getting increasing trend from low to high temperature for different sizes of Bulk devices. But for FDSOI, following article 1 is giving me mixed trend whereas with article 2, I am getting an increasing trend as well. I am not sure what to make of these trends. Basically, at low/cryo temperatures, mobility should increase, that could explain decreasing trend in resistance but there could be carrier freeze out which could increase Rsd at low temperature. There's a reference for bulk tech here (Chakraborty, W. et. al. “An Empirically Validated Virtual Source FET Model for Deeply Scaled Cool CMOS”, accepted in IEDM 2019) where they show increasing Rsd trend.

If anyone could help me out that would be great. Also, If someone could explain the method of Rsd extraction based on the papers/any other resources that could be helpful as well.

Is threshold voltage of transistors decreases with decrease in technology? In 22 nm PTM CMOS model card, i found zero baised threshold voltage is higher compare to 32nm, 45nm......

In my design I require some transistors with high threshold voltage. At schematic level, what changes should I do so that I can get transistors with high threshold voltage.

"Self-fulfilling prophecy" is Moore's own definition, while "a convenient fiction" is somebody else's...

I have decided that, giving some excerpts from two relevant articles will be more helpful than trying to explain my personal views in detail.

A.Z.

Excerpts from the article "Was Moore’s Law Inevitable?" by Kevin Kelly:

Excerpts from the article "A Moore’s Law Mystery" by Rose Eveleth:

Is there any open source software for CMOS based circuit layout design for some academic purpose?

we want to calculate the dynamic range of the one-transistor active pixel sensor (1T-APS), we know the largest light signal the sensor can detect, but it is not easy to clarify the weakest light signal(decided by the noise of the sensor). until now, we just get some idea about the dark current noise, how about other noise ( like the reset noise)? And how to calculate them?

If we talk about CMOS 32nm 22nm 14nm process, is the threshold voltage of NMOS or PMOS device is constant wrt particular technology nodes viz. 32nm 22nm or 14nm CMOS technology. Due to body effect, Vth is not constant. But if body effect is ignored, what is the value of Vth in 32nm, 22nm, 14nm CMOS technology?.

In PTM, at 32nm technology nodes, the value of Vth0=0.49, so can we conclude that threshold voltage at 32nm technology is near about 0.49V. ?

It is a general practice to introduce Ground Plane in FDSOI devices under the BoX. The Ground Planes are introduced by Ion Implantation through Top Si layer and Buried Oxide. I wanted to know that by doing this implantation, don't they harm the crystalanity of the Top Si layer in which the FDSOI MOSFET will be formed ? Since in FDSOI, they prefer very Low doped or even undoped Si channel, so by doing Ground Plane implantation, don't they affect the intrinsic/undoped/low-doped nature of top Si layer.

Greetings!

If we talk about CMOS 32nm 22nm 14nm process, is the threshold voltage of NMOS or PMOS device is constant wrt particular technology nodes viz. 32nm 22nm or 14nm CMOS technology. Due to body effect, Vth is not constant. But if body effect is ignored, what is the value of Vth in 32nm, 22nm, 14nm CMOS technology?.

In PTM, at 32nm technology nodes, the value of Vth0=0.49, so can we conclude that threshold voltage at 32nm technology is near about 0.49V. ?

I want to look at the beam profile with a CMOS array. I focus the collimated beam with a long f lens and observe it near waist. I noticed that using stacks of ND filters distorts the observed beam, probably because of interference of multiple reflections.

I am thinking of crossed polarizers (I have a diode fiber-coupled laser and random polarization) or maybe a polarizer and a single plate at a near-Brewster angle.

Any other suggestions?

I want to get the spectrum of an object illuminated by an incoherent source at the CMOS sensor without using any lens.

we need to move the positive charge away from the surface so that electrons from drain and source can form the inversion layer without recombination. But how does 2*bulk potential help in that?

Can anyone tell me how to simulate noise of CMOS image sensors, such as thermal noise and flicker noise with sentaurus TCAD?

I am designing a circuit based on 65nm CMOS. I would like to have the 65nm PTM CMOS model for 2020. I opened this link: http://ptm.asu.edu/, then I found the PTM models 2002 to 2008 and when I import these models in the 'ADS 2020 he doesn't accept, so I don't know what to do anymore, I need your help.

Best regard. .

The Output buffer consists of a source follower cascaded with two CMOS Inverters and uses a self biased CMOS inverter to set the bias current for the source follower and bias point for the two inverters.

I was reading the paper "Analysis of Temporal Noise in CMOS Photodiode Active Pixel Sensor" but I am a bit puzzled about noise calculation during integration. In particular, can someone explain to me how did we come up with the so called varying capacitance induced conductance formula?

I am unable to find the correct simulation result of DXCCII. I have designed DXCCII using CMOS and simulated by HSPICE using 0.18 μm TSMC lib.

Can anyone suggest what mistake i have made?

Waveform is attached.

Hello,

My project requires fast data read out (4000 data read outs (frames?) per second,

I need to get data at least every 1ms and save it to computer,

When I check CMOS sensors from here for example:

It looks like it can gather spectra in 10MHz rate and that seems to be unbelievable for me, since I also know spectrometer that has 500frames per second speed with this same sensor,

Also, this sensor needs driver. What is driver ? Will it affect the speed ?

Whats the difference?

Any help is really appreciated, I appreciated reading and lecture sources too,

Thanks a lot,

Seyitliyev

Studying CMOS image sensor and CMOS technolgy I noticed that the pixels of CMOS image sensor are composed by a photodiode and 3 or 4 transistors (which should be nMOS or pMOS), but not by CMOS, which should be a combination of the two.

So my question is: why CMOS image sensors are called "CMOS" if they use simply nMOS or pMOS separately and not together as they are in CMOS technology?

Is CMOS used somewhere else in the CMOS image sensors (other circuits)? Otherwise why call them CMOS image sensors?

P.S. My knowledge of electronics is very limited and what I write may be quite inaccurate or even wrong.

Can anybody suggest an open source CMOS process and device simulator that can be used for academic purposes?

I had found some literature that develops MEMS stress sensor (CMOS, N-MOS, P-MOS). However, I can't find commercial solutions for this type of sensor. Is there any replacement? (Stress measurement, tiny dimension).

Many thanks

I want to do a thermal inspection of an hot tube distant 8 meters from my camera .

Is there any chance that i can reach out to infrared wavelengths with some IR filters ?

What if i use the Daylight cut filter and remove the infrared cut filter from the camera ?

I have seen some products like FLIR phone converter , that display the thermal image using a phone's camera.

I'm seeking the physical technology behind it somehow if it's possible to realise

In many CMOS circuits i have seen Floating inputs implementation. how do we practically implement the same?

Beyond, how do floating input behave in a digital mechanism? A logic "low" or logic "high"?

So as per my understanding the pixel size (let's say in microns) of a camera like ccd or scmos would also depend on the rest of the optical setup like the objective used. So one would carry out a calibration experiment like with a nano-positioning stage to calculate the pixel to micron ratio. But I found this website ( https://bostonmicroscopes.com/product/andor-zyla-5-5-scmos-monochrome-microscope-camera/ ) where they have mentioned the pixel size as part of the camera specs. How is it possible? Also in another paper the authors mentioned the imaging area (say, x micron sq.) and then ROI (say y x y pixels) and so mentioned the pixel size as x/y. So how do I get this imaging area?

Hello,

Usually, by biasing Vgs < Vthreshold of MOSFET, we can push MOS into sub-threshold region. My curious question is: How much value of Vgs is "good" as a "rule of thumb"?

I have referenced to "Trade-offs and optimization in Analog CMOS design" book, and they supplied a good reference (please check the figure below). It seems to be good from this book is that we should bias MOS such that -4.5nUT < Vgs - Vth < -2nUT, which is equivalent to approximate value in a range of: -163 mV < Vgs - Vth < -72 mV (n is the slope factor defined by EKV model from EPFL, UT = kT/q is the thermal voltage).

Could you guys confirm or give out any recommendations?

Thanks!

Hi,

I am trying to model TSV in HFSS. I have no idea about TSV sizing in different technologies. Do you know any reference or document including the size of the TSVs in different CMOS technologies(especially 180n and 65n)?

Thank you in advance

I wonder that can we create a CMOS camera with GaAs wafer? I know that it is almost impossible to create a single crystal wafer from GaAs but If you create a camera using GaAs wafer and if you are lucky to get some large grans in your camera, in this case is your camera work? Work!!! I mean that camera can look a Frankenstein monster but Since I do not need to see whole pictures, I can work with it. In 4k pixel camera, If I can get 500 working fine pixel that is enough for me.

HDL - VLSI Circuits

I would like to mark the position of a small translucent specimen (a live Drosophila brain) on a depression slide. The depression is coated with sylistic to better adhere the brain tissue. The well is then filled with saline. We use a 20x objective with epifluorescence to image the neurons on a CMOS camera. There are no eyepieces on this custom built microscope - the image goes right to the computer screen. It can be difficult to locate the specimen and we'd like to mark the position so we can find it quicker. What ever technique we use can not cause autofluorescence and a simple dot with a sharpie won't work. Any other suggestions?

I am curious what could be hot research/study topics in the fields related to CMOS integrated circuits (both analog and digital).

My specific questions should be:

1. At device level:

- What are new potential devices? Are there some new sub-micron devices, I mean nano-scale CMOS devices?

2. At circuit/system levels:

- What are challenges? Are there any new circuits needed to be designed and invented?

- What are the hot trends, for example in the past few years: (a) Ultra-low power with sub-threshold circuits for energy harvesting applications, for portable/wearable applications; (b) Circuits for Intelligent Artificial (AI) applications, (c) Circuit for biomedical applications, (d) Circuits for neuromorphic applications and so on.

3. At application levels:

- What are the hot trends of applications that force CMOS integrated designers/researchers to think about?

Some publications and/or information will be highly appreciated.

I'm assuming that current leakage would be effecting the slope, but not sure how to articulate why. Any assistance is appreciated!

With the rapid development of traditional CMOS technology some drawbacks, started to generate inevitable problems for the circuits. Recourse to another technology like QCA is necessary and the gradual transition is a proposed methodology.

We used linear array CCD to capture movement object pictures. When extracting information from the pictured, we were bothered by the intensive sinusoidal stripe pattern (like the files jpg).

What the reason for it?

Hi, Does anybody explain the use of multiple valued logic in cmos vlsi design?

Dear all,

I am requesting you all to give me answer/reason for the following question?

Why static power increases with the increment of temperature in CMOS memory circuits or CMOS circuits? What is the relation between temperature and static power? why static power increasing with temperature in most of the memory circuits for example in content addressable memory (CAM)?

Thank you in advance.

Hello, every one.

Does anybody know how to measure leakage power of a digital circuit such as Static-CMOS NAND gate or Full Adders, etc using HSPICE? If you know a command to measure it, would that command be used for both 180nm and 32nm CMOS process technologies?

Thank you.

A book or some set materials are not even close to enough for CMOS Layout design. But to start with, I require a good book and some relevant materials. I have done the layouts of some basic static CMOS circuits. Now it is the time to make the layout of the design I am working with (an architecture of ternary CAM with some control and gating circuitry).

Which books or materials I can refer for an optimised layout? I am going to use virtuoso layout suite for the design.     

In the design of power converter ICs, sometimes the power switches are not given by the PDK. That means we have to design the power transistors as the switches (NMOS and PMOS).

Since the power loss causes by conduction loss and switching loss, the power efficiency of the converter is decided by a very well trade-off between these losses. The conduction loss depends on the Ron of the switch, that means larger switch (with larger Width of the transistor), the lower conduction loss. In the mean time, the switching loss increases since the parasitic capacitor of the power switch increase. 

So I would like to know the method of sizing the power switches in the converter for maximizing the power efficiency. Any ideas or recommendations/reference papers from you are highly appreciated. Thank you so much.

The 65nm CMOS process has 9 metal layers separated by Vias

Hello,

I am searching for a topic for my doctoral thesis around

I am intersted in:

- Consumers: customer journey, loyalty, trust, brand ambassadors, reviews, engagement, Millenials, Digital services

- Marketing org: impact on marketing organization, role of future CMOs

- Measurement: No equality in measurement. Each market player (Google, Facebook, Twitter etc.) uses their own industry standard for measurement.

What do you think is most relevant. I am also happy to hear about any topic ideas for this thesis :-)

Data: I have access to digital media agencies and direct clients of large brands in the german advertising market for interviews.

THANKS :)

I am trying to extract the effective channel length of a MOS transistor in 130 nm CMOS technology (Lmin = 120 nm). Or I should say the measure of lateral gate/drain (or gate/source) overlap using DC current methods described in "MOSFET modeling for VLSI simulation" by Narain Aroa. My problem is that each method yields a (vastly) different number.

Could somebody please help, shed some light or suggest some new methodology?

Lukas

How should we protect GPIOs from unwanted conditions such as short circuit, high voltage, etc. Is it sufficient to use a series resistor especially when the pin is driving a CMOS device? how large should it be?

Suppose i have an RF transistor similar to MOSFET  and the channel is something like graphene or high mobility semiconductor. If i have a current equation for this transistor, how can i create a new transistor model for this in ADS?

Although, CMOS transistor performs well up to 28nm node, the short channel effects become uncontrollable in CMOS transistor if scaled below 28 nm. In response to this issue, VLSI Industry replaced CMOS with FINFET and SOI transistor for 14 nm and 7nm technology node.However, as per research conducted, it is estimated that FINFET can be scaled up to 5 nm. Now, question arises what transistor technology industry might adopt to scale transistors below 5nm? I have listed several possible transistor topology below. Which one of the following transistor technology might bring about massive technological change in the near future?

1. Carbon Nano-Tube based FET (CNFET)

https://compoundsemiconductor.net/article/100334/InGaAs_FinFETs_For_Future_CMOS

https://ieeexplore.ieee.org/document/7412441/

https://www.nature.com/articles/s41598-018-23367-6