Zhiguo Zhao’s research while affiliated with Institute of Microelectronics, Chinese Academy of Sciences and other places

In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and the stress problem becomes more and more serious. Therefore, the low cost and low stress plasma enhanced tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP) oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAND. This paper explores the challenges in the application of PE TEOS in 3D NAND PMD oxide layer. In our experiment both PE TEOS and HDP are employed as the PMD oxide for 3D NAND staircase protection. There is not any void found in the two oxide structures. However, oxide pitting is spotted in the subsequent diluted hydrofluoric acid wet etching in the PE TEOS split. Moreover, we observe that the top silicon nitride corrodes in hot phosphoric acid. We study the mechanism of PE TEOS oxide pitting and silicon nitride corroding, propose two solutions: (1) HDP oxide + PE TEOS, and (2) PE TEOS + dry etching. Experimental results demonstrate that our solutions can well address the issue of PE TEOS oxide pitting and effectively protect the staircase structure. This work extends the application of PE TEOS oxide of which the cost and the stress are both low in 3D NAND.

3D NAND is a great architectural innovation in the field of flash memory. The staircase for control gate is a unique and important process in the manufacturing of 3D NAND. The staircase is employed to form the electrical connection between the control gate and contact. The current method used to measure the dimension of staircase patterns is, however, not precise enough for the development of state-of-the-art 3D NAND. In this circumstance, an accurate measurement of dimension for as-formed staircase patterns is of great importance and technical interest. In this paper, an improved measurement method is proposed to meet the requirement for higher precision. By taking the overlay into account, a calculation formula for measuring the dimensional error of as-formed staircase is derived for the first time. Two kinds of anchor design (convex SS0 and concave SS0) are put forward to perform dedicated experiments. Achieved results show that the measurement error of as-formed staircase using this improved method is improved from 31.6 nm for normal measurement method to 14.1 nm. The dimensional uniformity of as-formed staircase is therefore improved significantly which in turn leads to well controlled word line leakage. Furthermore, in advanced staircase structure of stair divided scheme (SDS), the convex SS0 shows an advantage in cost compared to the concave SS0.

An effective post etch treatment (PET) process was proposed to eliminate etch damage in the channel hole, of which the depth and the aspect ratio is beyond 3 μm and 30:1 respectively, prior to selective epitaxial growth (SEG) in three dimensions (3D) NAND flash memory. In this work, it is demonstrated that the damaged layer both at the channel hole bottom and sidewall induced by capacitively coupled plasma (CCP) was effectively eliminated using low energy plasma of CL2 + NF3/CH2F2 in PET, and then obtaining an excellent surface condition in channel hole and fabricating a void-free SEG epitaxial layer.

In order to optimize program disturbance characteristics effectively, a characterization approach that measures top select transistor (TSG) leakage from bit-line is proposed to quantify TSG leakage under program inhibit condition in 3D NAND flash memory. Based on this approach, the effect of Vth modulation of two-cell TSG on leakage is evaluated. By checking the dependence of leakage and corresponding program disturbance on upper and lower TSG Vth, this approach is validated. The optimal Vth pattern with high upper TSG Vth and low lower TSG Vth has been suggested for low leakage current and high boosted channel potential. It is found that upper TSG plays dominant role in preventing drain induced barrier lowering (DIBL) leakage from boosted channel to bit-line, while lower TSG assists to further suppress TSG leakage by providing smooth potential drop from dummy WL to edge of TSG, consequently suppressing trap assisted band-to-band tunneling current (BTBT) between dummy WL and TSG.

The 3D tri-gate FinFET device architecture is a key transistor scaling to 22nm node and beyond for its excellent short-channel performance[1]. However, compared with planar transistors, it poses greater challenge in the finFET gate etch.[2] As shown in fig.1, the etch needs to stop on top of the fin while etching further down to the STI oxide layer. Therefore, the top of fin needs to endure long time over etch without any structural damage which would adversely affect device performance. What’s more, the gate profile must be vertical and there should not be residual in the corner of gate and fin. It is not an easy task to achieve, at the same time, the three goals of vertical gate profile, no residual in the corner of fin and gate, as well as no structure damage on the top of fin, due to an unavoidable tradeoff. More specifically, vertical gate profile and no residual in the corner of fin demand strong etch function and light polymer, while no structure damage in the top of fin requires weak etch function and heavy polymer, which points to high etch selectivity of silicon to oxide layer. To achieve good etch results, one often falls into this dilemma. As far as we know, few publicly available papers have provided satisfactory solutions to the above- mentioned problem. In this work, we deal with it. The process of gate stack with CD below 30nm is illustrated in fig.2. Then, a HBr/O2 process in transformer coupled plasma is applied to finFET gate etch. As shown in fig.3, gate profile is vertical, fin is well protected and no residual appears in the corner fin. In conclusion, an HBr/O2 plasma etch process of finFET gate with CD below 30nm is investigated.Through appropriate tradeoff , an etch result of vertical gate profile, no residual in the sidewall and corner of fin, no structure damage on the top of fin is achieved.

FinFETs with 20nm BEOL with one generation improvement in performance and power efficiency has announced for mass production by leading IC companies. The processing details, however, have never been reported. In this talk, processing challenges of CMOS integration of FinFETs with all-last gate stacks is presented based on our recent results. Special processing issues in Fin and the replacement gate (RMG) formation, RMG filling with high-k/metal gate and self-aligned contact (SAC) module will be discussed. It is found that the etching of dummy gate of FinFETs behaves differently from that in planar MOSFETs. Thick enough dummy SiO 2 is needed for protecting the Fin from plasma damage during dummy gate etch. Wet removal of dummy SiO 2 in gate area faces also the risk of Fin damage, due to galvanic corrosion, and thus prefers to a thin SiO 2 for control of the wet processing window. It is shown that TaN coverage of the channel area is important in single dielectric dual metal gate stack, where a p-FET stack is first deposited in both n- and p-area, and then the top work function metals in n-area will be removed before n-FET metal deposition. ALD TaN is studied systematically for the the etch stopper application. It is found that the largest issue in the CMOS integration of the FinFETS is n-work function metal deposition. Poor TiAl coverage induces large Vt variation. ALD TiAl could be a good solution for n-work function metal deposition. Filling of the RMG, which has extremely large AR in FinFETs, and SAC is a big challenge. A systematic study of ALD W shows that its advantage in properties such as adhesion, conformality and good constraint by TiN barrier enables good fill of the gaps. Electrical characterizations of the FinFETs are presented in order to show the impact of the above issues to device behavior variation.