Z. Pfeffer’s research while affiliated with University of Colorado and other places

IBM's autonomic computing initiative seeks to create self reliant IT systems, but autonomic properties can also be applied to tower layers of computing. This paper reviews a new autonomic CPU design intended to integrate into an embedded autonomic system. The CPU is made up of "Cogs" which intemperate to carry out computation. Code written for a Cog computer simulator is presented that demonstrates core Cog features. A review of this first machine concludes the paper.

Autonomic computing is a set of new architectural goals envisioned by IBM and inspired by the human autonomic system. Autonomic architecture is intended to avoid a management crisis that looms based upon the success of Moore's law. If we continue to increase storage, memory, processing and 10 resources at present rates and manage them the way we have, IBM projects a system administration crisis. The proposed autonomic architecture has four goals for systems: self configuring, self-healing, self-optimizing, and self-protecting. In this paper, we examine how autonomic architecture goals apply to real-time embedded systems rather than the enterprise systems that IBM has focused upon.

In this paper we describe a VLSI implementation and complete circuit design of a fast ternary CAM (TCAM). TCAMs are commonly used to perform routing lookups in the backbone of IP networks and small gateways. Our TCAM is designed to have a greater capacity and speed than any commercial offering at this time. In contrast with existing TCAM approaches, our TCAM allows complete flexibility in the location where any new entry is inserted. This is achieved by a novel longest prefix match (LPM) determination circuit, whose delay increases logarithmically with the number of bits to be looked up. We have implemented our TCAM with 512 bits of prefix entry with 512 bits of destination information, allowing it to implement large address lookups as well as quality of service mechanisms. This would make our TCAM design particularly suitable for IPv6 routing lookup applications. The speed improvement of our TCAM over currently available TCAMs results from various carefully selected VLSI architectural and implementation choices. The TCAM size is 21 Mb and is broken up into a regular grid of 13x13 smaller TCAM blocks for improved speed characteristics. Routing lookup operations use a heavily pipelined approach for maximum throughput, while ensuring a lookup latency of 3 clock cycles. Individual match lines in these blocks are split into 4 sections to reduce RC delay in the lookup process. Our LPM determination circuit is implemented using an efficient wired-NOR circuit for further reduced delay. Sense amplifiers are utilized in the LPM and SRAM sections of the TCAM and are located in the center of each TCAM subblock in order to improve lookup speed. We have implemented and validated our design using state-of-the-art circuit analysis and design tools. We have also generated mask layouts of the entire TCAM design using current layout tools. The complete TCAM circuit design is approximately 18mm on a side, with a total capacity of 21Mb. Our TCAM has an ability to perform routing lookups at a line rate of 76.8Gb/s which is twice as fast as the fastest commercially available TCAM today.

In this paper I describe an implementation of a 5-bit folding and interpolating analog to digital converter (FI-ADC). A FI-ADC is used to perform analog to digital conversions in as few clock cycles as possible. The implemented FI-ADC was a major block in a larger chip. The larger chip provided analog to digital (ADC) and digital to analog (DAC) capabilities for a PC parallel port configured in standard parallel port (SPP) mode. The chip was not fabricated. The chip was designed in a 0.35 um CMOS process from Austriamicrosystems. It was designed, simulated and laid out with Cadence design tools, specifically: IC 4.4.6 (custom IC design), LDV 3.4 (digital design & verification), SPR 4.0 (digital synthesis) and Virtuoso XL 4.4.6 (layout). A post layout simulation was not performed. The specifications for the 5 bit FI-ADC were: an input range of 0 to 1.8 V (Vref), a conversion rate of 2 million samples per sec, a 200 kHz bandwidth on the input and less than 1 least significant bit (LSB) for the integral non-linearity (INL) and differential non-linearity (DNL). All specifications were met or exceeded. The maximum INL was 0.62 and the maximum DNL was 0.30. The sampling rate could be set as high as 3 million samples per second and signals with frequency components of up to 200 kHz were passed through simulation without significant distortion.

The purpose of this paper is to detail our investigation of issues involved in clock and data recovery associated with a high speed serializer-deserializer (SERDES) receiver block. Because of the over-all complexity of such a block, the approach that was taken was to start at a high level of abstraction, gain a general understanding at that level, then choose one of the more interesting sub-blocks and investigate this block at the next level of detail.