Yu Zhang’s research while affiliated with Institute of Microelectronics, Chinese Academy of Sciences and other places

An effective post etch treatment (PET) process was proposed to eliminate etch damage in the channel hole, of which the depth and the aspect ratio is beyond 3 μm and 30:1 respectively, prior to selective epitaxial growth (SEG) in three dimensions (3D) NAND flash memory. In this work, it is demonstrated that the damaged layer both at the channel hole bottom and sidewall induced by capacitively coupled plasma (CCP) was effectively eliminated using low energy plasma of CL2 + NF3/CH2F2 in PET, and then obtaining an excellent surface condition in channel hole and fabricating a void-free SEG epitaxial layer.

In this study, the wafer warpage resulting from common source line tungsten (CSL W) is investigated in 3D NAND flash memory. It is found that the warpage is related to the annealing conditions after CSL W deposition, and it reduces exponentially with increasing annealing temperature or linearly with increasing annealing time. This result shows that the effect of annealing temperature on warpage is greater than that of time. Consequently, spike annealing with a low thermal budget is proposed to achieve the desired reduction of warpage as long as the annealing temperature is adequate. This work provides an effective approach to solve the wafer warpage problem in 3D NAND flash memory manufacturing.

The impact of temperature on array Vth distribution was investigated in 3D NAND flash. Cell Vth distributions were obtained under different program and read temperature splits. After the page is programmed under high temperature, it is found that the high tail of Vth distribution exhibits a larger shift than the low tail, during read at different temperatures (85°C and –25°C). On the contrary, the low tail of Vth distribution shows a larger shift than the high tail during cross temperature read, after the page programmed under low temperature. The temperature coefficient (Tco) of cell Vth shows cell to cell variations, which can be categorized into two types. For type 1, the Tco is correlated with the selected cell Vth due to polysilicon channel; For type 2, the Tco is independent of the selected cell Vth. The corresponding impacts on Vth distribution are studied via array Monte Carlo simulation. Based on the simulation results, the above temperature dependent observations can be well modeled by the combination of both Tco variation type 1 and 2. Furthermore, two optimization approaches are proposed to alleviate the Vth distribution broadening and are validated by experiments.

The electrical characteristics of top select gate transistor (TSG) has been investigated in vertical channel three dimensional NAND flash memory. TSG shows wider initial Vth distribution as compared with memory cells, and even worse after erase. By experimental analysis and TCAD simulation, a physical model based on grain boundary (GB) interface traps is proposed to explain the mechanism. Grain boundary traps in offset region between bit line contact and TSG can induce a higher local potential barrier in channel, which results in higher TSG initial Vth. Besides, random GB position within offset region, leads to worse variation of TSG initial Vth. Furthermore, the local potential barrier in offset region of TSG cannot be reduced by erase operation, leading to worse Vth distribution after erase. According to proposed model, two methods with optimization of offset doping energy and poly-Si GB trap passivation condition are proposed to achieve tight distribution and improved erase uniformity.

In this work, the GAA (Gate All Around) L-Shaped bottom select transistor (BSG) in 3D NAND Flash Memory has been investigated. Different methods are proposed to optimize its performance from viewpoints of process and structure. BSG in 3D NAND is a novel device structure with two connected transistors: one is horizontal MOSFET (regarded as convention MOSFET) and one is vertical MOSFET (regarded as GAA transistor). With implant dose increasing in vertical channel, BSG Vth has much more tighter Vt distribution, which is beneficial for boosting potential improvement and program disturbance suppression. Meanwhile, BSG corner rounding is proposed to improve the characteristic of BSG. Experiment and TCAD simulation data are matches quite well, giving a way to improve cell characteristics distribution and self-boosting potential control in high density 3D NAND array.

A new program scheme using an “erase-like” waveform for precharge operation is proposed for program disturbance optimization in 3-D vertical channel flash memories. With the proposed scheme, the effect of precharge operation, which is followed by program operation, on the initial unselected channel is enhanced by charging additional holes from p-type well. Consequently, boosting efficiency and boosting potential of unselected string are promoted, leading to a significant suppressed program disturbance, and the V _pass window can be enlarged notably as well. Meanwhile, the timing requirement of the proposed scheme is evaluated. The advantage of the erase assisted precharge scheme has been demonstrated by TCAD simulation and measurement in mini-array test-key device.

The disturbance mechanism of dummy cell during memory cell cycling has been investigated in 3D NAND flash. Edge dummy cell (DMY) threshold voltage (Vt) increasing was observed during cell program and erase cycling, which leads to a reduced string current and read failure. According to experiment and TCAD analysis, two mechanisms were identified to contribute to the dummy disturbance: one is the tunneling of electrons from the adjacent gate to the trapping layer during cell erase condition, which was also observed in 2D NAND; the other one is the lateral charge spreading from the trapping layer of edge cell to DMY, which is new observation for the junction-less 3D NAND with continuous nitride trapping layer. Furthermore, an optimal DMY bias scheme under erase operation is demonstrated to suppress the disturbance.

In order to optimize program disturbance characteristics effectively, a characterization approach that measures top select transistor (TSG) leakage from bit-line is proposed to quantify TSG leakage under program inhibit condition in 3D NAND flash memory. Based on this approach, the effect of Vth modulation of two-cell TSG on leakage is evaluated. By checking the dependence of leakage and corresponding program disturbance on upper and lower TSG Vth, this approach is validated. The optimal Vth pattern with high upper TSG Vth and low lower TSG Vth has been suggested for low leakage current and high boosted channel potential. It is found that upper TSG plays dominant role in preventing drain induced barrier lowering (DIBL) leakage from boosted channel to bit-line, while lower TSG assists to further suppress TSG leakage by providing smooth potential drop from dummy WL to edge of TSG, consequently suppressing trap assisted band-to-band tunneling current (BTBT) between dummy WL and TSG.

A new read scheme is proposed to suppress read disturbance in unselected strings of three dimensional (3D) vertical channel flash memories. This new scheme decreases the channel potential difference between select word-line (WL) and adjacent WL by more than 20% and the read disturb due to hot carrier injection in adjacent WL of selected WL is suppressed effectively by about 95%. Meanwhile, boosted channel potential during read operation has been preserved to improve soft programming read disturbance by more than 85% in non-adjacent unselected memory cells, owing to the reduced electric field across tunnel oxide. Compared to conventional scheme, the proposed scheme leads to a significant improvement in read disturbance characteristics with a shorter read period as well as a simplified waveform of read operation.