Yu-Cheng Peng’s research while affiliated with National United University and other places

This paper presents the novel multi-bit bitwise adaptive embedding algorithms for data hiding. These embedding algorithms can embed multi-bit (k-bit, k ≥ 1 ) secret data into cover data only introduce minimum embedding error smaller than (2k-1-1)2i-k according to the embedding location i. To achieve such a goal, the proposed embedding algorithm adaptively evaluates the most similar value to replace the original one and which can be divided into three steps: (1) embed logo data into cover data, (2) adaptively adjust the least-significant bits (LSBs) of cover data, and (3) adaptively adjust the maximum-significant bits (MSBs) of cover data. The proposed embedding algorithms are not only achieving minimum error but also suitable to hardware implementation due to it is based on logic, algebraic, and bit operations. Many simulations show that the proposed embedding algorithms perform good embedding quality for watermarking and steganography applications.

This paper presents an novel bitwise minimum error replacement (MER) technique for data hiding. Such a bitwise MER can embed k-bit (k ≥ 1) secret data into cover data only introduce minimum embedding error smaller than (2k-1 - 1)2i-k according to the embedding location i. To achieve the goal of MER, we develop novel multi-bit bitwise 3-step MER algorithms to adaptively evaluate the most similar value to replace the original one, which consist of three steps: (1) embed logo data into cover data, (2) adjust the least-significant bits (LSBs) of cover data, and (3) adjust the maximum-significant bits (MSBs) of cover data. Reason that we called these multi-bit MER algorithms are "bitwise" is that data replacements are based on the logic and algebraic bit operations to achieve minimum error. Many simulations show that the proposed MER performs good embedding quality for watermarking and steganography applications.

This paper presents the architecture design of a high efficient and non-memory Advanced Encryption Standard (AES) crypto core to fit WPAN security requirement. The proposed basis transformation approach from Galois Field (28) to Galois Field GF(((22)2)2) can significantly reduce the hardware complexity of the SubBytes Transformation (S-box). Besides, the on-the-fly key expansion function is used to replace the RAM-based, and the new on-the-fly key scheduler fully supports AES-128, AES-192 and AES-256. Moreover, resource-sharing scheme will also be employed to reduce the hardware complexity of the cipher and decipher. Experiment results show that the AES core works at 100 MHz clock it takes about 400 ns and 770 ns to complete an AES-128 encryption and decryption, respectively. That is, the corresponding throughputs are 320 Mbps and 166 Mbps. The hardware cost of the AES design is about 16.4 K logic cells with 3-in-1 key scheduler included. Experiment results also show that the proposed design is suitable for integration into the WPAN system chips due to its acceptable power dissipation.