Yasunari Suzuki's research while affiliated with NTT DATA Corporation and other places

... For example, while Shor's algorithm for factoring is not a near-term algorithm, recently a VHQCA for factoring was introduced potentially making factoring nearer term [19]. Other VHQCAs have been proposed for chemistry [20][21][22][23], simulation [24][25][26][27][28], data compression [29], state diagonalization [30][31][32], compiling [33,34], quantum foundations [35], fidelity estimation [36], and metrology [37]. ...

... It is important to emphasize once again that faulttolerant and quantum repeater technologies, which protect the data of quantum information and quantum communication, are essential for the correct and safe execution of quantum information processing [22]. There are many unexplored areas of architectures for fault-tolerant processing in quantum information processing, and breakthroughs are expected through future research. ...

... (3) Development of advanced technologies for the future to support security R&D As a security Center of Excellence, develop basic technologies for the future such as cryptography and information theory and quantum information security technology [5]. ...

... Furthermore, our efforts have revealed that the existing quantum stack is severely limited in supporting new applications like ours. Existing research is heavily focused on features and devices close to hardware such as error mitigation [24,25,26] and reliability [27,28,29,30,31,32], circuit synthesis [33,34], and microarchitecture [35]. There is a lack of research targeting usability and higher-level organization, which is restricting the potential of these systems. ...

... We accomplish these by employing an information-theoretic approach, which establishes the novel connection between the state distinguishability and operationally motivated errormitigation performance measures. Our results place the fundamental limitations imposed on the capability of general error-mitigation strategies that include existing protocols [5][6][7][8][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] and the ones yet to be discovered, being analogous to the performance converse bounds established in several other disciplines-such as thermodynamics [32][33][34], quantum communication [35,36], and quantum resource theories [37,38]-that contributed to characterizing the ultimate operational capability allowed in each physical setting. ...

... In the context of entanglement-induced barren plateaus, most strategies rely on limiting the amount of entanglement [16][17][18][19][20]. Other methods make use of tailored distributions of the initial circuit parameters and carefully designed circuit architectures [21][22][23][24][25][26][27][28][29]. Yet, only a handful of configurations offer trainability guarantees and robustness against barren plateaus [30,31]. ...

... Since the widespread transmons pose the tightest constraints, the value of 1 µs is often used as the benchmark for real-time decoding. However, this could be relaxed to a few µs with the use of parallelization [17,18] or trading time for space with the use of Auto-T gadgets (see figure 17(b) in [19]), where the use of an extra ancilla per T gate allows to postpone the moment when the output of the Comparison of decoders: summary of decoders for a distance-11 surface code (unless otherwise specified) [25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40]. For the cases that do not account for measurement errors, the decoding time is given for a d × d × 1 block, whereas for those that do is given as 1/d of the time to decode a d × d × d block. ...

... In Sec. III, we discuss the conventional probabilistic error cancellation technique [26][27][28][29][30][31][32][33][34][35], developed to fully mitigate noise in a quantum circuit, and demonstrate that it can also be employed to partially mitigate the error probabilities of stochastic Pauli noise channels in a controlled manner. We show that our approach can be used to implement stochastic Pauli noise with desired decoherence rates on NISQ devices. ...

... To meet the timing requirements, the clock period should be equal to 5.6 m/2 =0.025ns, which is a maximum clock frequency of 40GHz. This frequency cannot be achieved by any FPGA or ASIC, and on the other hand, it would require a large power consumption that will cause another problem with the power budget and the refrigeration system [13]. With the previous examples, it is easy to conclude that the implementation of serial scheduling, even if it has a better performance than the flooded one, it is not a realistic solution when it comes to implementation. ...

... Finally, all the calculations performed in this paper have been done on the quantum emulator Qulacs [44] as state vector emulations. ...