Yasuhiro Sugimoto’s research while affiliated with Chuo University and other places

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Publications (39)


Q Controllable Antenna as a Potential Means for Wide-Area Sensing and Communication in Wireless Charging via Coupled Magnetic Resonances
  • Article

January 2016

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76 Reads

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22 Citations

IEEE Transactions on Power Electronics

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Masato Namiki

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Yasuhiro Sugimoto

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Hideki Hashimoto

Recently, wireless charging via coupled magnetic resonances gains attention because it has a potential of efficient mid-range wireless charging. Here, functions such as sensing at the transmitter and wireless communication from the target are the essential elements to realize the standard wireless charging system. Currently, the sensing and communication protocol of hardware (i.e., high-frequency power source and antenna configuration) compatible with wireless charging is gaining attention in terms of cost and space reduction due to the use of common components in multiple functions. However, these protocols have the problem of narrow effective areas. Therefore, this paper presents a method for wide-area sensing and communication with slight modification of the configuration. The basic concept is to expand the effective area related to antenna Q factor by using the Q controllable antenna acting as though the Q factor increased. The underlying theory was described with electric circuit theory. The experimental results showed that the Q factor can be increased until the resonance collapses, and the increase of Q factor has the potential to widen the effective area of sensing and communication.


A fast and precise circuit simulation method for switching power converters using a mixture of circuits and behavioral models

February 2015

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26 Reads

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4 Citations

We propose a fast and precise simulation method for replicating the transient responses and frequency characteristics of switching power converters using a mixture of real circuits and behavioral models. The method used a behavioral simulation tool (Verilog-A), which was supported by an analog simulator such as SPECTRE®. The time-step became variable, however, the nonlinear operation of the circuit was considered and state-space equations were formulated by applying the hybrid-dynamical-system control scheme in behavioral modeling [1]. Each macro block can have either the real schematic and behavioral model. The transient simulation operates in such a way that the analog simulator advances the simulation step by step while obtaining results from behavioral blocks. Further application of the periodic steady state (PSS) and periodic stability (PSTB) analyses, allowed us to obtain the frequency characteristics in short time. For verification, we simulated the circuits of the current-mode buck DC-DC converter IC, which was previously fabricated using a 0.18-um CMOS process. When we chose blocks of a buffer, the switching and output circuits and RS-FF real transistor circuits, while the rest behavioral models, we achieved transient response and frequency characteristics that were 13 and 75 times faster, respectively, than the analog simulator alone, while keeping less than 3.9% and 2.5% of errors compared with IC's evaluation results.


Feedback Loop Analysis and Optimized Compensation Slope of the Current-Mode Buck DC-DC Converter in DCM

January 2015

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81 Reads

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17 Citations

IEEE Transactions on Circuits and Systems I Regular Papers

Frequency characteristics of the total feedback loop of a current-mode buck DC-DC converter in the discontinuous conduction mode (DCM) are examined by formulating an equivalent small-signal transfer function using a proposed block structure that does not suffer direct influence from the current feedback. Utilizing this transfer function, it is clarified that the type of the compensation slope in a current feedback loop affects the loop frequency characteristics in DCM, and in terms of stability, high voltage gain and large 0-dB frequency bandwidth, the quadratic compensation slope is more effective than the linear compensation slope. The validity of the proposed block structure and formulations and the effectiveness of applying a quadratic compensation slope instead of a linear compensation slope in DCM are verified by comparing calculation results, SPICE simulation results and evaluation results using circuit and measurement data from an MOS current-mode buck DC-DC converter IC that had been previously fabricated. More than 10-dB higher voltage gain, three times larger 0-dB frequency bandwidth, more than 10-degree larger phase margin and faster recovery time in load current change are realizable in DCM compared with the case using a linear compensation slope.


Circuit techniques to enhance linearity and intrinsic gain to realize a 1.2 V, 200 MHz, +10.3 dBm IIP3 and 7th-Order LPF in a 65 nm CMOS

June 2013

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8 Reads

IEICE Transactions on Electronics

Circuit techniques to enhance the linearity of input-voltage-to-current (V/I) conversion and to increase the output impedance of a current source by compensating for the low intrinsic gain of a transistor were introduced to realize a high-frequency operational transconductance amplifier (OTA) for a low supply voltage using sub-100-nm CMOS processes. Applying these techniques, a MOS 7th-order Gm-C linear-phase low-pass filter (LPF) was realized using a 65 nm CMOS process. A simplified biquad LPF that can serve as a component of a 7th-order LPF was newly developed by replacing OTAs with resistors. As a result, the -3 dB frequency bandwidth, group delay ripple, 3rd-order distortion, and 3rd-order input intercept point (IIP3) were 200 MHz, 2.2%, ≤ -55 dB with a 100 MHz input, and +10.3 dBm, respectively, all with a ±0.1 Vp-p input signal at each input terminal in the pseudodifferential configuration. The LPF including an output buffer dissipated 60 mW in the case of a 1.2 V supply. Wide spurious-free dynamic range (SFDR) characteristics were confirmed up to high frequencies. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.


A Precision and High-Speed Behavioral Simulation Method for Transient Response and Frequency Characteristics of Switching Converters

June 2012

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37 Reads

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1 Citation

IEICE Transactions on Electronics

We propose a fast and precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the nonlinear formula based on the circuit operation and by applying feedback. To assess the accuracy and simulation time of the proposed simulation method, we designed current-mode buck and boost converters and fabricated them using a 0.18-µm high-voltage CMOS process. The comparison in the transient response and frequency characteristics among SPICE, the proposed program on a behavioral simulation tool which we named NSTVR (New Simulation Tool for Voltage Regulators) and experiments of fabricated IC chips showed good agreement, while NSTVR was more than 22 times faster in transient response and 85 times faster in frequency characteristics than SPICE in CPU time in a boost converter simulation.


A low-voltage and stable phase compensation technique to realize an 99 dB, 650 MHz and 1.8 V three-stage Amplifier

May 2012

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25 Reads

A 1.8-V operational 3-stage Amplifier with a 99 dB of voltage gain, a 650 MHz of the unity-gain frequency bandwidth and 54 degrees of phase margin is realized. It has two pairs of a resistor and a capacitor in series as feedback elements and a feed-forward transconductance amplifier to perform threefold phase compensation. In order to apply this threefold phase compensation scheme to realize a high gain and high frequency 3-stage amplifier with enough phase margin, the small signal equivalent circuit model with stray capacitors at the output of each stage of amplifier is newly developed and the small signal transfer function including those stray capacitors are formulated. The transfer function is factorized into poles and zeros so that their relationship and influence on the frequency characteristics can be examined. The 3-stage amplifier is actually circuit designed by using 0.18μm CMOS devices. The calculated gain and phase frequency characteristics from our equivalent circuit model with stray capacitors have agreed very well with SPICE simulation results of the actual circuit especially at high frequencies above 1 GHz.


A Current-Mode Buck DC-DC Converter with Frequency Characteristics Independent of Input and Output Voltages Using a Quadratic Compensation Slope

April 2012

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32 Reads

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3 Citations

IEICE Transactions on Electronics

By using a quadratic compensation slope, a CMOS current-mode buck DC-DC converter with constant frequency characteristics over wide input and output voltage ranges has been developed. The use of a quadratic slope instead of a conventional linear slope makes both the damping factor in the transfer function and the frequency bandwidth of the current feedback loop independent of the converter's output voltage settings. When the coefficient of the quadratic slope is chosen to be dependent on the input voltage settings, the damping factor in the transfer function and the frequency bandwidth of the current feedback loop both become independent of the input voltage settings. Thus, both the input and output voltage dependences in the current feedback loop are eliminated, the frequency characteristics become constant, and the frequency bandwidth is maximized. To verify the effectiveness of a quadratic compensation slope with a coefficient that is dependent on the input voltage in a buck DC-DC converter, we fabricated a test chip using a 0.18µm high-voltage CMOS process. The evaluation results show that the frequency characteristics of both the total feedback loop and the current feedback loop are constant even when the input and output voltages are changed from 2.5V to 7V and from 0.5V to 5.6V, respectively, using a 3MHz clock.


A MOS current-mode boost DC-DC converter with the duty-ratio-independent frequency characteristics

November 2011

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17 Reads

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3 Citations

In order to elevate an input voltage of less than 1-V to an output voltage of from several volts to 10-V while also realizing a large output-current capability, a wide feedback-loop frequency bandwidth under a high duty-ratio condition and a high power efficiency, we developed a MOS current-mode boost DC-DC converter which utilizes the quadratic compensation slope with the output voltage dependency and the variable gain amplifier in front of the error amplifier. The frequency characteristics of the total feedback loop were independent of the duty-ratio change. A test chip was fabricated by using a 0.18-um high-voltage CMOS process. The resulting 1 MHz operational MOS current-mode boost DC-DC converter converted input voltages of 0.4-V to 5.3-V to output voltages of 1-V to 6-V, realized 50 mA and 150 mA of output currents for input voltages of 1-V and 1.8-V, respectively, realized a feedback-loop frequency bandwidth of 70 kHz with a 1-V input and a duty-ratio of 81%, and realized 75% and 90% power efficiency for the 1-V and 2.5-V inputs, respectively, when the output voltage was 5.3 V.


Linearity and intrinsic gain enhancement techniques using positive feedbacks to realize a 1.2-V, 200-MHz, +10.3-dBm of IIP3 and 7th-order LPF in a 65-nm CMOS

September 2011

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18 Reads

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2 Citations

Linearity and intrinsic gain enhancement tech- niques for realizing high-performance and low-voltage analog circuits in a deep-submicron CMOS are introduced. In place of a differential amplifier for the voltage-to-current (V/I) conversion at the input, a V/I conversion using a linear resistor and a positive feedback in a pseudo-differential configuration was adopted. The positive feedback concept was also applied to enhance the intrinsic gain of the deep-submicron MOS transistor which is used as a current source to realize high output impedance in amplifiers. In order to verify the effectiveness of the proposed techniques, a MOS 7th-order Gm-C linear phase low-pass-filter (LPF) was realized using a 65-nm CMOS process. Evaluation results showed that the -3 dB frequency bandwidth, group delay ripple, 3rd-order distortion and 3rd-order input intercept point (IIP3) were 200 MHz, 2.2%, less than -55 dB with a 100-MHz input and +10.3 dBm, respectively, all with a §0.1 Vp-p signal input at each input terminal in pseudo differential configuration, while the LPF including an output buffer dissipated 60 mW from a 1.2-V supply.


Accurate, high-speed simulation of transient response and frequency characteristics of switching converters

January 2011

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28 Reads

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1 Citation

This paper proposes a fast, precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool (MATLAB/Simulink) without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the formula based on the circuit operation and by applying feedback. The transient response and frequency characteristics of a current-mode boost DC-DC converter and a charge pump that were designed using a 0.18-um CMOS process were simulated by SPICE and the proposed program on a behavioral simulation tool, which we named NSTVR (New Simulation Tool for Voltage Regulators). Simulation results showed good agreement, yet NSTVR was more than 85 times faster than SPICE in CPU time in calculating frequency characteristics of a current-mode boost DC-DC converter.


Citations (21)


... In 2012, Japanese car manufacturer Nissan Group announced the addition of wireless charging equipment in Leaf models, and changed the equipment to adopt electromagnetic induction wireless charging. There are two forms of charging, one is to install the device in the form of a charging pile on both sides of the parking lot, the other is to bury the device in the ground, as long as the vehicle enters the range of wireless charging equipment, you can charge yourself, while the car is also equipped with a control button, you can choose whether to charge, this device will not be affected by the weather [25][26][27]. In 2014, Toyota Motor Manufacturing Company pioneered the use of electric magnetic resonance technology for charging electric vehicles, deploying charging coils both beneath and atop parking lots during their experimentation phase. ...

Reference:

Application of wireless energy delivery system in automobile charging
Q Controllable Antenna as a Potential Means for Wide-Area Sensing and Communication in Wireless Charging via Coupled Magnetic Resonances
  • Citing Article
  • January 2016

IEEE Transactions on Power Electronics

... This is in turn well-aligned with other works, e.g. switched power converters, which look for different analysis and design methodologies [8,9] for fast and still accurate circuit behavior evaluation. The use of either Verilog-A or AMS or a mixed approach of these system level hardware description languages with electrical netlists is also often observed [9,10] and was chosen for this work. ...

A fast and precise circuit simulation method for switching power converters using a mixture of circuits and behavioral models
  • Citing Article
  • February 2015

... Another key difference is that our continuous-time model considers the amplifier's voltage gain and the time delay during operation in a hysteresis comparator, accounting for the slew rate at its input. In contrast, the comparator in reference [18] is characterized by the ratio ∆ /∆ , as found in equation (20) of the reference, where ∆ represents the variation in the duty cycle and ∆ represents the variation in reference voltage. This ratio is determined solely by the slope of , which depends only on the values of , and , without considering the role of the amplifier. ...

Feedback Loop Analysis and Optimized Compensation Slope of the Current-Mode Buck DC-DC Converter in DCM
  • Citing Article
  • January 2015

IEEE Transactions on Circuits and Systems I Regular Papers

... Veröffentlichungen, welche mögliche Umsetzungen dieser ersten Stufe behandeln, sind in Abbildung 2.5a dargestellt. Von den abgebildeten 72 Einträgen sind 20 als Abwärtswandler [102, 106, 112-114, 117, 120, 121, 131, 134, 136, 145, 153, 154, 157, 161, 163, 164, 195, 196], 18 als Aufwärtswandler [123,124,127,130,132,135,140,141,144,146,147,149,151,152,155,158,159,166], vier mit einer switched-capacitor-Topologie [101,111,115,122], drei als invertierender Wandler [143,168,196], drei als Multi-Level-Topologie [100,109,118] und zwei als SEPIC [150,160] 10 20 30 [269,270]. ...

A MOS current-mode boost DC-DC converter with the duty-ratio-independent frequency characteristics
  • Citing Conference Paper
  • November 2011

... However, it is usually difficult to achieve the operation of ring VCOs at the high frequencies required today. To overcome these difficulties it has been proposed several topologies [1]- [3], nevertheless, the power dissipation is critical in the most of the cases. In this paper a new ring VCO of two stages is proposed, which uses partial positive feedback in its delay cell, allowing that the circuit to work in high speed and dissipate little power. ...

A 2 V, 500 MHz and 3 V, 920 MHz Low-Power Current-Mode 0.6 µm CMOS VCO Circuit
  • Citing Article
  • July 1999

IEICE Transactions on Electronics

... Current mirror is usually used as input stage because of low input impedance, the simple current mirror has many problems such as input offset and output offset due to finite impedance [14], the input offest is calculated using the following equation, and its circuit diagram is shown in Fig. 1a. ...

A 35MS/s and 2V/2.5V Current-mode Sample-and-Hold Circuit with an Input Current Linearization Technique
  • Citing Conference Paper
  • December 2005

... For power converters with peak current control, quadratic slope compensation (QSC) method can increase the stable operational region compared with the conventional linear ramp compensation (LRC) [37,38]. Fig. 7 (a) presents the diagram of the control algorithm for boost converter with CPL, where voltage feedback peak current control with proportional-integral (PI) and QSC method is applied. ...

Design of a current-mode, MOS, DC-DC buck converter with a quadratic slope compensation scheme
  • Citing Conference Paper
  • September 2005

... Although ADCs have been designed using floating gates including sigma-delta and flash converters282930, a voltage-mode pipelined implementation that uses floating gates in order to trim offsets for accuracy was designed. The floating-gate biases allow the power consumption, area, and complexity of the pipelined stage to be greatly reduced when compared to other pipelined architectures that use other calibration techniques313233 . Although the architecture of the ADC, shown inFigure 7.1, can be easily extended to as many bits as needed, a 10-bit converter was designed and built. ...

The Realization of a Mismatch-free and 1.5-bit Over-sampling Pipelined ADC
  • Citing Conference Paper
  • June 2005

... bandwidth to BW = 53.1 MHz, hysteresis = 10 mV, and R-latch time constant R L ·C L = 2 ns. However, since the comparator offset will be noise-shaped by the loop filter, it will not critically degrade the modulator performance, thus the modulator can tolerate a large offset [25]. As a result, the most critical non-idealities that are pre-amp. ...

Design of a 1-V Operational Passive Sigma-Delta Modulator
  • Citing Conference Paper
  • September 2009

... In [19], the fast method of estimation of transient response and frequency characteristics of switching converters is proposed. In the simulations performed with the use of MATLAB-Simulink, the nonlinearities of elements of the considered circuit were taken into account. ...

Accurate, high-speed simulation of transient response and frequency characteristics of switching converters
  • Citing Conference Paper
  • January 2011