Wu Xiaobo’s research while affiliated with Zhejiang University and other places

This paper presents a low-power high-precision switched-opamp(SO)-based delta—sigma (ΔΣ) analog-to-digital converter (ADC). The proposed SO design allows circuit operation at sub-1 V supply voltage, only needs to work in half of a clock cycle, and thus is suitable for low power applications. In addition, an opamp-sharing technique is applied to save on hardware overheads. Due to the use of a dual cycle shift data weighted averaging (DCS-DWA) technique, mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones. The proposed ADC has been implemented in a standard 0.18 μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth. The power consumption is 58 μW for the modulator at 0.9 V supply voltage and 96 μW for the decimation filter, which translate to the figure-of-merit (FOM) of 35.4 fJ/step for the solo modulator, and 94 fJ/step for the whole system.

An analog implementation of a novel fixed-frequency quasi-sliding-mode controller for single-inductor dual-output (SIDO) buck converter in pseudo-continuous conduction mode (PCCM) with a self-adaptive freewheeling current level (SFCL) is presented. Both small and large signal variations around the operation point are considered to achieve better transient response so as to reduce the cross-regulation of this SIDO buck converter. Moreover, an internal integral loop is added to suppress the steady-state regulation error introduced by conventional PWM-based sliding mode controllers. Instead of keeping it as a constant value, the free-wheeling current level varies according to the load condition to maintain high power efficiency and less cross-regulation at the same time. To verify the feasibility of the proposed controller, an SIDO buck converter with two regulated output voltages, 1.8 V and 3.3 V, is designed and fabricated in HEJIAN 0.35 μm CMOS process. Simulation and experiment results show that the transient time of this SIDO buck converter drops to 10 μs while the cross-regulation is reduced to 0.057 mV/mA, when its first load changes from 50 to 100 mA.

This study examines factors that determine the propensity of product innovation of entrepreneurial firms in ICT sector. These factors include R&D, founding team characteristics, education level of employees, environment, networking activities, adaptability to customer needs, and environment. Our Logit model shows that except environment, all of these variables have direct significant effects on product innovation in new ICT firms. But environment affects product innovation by interacting with adaptability to customer needs. Among them, education level of employees plays the most important role.

Manufacturing industry is playing a more and more important role in China's economic booming. As the globalizing of manufacturing industry goes further, the thinking of catching up with developed countries is changing dramatically . Globalization brings about both chances and threats to China's manufacturing enterprise. While technology Acquisition (TA) is the most important channel to advance enterprise's technology and accumulate capabilities, TA is adopted as the key way to shorten the technological gap between China and developed countries. However, the actual performance of TA in China, at enterprises level, is not so satisfying. To evaluate the factors affecting the performance of TA is a significant work for us to do. Based on related theories and a questionnaire study on China's TA performance, deploying statistics method, this paper analyses the factors affecting TA effects. And based on the study, a tentative model of factors affecting TA is proposed, which gives an alternative reference for China's enterprises to improve their thinking about TA performance and which could also be used as a tool for them to implementing their technology strategy.

The mining loss rate and dilution rate are the key indicators for the mining technology and management level of mining enterprises. Aiming at the practical problems such as the large workload but inaccurate data of the traditional loss and dilution calculation method, this thesis introduces the operating principle and process of calculating the loss rate and dilution rate at the mining fields by adopting geological models. As an example, authors establishes 3D models of orebody units in the exhausted area and mining fields in Yangshu Gold Mine in Liaoning Province, and conduct Boolean calculation among the models to obtain the calculation parameters of loss and dilution, and thereby calculate out the dilution rate and loss rate of the mining fields more quickly and accurately.

A novel charge pump with variable frequency modulation (VFM) is proposed in this paper. To provide base for its design and improvement, detailed models for VFM charge pump are derived. And it is successfully implemented for the charge pump to introduce a voltage controlled oscillator (VCO) to control the switching frequency, which results in its high efficiency and low ripple output both at high load and light load. The chip is designed and fabricated in TSMC 0.35um mixed signal process. The simulation and test results show that high efficiency (up to 75%) and very low ripple output ( around 10 mV) is realized as expected. Besides, the accuracy of the model's prediction is proved.

Modular design technologies play a vital role in the success of enterprise production and marketing. A method based on Generic Product Structure for developing various modular products is presented in this article, which can present an effective method for enterprise during the process of module generation, platform creation and variant products delivering.

A CMOS bandgap reference (BGR) capable of operating at supply voltage of 0.9V was proposed in this paper. To guarantee its normal operation at ultra low supply voltage, the substrate bias techniques is used to reduce the threshold voltage. Meanwhile, an amplifier biased by subthreshold current is designed. This circuit is designed in tsmc 0.35μm CMOS technology. An average reference voltage of 658mV with a temperature coefficient of 18.5 ppm/_ is achieved.

A low voltage high linearity MOSFET-only Delta-Sigma modulator for implantable neural signal sensors is presented in this paper. In order to reduce the capacitor area significantly, most of the capacitors in the modulator are implemented by the single PMOSFET MOSCAPs in inversion region. The rest capacitors are realized by series compensated MOSCAPs to ensure high linearity over the wide swing. A DC level shift technique is employed in the first integrator to guarantee the PMOSFET in the inversion region and thus extend the input signal swing. Besides, a 4-bit quantizer is applied to increase the signal-to-noise-and-distortion-rate (SNDR) and decrease the output swing of each integrator for the linearity optimization of MOSCAPs. The bottom terminal parasitic effect of PIP (poly-insulator-poly) capacitors is also eliminated completely as a result of MOSCAPs application. The modulator is simulated in a 0.35μm n-well standard CMOS process and achieves 104dB SNDR at 8k-Hz signal bandwidth. Compared with the PIP capacitor design, this work reduces about 77% of the total capacitor area.