Willy Sansen’s research while affiliated with KU Leuven and other places

A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation. A three-stage IAC amplifier was implemented and fabricated in a 0.35 μm CMOS technology. Experiment results show that the implemented IAC amplifier, driving a 150 pF load capacitance, achieved a gain-bandwidth product (GBW) of 4.4 MHz while dissipating only 30 μW power with a 1.5 V supply.

In this work, the high frequency (RF) performance of FinFETs is investigated in detail using a two-level parasitic model comprising outer and inner parasitic capacitances in addition to parasitic series resistances. Use of scaling relations of these parasitic capacitances with numbers of fins and fingers allows extraction of these elements. Next, by defining a series of reference surfaces, each associated with a certain set of parasitic elements, we proceed to calculate the RF figures of merit, namely fT and fmax at these surfaces. These are called `available fT (fmax)' in this work. Analysis of the available fT (fmax) gives insight into the extent to which different parasitics affect the FinFET's RF performance. The main bottleneck to the FinFET's RF performance is identified, solutions are proposed and relevant trade-offs are discussed.

At its August meeting, the SSCS AdCom celebrated the conversion of the Society's Newsletter into a Magazine and heard a breathtaking preview of how ISSCC might look in 2020. According to conference spokesman Dennis Monticelli, the ISSCC may go virtual, with e-papers, an e-digest, and other complementary materials such as an e-journal developed as a result. Task Force actions taken to date will result in four experimental satellite conferences next year in the Far East, within three weeks of the ISSCC. This project not only addresses the future of the ISSCC, but of all SSCS conferences, even conferences in general.

SSCS members ask me, is hardware disappearing? Has it gone virtual, or has it been globalized out? The Journal of Solid-State Circuits is hardware. However, the thick pack of paper we are used to receiving every month is disappearing, virtualized together, perhaps, with our desk. Nowadays the circuit "paper" comes in layers, organized per screen. The layers go up and down -- up for the applications, down for the circuit details -- with one delta of understanding added per screen. Thus, design has gone virtual. Or is it the hardware (chip) that has gone virtual? Has the design of this hardware gone soft? A conference, on the other hand, is like the premiere of a painting exhibit. We receive a catalogue beforehand. Then we then get together with a few colleagues or friends to make a short tour. We exchange our impressions and at the reception at the end we have a drink (free for SSCS members).

This paper presents a low-power LDPC decoder design for additive white Gaussian noise (AWGN) channels. The proposed decoding scheme provides constant-time decoding and thus facilitates real-time applications where guaranteed data rate is required. It ...

This paper presents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10bits for a 10MHz signal bandwidth. It is designed in a standard 0.18μm CMOS technology and consumes only 6mW. After the design/selection of the topologies for the integrators, comparator and D/A converters, optimal sizing of the complete modulator was ensured by using a hierarchical bottom-up, multi-objective evolutionary design methodology. With this methodology, a set of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decomposed lower-level subblocks. From the generated Pareto-optimal design set, a final optimal design is chosen that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption.

This paper provides a review of all important effects in nm CMOS technologies, with 1 volt supply voltages. They are the reduction of the transconduction, the increase of the gate current, the noise and the mismatch. It is followed by an overview of amplifiers/filters configurations with both Gate and Bulk drives. A large number of sub-1 volt circuits are then provided for sake of illustration, including sigma-delta modulators.

A hierarchical synthesis methodology for analog and mixed-signal systems is presented that fully in a novel way integrates topology selection at all levels. A hierarchical system optimizer takes multiple topologies for all the building blocks at each hierarchical abstraction level, and generates optimal topology combinations using multi-objective evolutionary optimization techniques. With the presented methodology, system-level performance trade-offs can be generated where each design point contains valuable information on how the systems performances are influenced by different combinations of lower-level building block topologies. The generated system designs can contain all kinds of topology combinations as long as critical inter-block constraints are met. Different topologies can be assigned to building blocks with the same functional behavior, leading to more optimal hybrid designs than typically obtained in manual designs. In the experimental results, three different integrator topologies are used to generate an optimal system-level exploration trade-off for a complex high-speed DeltaSigma A/D modulator