# William H. Kautz's scientific contributions

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## Publications (29)

A cellular array is a two-dimensional, checkerboard type interconnection of identical modules (or cells), where each cell contains a few bits of memory and a small amount of combinational logic, and communicates mainly with its immediate neighbors in the array. The chief computational advantage offered by cellular arrays is the improvement in speed...

This chapter is concerned with the analysis and design of efficient micro-cellular logic arrays whose behavior is controlled by electronic programming (one or two flip-flops) in each cell. In addition to the usual advantages of cellularity, these arrays are characterized by their versatility—they can exhibit a very wide range of behavior from a sin...

A design is presented for an augmented content-addressed memory (ACAM) that can realize arbitrary combinational and sequential logic as well as a repertoire of simulta- neously executed but varying word-organized operations. The ACAM array is offered as a useful and efficient module that is highly compatible with large-scale-integrated (LSI) device...

Faults can be circumvented in one-dimensional cellular arrays simply by switching out (bypassing) the defective cells in the cascade. In this note, the problem is solved of finding the minimal network of switches capable of bypassing up to q possibly defective cells from an n-celled array. The cells may be combinational or sequential, unilateral or...

A cellular-logic approach is used to generate a family of multiple-output combinational switching circuits containing closed loops ( of the type that normally generate sequential behavior) and composed of simple gates. These networks contain fewer gates than any loop-free realizations. Some members of the family are oscillatory, while others are st...

A cellular array is a logical network of identical or almost identical cells, each of which contains a small amount of logic and storage, and, except for a few buses to the edge of the array, is connected only to its immediate neighbors. The cellular approach offers special advantages for realization by the forthcoming large-scale-integrated (LSI)...

As a direct consequence of large-scale integration, many advantages in the design, fabrication, testing, and use of digital circuitry can be achieved if the circuits can be arranged in a two-dimensional iterative, or cellular, array of identical elementary networks, or cells. When a small amount of storage is included in each cell, the same array m...

Described in this report are the results of a comprehensive technical survey of all published Soviet literature in coding theory and its applications--over 400 papers and books appearing before March 1967. The purpose of this report is to draw attention to this important collection of technical results, which are not well known in the West, and to...

The report presents results of a second project concerned with the theory of cellular logic networks and machines. The ultimate objective of this program is the development of effective mathematical techniques for the analysis and synthesis of cellular logic networks and machines. The report deals with the design of array interconnection networks f...

The report presents results on a first project covering research on the design of modular multifunctional logic networks. The objective of the research is the development of design techniques for general logical nets made up of modules constrained in various ways or satisfying certain criteria. Module complexity, terminal pin count, and signal dela...

The problem is treated of finding for a set of identical processing elements an interconnection structure that achieves a certain richness of interelement communication with only a limited number of actual inter-element connections. In graphical terms, this problem is one of finding a universal n-node graph of minimal degree D(n,d) in which every n...

Abstract—A class of networks is described that has the capability of permuting in an arbitrary manner a set of n digital input lines onto a set of n digital output lines. The circuitry of the networks is arranged in cellular form, i. e., in a two-dimensional iterative pattern with mainly local intercell connections, where the basic cell behaves as...

Abstract—he problem of designing test schedules for the testing or diagnosis of a small number of nontransient faults in combinational digital circuits (switching networks) is considered in detail. By testing and diagnosis we mean the following: 1) detection of a fault, 2) location of a fault, and 3) location of a fault within the confines of a pre...

Cellular logic arrays are beginning to take on an increasingly greater importance in digital technology, mainly because of their numerous advantages for the design, manufacture, and use in digital systems employing large-scale integrated semiconductor arrays. Particularly significant among these advantages is the feature of testability. One would n...

Computationally efficient algorithms are presented for the clustering of the gates of an arbitrary network into pin-limited modules for minimum worst-cast network delay, assuming all delays are at module interfaces. Algorithms are presented for optimally locating clock-distribution terminals on a clock network having uncertain delays proportional t...

The purpose of this paper is to describe the design of an all-digital cellular threshold array that is well adapted to realization by large-scale integrated semiconductor technology. A set of these arrays may be interconnected to realize arbitrary combinational or sequential logic, or may be stacked to form a multilevel adaptive pattern classificat...

This report presents results of research on cellular logic techniques. The objective of the research has been to develop techniques for the efficient realization of general logical functions in cellular arrays. The report covers the subjects of theory and application of cascade decompositions; universal logic module studies; sampled sequence detect...

The report summarizes the results of the third year of research on techniques for the analysis, organization, and design of logical networks in which the propagation delays on the lines interconnecting the operational blocks of the network are appreciable compared to the delays within the blocks. During this reporting period, technical advances hav...

A comprehensive technical survey of Soviet switching theory and its applications to the logical design of digital systems reveals that, despite considerable activity (763 papers and books), the average state of the art in the U.S.S.R. is somewhat behind that in the U.S. However, there are a large number of noteworthy contributions, particularly in...

A new family of codes is described for representing serial binary data, subject to constraints on the maximum separation between successive changes in value (0 rightarrow 1, 1 rightarrow , or both), or between successive like digits ( 0 's, 1 's, or both). These codes have application to the recording or transmission of digital data without an acco...

A family of single-error-correcting codes is described for the protection of binary data words of fixed length k , each of which has the same number w of 1 's. The code family is shown to be valid for all integers k and w (where 0 < w < k) . Some other related codes, based upon conventional Hamming codes, Latin squares, and block designs are also d...

A binary superimposed code consists of a set of code words whose digit-by-digit Boolean sums (1 + 1 = 1) enjoy a prescribed level of distinguishability. These codes find their main application in the representation of document attributes within an information retrieval system, but might also be used as a basis for channel assignments to relieve con...

This paper describes an IBM 7090 program for the design of single output combinational switching circuits for arbitrary sets of primitive logical elements. The only restriction on circuit configurations is that no feedback loops may occur. The procedure is an outgrowth of one given by Roth. The decomposition techniques are generalizations of those...

The problem of synthesizing switching networks out of linear-input (threshold) elements is studied for the class of symmetric switching functions. Tight bounds are derived for the number of elements required in a minimal realization, and a method of synthesis is presented which yields economical networks. Minimal networks result for all symmetric f...

First Page of the Article

Following are statements of several unsolved problems which may be of interest to researchers and students in the fields of switching theory or logical design, and in some cases to applied mathematicians with combinatorial leanings. Where pertinent, the most significant references to the literature are cited. Most of these problems have arisen from...

A class of counters is described in which the number of 1's in the flip-flops or register stages composing the counter remains constant as the counter advances from state to state. Simple digital circuit arrangements are described for the design of such counters, which may be used with a particular type of decoding tree as economical ring-type coun...

## Citations

... Linear cascades of fixed cell types could be aligned vertically to form a two-dimensional mesh. The result of each vertical cascade could be summed together in either sum-of-products [11], productof-sums [20], or Reed-Muller form [13] to generate a final result. Virtually all arrays and cascades used unidirectional logic flow (e.g top to bottom or left to right). ...

... Despite being known for a long time, active research is still going on on De Bruijn and Kautz digraphs B(d, D) and K(d, D) [4,7,17,18], both in graph theory [5,9,15,20] and in network engineering [12,21,25,28]. This paper is concerned with deflection routing in these kind of networks. ...

... Threshold logic based on adder (FATL) concept was first realized by Kautz [17]. It was stated that the advantage of the design is to implement n-bit TLG with about log2(n) components. ...

... Examples for 9, 10, or 11 players are given in Freixas andMolinero (2009a, 2010). In the field of threshold logic, examples of threshold functions requiring large weights are discussed by Myhill and Kautz (1961), Muroga (1971), Håstad (1994). Some previous studies enumerate (minimal) integerweight representations of simple games with a small number of players (e.g., Muroga et al. 1962;Winder 1965;Muroga et al. 1970;Krohn and Sudhölter 1995). ...

... Test methods in use today began to be developed in the 1960's anticipating circuit sizes that would make exhaustive test methods intractable. Classical test theory attempts to determine if a given circuit is or is not functional [1,2]. This is accomplished by testing a circuit in order to determine if any of the logical failures modelled by the set of considered fault models are present. ...

... Testing of iterative arrays have been previously studied with C-testability, which is primarily based on functional testing with constant number of test patterns to test each PE [18], [19]. Friedman [19] presented a theory for modified Ctestability based on the function of the processing cell, which detects single faulty cell of an array. ...

... In a limited sense the proposal was for a 16-pe DAP without the processor interconnections. Kautz (1971) proposed a more extensive logic-in-memory computer called an Augmented Content-Addressed Memory (ACAM) with special circuitry for sorting, matrix inversion, fast Fourier transform, correlation etc. The engineering of the l s i chips was to be by cellular arrays with a universal logic capability, implementing as far as possible in hardware special algorithms that had been devised for parallel computation: for example, fast Fourier transform (Pease 1968) and matrix inversion (Pease 1967). ...

... There has been a great interest among the distributed system researchers to solve this problem under different assumptions. Many of those contributions are concerned with non-anonymous instance of spanning trees, see for example [370][371][372][373][374], this problem is also addressed under parallel settings [375][376][377][378][379][380][381][382]. In anonymous instance of the problem, all the nodes can initiate the construction of spanning tree concurrently. ...

... Prior work has explored near-DRAM processing elements near DRAM arrays [30,31,32,33,34] and processing elements coupled with DRAM cells [35,36,37,38] There are multiple advantages that arise from near-memory computing. First, the memory bandwidth has significantly increased, because the bottleneck in the external memory data bus no longer exists. ...