Vikash Sonar’s research while affiliated with KLE Technological University and other places

RISC V architecture is finding its importance with semiconductor industry and academia. With the availability of open instruction, set design of the processor is possible. The RTL needs an extensive verification. Simulation-based methods are rampant, but exhaustive test generations are required. The papers reports design and System Verilog verification of the five-stage RISC V processor. Mentor Questa simulator is used to verify the design. The code coverage reported is 80%.