Uwe Mayer’s research while affiliated with TUD Dresden University of Technology and other places

In this article a fully differential CMOS attenuator with automatic matching and control linearization is presented. The circuit was measured from 100 MHz to 10 GHz and exhibits a phase variation of only 4° within an attenuation control range of 30 dB. The maximum gain control range is almost 50 dB. The control circuitry draws less than 500 μA from a 1.8 V supply. The circuit was fabricated in 0.18 μm CMOS requiring only 0.044 mm2 of chip area.

This paper presents an integrated 802.11a compliant receiver integrated circuit (IC), which is capable of processing four antenna signals using RF multiple-input multiple-output (RF-MIMO) schemes. Following four low-noise amplifiers, the weighting is performed using Cartesian vector modulators, whose output signals are combined and down-converted. The baseband filters, variable gain amplifiers (VGAs), a quadrature voltage-controlled oscillator, and digital interfaces are integrated. Experimental results demonstrate the performance of the individual components, as well as the RF-MIMO capabilities of the whole chip. The IC achieves a receiver noise figure of 3.6 dB, a phase noise of $-{\hbox{113 dBc}}/{\hbox{Hz}}$ at 1-MHz offset, and an equivalent Cartesian weighting precision of 6$\,\times\,$6 bit. An RF input signal of up to $-{\hbox{35.3 dBm}}$ (1-dB compression) can be processed, while the maximum RF path gain amounts to 28.6 dB. The baseband VGA provides further 9–61-dB gain in 64 steps.

This paper presents and analyzes an active vector modulator based on the polar coordinate system and composed of circulator-based phase shifters and a variable gain amplifier. The design provides full phase control range of 360$^{\circ}$ and gain control range of 36 dB for a wide frequency range of 2–6 GHz. Phase and gain can be controlled with total root mean square (rms) linearity errors of 6.3$^{\circ}$ and 0.15 dB and rms correlation errors between gain and phase of 0.6 $^{\circ}$ and 1.1 dB, respectively. Therefore, the design is suitable for RF diversity receivers in the S- and C-bands. The integrated circuit includes all necessary peripheral circuits, such as a digital control block and internal references and covers 1.06 $\ {\hbox {mm}}^{2}$ on a 0.25-$\mu{\hbox {m}}$ BiCMOS technology.

This article presents an integrated receiver (RX) for antenna combining in the radio-frequency (RF) front-end for 802.11a designed in 0.25µm SiGe BiCMOS. The four-element array includes four low noise amplifiers (LNAs), vector modulators (VMs), and a signal combiner. These circuits can weight the incoming C-band (5.6GHz) signals in their I- and Q-components with an 8-bit resolution before superposition and downcoversion. The zero-IF architecture integrates a complete RX including an 8th order switched-capacitor (SC) filter for channel selection and an automatic gain control (AGC). Together with digital control logic the integrated circuit (IC) has a power consumption of 350mW and an area of 7.5mm2.

This paper presents enhancements in the physical layer of 802.11a wireless local area networks (WLANs) to support multiple-input multiple-output (MIMO) communication. In this approach, spatial diversity is exploited at the radio-frequency (RF) front-end by weighting the transmitted and the received signals using integrated circuits (ICs). Their optimum weight settings are derived by baseband algorithms based on the estimated MIMO channel response. Prototyping platforms are designed for baseband signal processing and RF transmission, which contain all key components for the RF-MIMO technique and 802.11a data transmission, respectively. The developed algorithms, computing platforms and ICs are successfully verified with respect to the RF-MIMO concept and their compatibility to 802.11a devices.

This paper presents an active BiCMOS vector modulator based RF weighting circuit suitable for WLAN diversity transceivers. It features a LNA, a SPI and 8-bit DACs for vector control and internal references. When mounted on a PCB, it delivers a maximum gain of 12 dB at 5.6 GHz. It draws a current of 17 mA from a 3.3 V supply. The whole design is free of bulky inductors thus requiring an area of only 1.3 mm². Index Terms — Vector modulator, BiCMOS, MIMO, adap- tive antenna combining.

When examining a monthly bank account statement, it is not only the number below the bottom line that matters. Whether that number has a minus or plus in front of it is crucial. For many technical problems, the sign matters as well. In circuits, we can change the sign by means of phase shifters. Moreover, by using phase shifters, intermediate states between the signs (including complex values) can be set in circuits. Hence, phase shifters play an important role in electrical engineering. Unfortunately, this article does not give direct insights to change the sign of your bank statement. However, it aims to give a comprehensive overview of tunable phase shifters for radio frequency (RF) applications including cookbooklike design guidelines and performance comparisons. The focus of this article is put on phase shifters fully integrated in a chip.

Phase variations of variable gain cascode amplifiers are analysed and a method, which significantly reduces the phase variations versus gain is presented. The operation point current and the load of the variable gain transistors are stabilised by current weighting using dummy paths. The approach is verified by a fully integrated CMOS variable gain amplifier at C-band. A maximum gain of 18 dB with a 1 dB bandwidth of 5.2 5.7 GHz is measured. At 5.7 GHz and within a gain control range of 23 dB the absolute phase difference is reduced to a minimum of ±4° yielding an improvement by a factor of 5 compared with simple cascode topologies. A total supply power of 9 mW is consumed. A very low phase variation has been achieved at comparable gain control range and power consumption for a variable gain amplifier in CMOS.

This document describes the design of received signal strength indicators (RSSI) for RF-MIMO systems. It covers considerations of system level aspects such as dynamic range and the suiting location of the RSSI and presents the implementation of a fully integrated RSSI circuit for 802.11a compliant diversity receivers. Drawing a total current of 6.1 mA from a 3.3 V supply, this circuit provides a dynamic range of about 35 dB with a high response speed of less than 1.15 μs even under heavy capacitive loading conditions.