Tom Chen's research while affiliated with Colorado State University and other places

Publications (101)

Article
Full-text available
Dietary supplementation is the most feasible method to improve oocyte function and developmental potential in vivo. During three experiments, oocytes were collected from maturing, dominant follicles of older mares to determine whether short-term dietary supplements can alter oocyte metabolic function, lipid composition, and developmental potential....
Article
Advanced maternal age is associated with a decline in fertility and oocyte quality. We used novel metabolic microsensors to assess effects of mare age on single oocyte and embryo metabolic function, which has not yet been similarly investigated in mammalian species. We hypothesized that equine maternal aging affects the metabolic function of oocyte...
Article
Full-text available
Mitochondrial replication is arrested during early cleavage stages, leaving the embryo dependent on maternally derived mitochondria for oxidative phosphorylation. Numbers of mitochondrial DNA (mtDNA) are used as indicators of functional mitochondria; however, direct comparisons for mtDNA and oxygen consumption rate (OCR) have not been performed for...
Article
Full-text available
This paper presents the development of a multi-sensor platform capable of simultaneous measurement of dissolved oxygen (DO) concentration, glucose and lactate concentrations in a micro-chamber for real-time evaluation of metabolic flux in bovine embryos. A micro-chamber containing all three sensors (DO, glucose, and lactate) was made to evaluate me...
Poster
Create an ex vivo microfluidic platform that maintains cellular diversity and optimizes physiological relevance. Many in vitro experimental models of the gastrointestinal tract rely upon cell lines, and consequently, lack the diversity of cells and microorganisms present in vivo. Studies using cell lines fail to accurately represent the complex bi...
Article
The ability to view biological events in real time has contributed significantly to research in the life sciences. While video capture of real time changes in anatomical relationships is important, it is equally important to visualize real time changes in the chemical communications that drive cell behaviors. This paper describes an electrochemical...
Preprint
Full-text available
Current commercially available instruments for monitoring mitochondrial respiration are incapable of single cell measurements. Therefore, we developed a three-electrode, Clark-type biosensor suitable for mitochondrial respirometry in single oocytes and embryos. The biosensor was embedded in a PMMA (polymethyl methacrylate) micro-chamber to allow in...
Poster
Full-text available
This work describes the development of an integrated sensors system to measure concentrations of dissolved oxygen (DO), pH, glucose, and lactate concurrently at single cell level. DO was measured amperometrically using a three-electrode system of working (WE), counter (CE) and reference (RE) electrodes. pH was measured potentiometrically using two...
Article
Full-text available
This paper describes the response characteristics of a Clark type oxygen sensor using microelectrodes under a variety of operating conditions. The silicon based microelectrodes were fabricated using a CMOS process with Pt surface using a lift-off process. The Clark type sensor was configured using a three-electrode system. A set of four operating c...
Conference Paper
Full-text available
There has been a growing interest in electrochemical measurement of the output from biological specimens. With the advent of silicon CMOS technology, it is possible to measure target molecule release and movement through extra cellular space using microelectrode arrays (MEAs). While MEAs have been used for electrophysiological measurements, their u...
Conference Paper
In this paper, a circuit for signal stimulus generation and response signal acquisition for electrochemical impedance spectroscopy (EIS) is presented. The circuit is capable of generating a stimulus signal consisting of 32 frequencies with a 2 Hz (low band) and a 62 Hz (medium band) step from 2 Hz to 2 kHz. A composite signal was generated from the...
Article
In a high-speed synthesis design environment, designers struggle to ensure that multi-clock and multi-power interfaces are designed, placed, connected and timed correctly. Identifying and applying proper timing constraints such as “no cycle stealing” at synchronous and asynchronous domain interfaces in macro synthesis, unit and chip timing are esse...
Article
Full-text available
A high-density amperometric electrode array containing 8192 individually addressable platinum working electrodes with an integrated potentiostat fabricated using Complementary Metal Oxide Semiconductor (CMOS) processes is reported. The array was designed to enable electrochemical imaging of chemical gradients with high spatiotemporal resolution. El...
Article
Electrochemical detection of NO generated from chemical donors is reported. Because NO is an important biological messenger, many donor sources and detection methods have been developed. Few reports have characterized NO donors using electrochemistry despite electrochemical techniques being sensitive and selective. Here, a CMOS platinum microelectr...
Article
We propose a physical design methodology for synthesis using soft hierarchy, interior pin placement, pre-placing critical logic, and routing techniques on a very timing- and area-challenged unit, the L2 cache, with ~20 million synthesizable transistors. In any past and present standard design at IBM, this test case would stretch all front- and back...
Article
Design of biosensor circuits requires low power and low noise. One of the important components in a sensor read channel is the analog-to-digital converter (ADC). In addition to the circuit design techniques to achieve low power consumption, the use of low supply voltage is an effective alternative to reduce the overall power consumption of a CMOS c...
Conference Paper
Biomedical devices are often battery operated and require low power consumption. As biomedical devices increase in complexity to include multiple functions such as signal processing and data storage, the constraint on power consumption becomes a larger issue. This paper presents a low power design for a decimator as part of a sigma-delta ADC for bi...
Article
In this paper, a microelectrode array is introduced and characterized using differential pulse voltammetry (DPV), amperometry and fast scan cyclic voltammetry with norepinephrine as a model neurotransmitter. Twenty-one sensor geometries were evaluated with DPV to determine optimal electrode configurations. Next, electrode responses were characteriz...
Article
Due to limited battery capacity, electronics in biomedical devices require low power consumption. On the other hand, biomedical devices that integrate multiple functions like sensing, amplification, signal conditioning, signal processing, data storage, etc. have put a greater constraint on power consumption for each functional unit. This paper pres...
Article
Clock distribution in the multi-gigahertz range is getting increasingly difficult due to more stringent requirements for skew and jitter on one hand and the deteriorating supply voltage integrity and process variation on the other hand. Global clock network, especially in nanometer CMOS designs with ever increasing die sizes, has become a prominent...
Article
Optoelectronic components for clock distribution that are fully compatible with all standard CMOS processes are described. Waveguide cores are silicon nitride, while the waveguide cladding is silicon dioxide. Polysilicon photodetectors offer responsivities up to 1.3 A/W, 10–90% rise time of 0.58ns, and full-width half-max duration of 0.85ns. Power...
Article
Rapid and effective design space exploration at all stages of a design process enables faster design convergence and shorter time-to-market. This is particularly important during the early stage of a design where design decisions can have a significant impact on design convergence. This paper describes a methodology for design space exploration usi...
Article
Metal-semiconductor-metal (MSM) polysilicon photodetectors which are compatible with all standard complementary metal-oxide-semiconductor (CMOS) processes and which were made in a commercial 0.35 mum process have demonstrated DC responsivities up to 1.3 A/W at 690 nm. An effective absorption coefficient of 0.63 dB/&mum was found from a comparison o...
Article
Most existing optimization methods for analog cir- cuits focus on the accuracy of their performance modeling techniques, which results in complicated and non-intuitive models such as high order polynomials or high rank matrices. These models may give designers good estimates on circuit performance, but not sufficient insight into the circuit behavi...
Conference Paper
Early design phase space exploration, power validation and performance estimation will enable faster design convergence and shorter time-to-market. System level models based on physical design parameters, in-situ macro models and background SPICE simulation improves overall model accuracy. This paper describes a pareto analysis methodology for desi...
Conference Paper
Early phase space exploration with a focus on power performance tradeoffs has been shown to enable faster design convergence. Tightly coupled physical design considerations and system level models are needed to guarantee time-to- market. This paper describes a methodology for early design space exploration. A Pareto-front analysis using the propose...
Conference Paper
Radiation-induced soft errors on large-scale integrated circuits are becoming increasingly problematic as device sizes are scaled down, operating voltages are reduced, and node capacitances shrink. Therefore, chip reliability has become a big issue in modern VLSI design and the importance of detecting soft error in combinational logic circuits has...
Conference Paper
The Partnership for Engineering Education in the Rockies (PEER) has developed an electrical and computer engineering curriculum for high school students in the Northern Colorado region. PEER brings together representatives from the semiconductor industry and educational institutions, led by Colorado State University, who are dedicated to improving...
Article
CMOS technology scaling especially in the sub-100 nm regime has made signaling in long global a challenge, resulting in a need for an improved interconnect technology. Optical signalling is a promising alternative to existing global interconnects and alleviates interconnect bottle-neck. This paper presents a design of a CMOS trans-impedance amplifi...
Article
Complementary metal-oxide-semiconductor-compatible metal-semiconductor-metal polysilicon photodiodes fabricated in a commercial 0.35-mum technology offer estimated responsivities of up to 0.35 A/W at 654 nm. An effective absorption coefficient of 0.63 dB/mum was extracted from responsivities for 5- to 10-mum-long waveguide-coupled detectors. Increa...
Article
Continued scaling of silicon process technologies beyond the 90nm node will face problems due to within die process variations. The increasing relative magnitude of within die process variations will cause power-frequency distributions to widen, thus reducing manufacturing yields. Mitigating the effects of these process variations can be done by us...
Conference Paper
Early design space exploration is crucial to achieving optimal designs, when it is increasingly difficult to fit a design into a tight design space. System level exploration needs to be coupled with physical design considerations to guarantee design closure and time-to-market. This paper presents a methodology for early design space exploration aim...
Conference Paper
The Partnership for Engineering Education in the Rockies (PEER) is a unique collaboration of teaching and industry professionals dedicated to developing an electrical and computer engineering curriculum for high school students in the Northern Colorado region. PEER offers four college-level courses to high school students, including courses in intr...
Article
Characterization of leaky-mode coupled polysilicon MSM photodetectors fabricated in 0.35 mum commercial CMOS with varying contact spacing and length reveals short and narrow devices have responsivity sufficient for optical interconnect applications
Conference Paper
Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of different inputs on a logic gate ever closer to each other. The traditional method of static timing analysis assuming single input switching is no longer adequate enough to capture gat...
Article
Performance optimization is a critical step in the design of integrated circuits. Rapid advances in very large scale integration (VLSI) technology have enabled shrinking feature sizes, wire widths, and wire spacings, making the effects of coupling capacitance more apparent. As signals switch faster, noise due to coupling between neighboring wires b...
Article
It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and cannot be ignored in delay modeling for these nets. However, the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ult...
Conference Paper
A formal methodology for the analysis of a closed loop clock distribution and active deskewing network is proposed. In this paper an active clock distribution and deskewing network is modeled as a closed loop feedback system using state space equations. State space analysis allows systematic analysis of any clock distribution and deskewing systems...
Article
We propose a sensitivity-based method to allocate decaps incorporating leakage constraints and tighter data and clock interactions. The proposed approach attempts to allocate decaps not only based on the power grid integrity criteria, but also based on the impact of power grid noise on timing criticality and robustness. The resulting algorithm redu...
Conference Paper
In this paper, a methodology for analyzing closed loop clock distribution and active deskewing networks is proposed. An active clock distribution and deskewing network is modelled as a closed loop feedback control system using state space equations. The state space models of the system were then used to simulate the clock deskewing scheme, and most...
Article
With continuing scaling of CMOS process, process variations in the form of die-to-die and within-die variations become significant which cause timing uncertainty. Statistical design methods have been proposed in the past to model the impact of process variations. However, all the existing methods deal almost exclusively with modeling delay variatio...
Article
We present single- and dual-rail mixed pass-transistor logic (PTL) synthesis method based on genetic search and compared the results with their conventional static CMOS counterparts synthesized using a commercial logic synthesis tool in terms of area, delay, and power in an experimental 0.1- and 0.13-μm CMOS technologies as well as a 0.13-μm floati...
Conference Paper
Abstract— Rapid advances in VLSI technology have enabled shrinking feature sizes, wire widths, and wire spacings making the effects of coupling capacitance more apparent. As signals switch faster, noise due to coupling between neighboring wires becomes more pronounced. Changing relative signal arrival times alters the victim line delay due to the v...
Article
Process variations as a percentage of nominal delay and power consumption are becoming more and more severe with continuing scaling of VLSI technology. The worsening process variation causes increased variability in performance, power, and reliability of VLSI circuits. Thus, performance and power consumption targets obtained during the design phase...
Conference Paper
We present a silicon-on-insulator (SOI) pass-transistor logic (PTL) gate with an active body bias control circuit and compare the proposed PTL gate with other types of PTL gates with different body bias circuits in two different 0.13 μm SOI CMOS technologies. The experimental results show that the proposed SOI PTL gate using the body bias controlle...
Conference Paper
The test chip presented in this design is intended to allow: 1) circuit and package designers to evaluate and validate the accuracy of package models under a variety of environment conditions; 2) system designers to evaluate package/system level signal integrity issue before actual chips are available; and 3) system designers to evaluate on-chip te...
Article
Object-based coding and description in real time are increasingly important for many image and video applications. We propose a very large scale integration (VLSI) architecture based on a novel segmentation algorithm for extracting objects in video. The segmentation architecture of a frame mainly consists of two functional phases. In the first phas...
Conference Paper
The verification of behavioral models is an important step before transferring a hardware design to the layout. A popular approach is to use a variety of code coverage measures to evaluate how much of the design has been simulated. Common coverage measures include branch coverage and bit toggle coverage. This paper presents a test pattern generatio...
Article
Anti-random testing has proved useful in a series of empirical evaluations. The basic premise of anti-random testing is to chose new test vectors that are as far away from existing test inputs as possible. The distance measure is either Hamming distance or Cartesian distance. Unfortunately, this method essentially requires enumeration of the input...
Conference Paper
Statistically forecasting potential returns in terms of code coverage for a given set of test cases (patterns) to be applied to a behavioral model can improve the overall effectiveness of behavioral model verification. In this paper, we present a forecasting model for behavioral VHDL model verification. The statistical assumptions of the proposed m...
Article
We present a segmentation scheme in order to develop a method which can identify homogeneous regions to represent higher level objects for content-based functionality. The proposed scheme extracts multiple features, such as motion and texture, on the pixel basis. Different weights are applied to each feature components based on motion confidence me...
Conference Paper
Full-text available
In order to improve the efficiency of behavioral model verification, it is important to determine the points of diminishing return for a given verification strategy. This paper compares the existing stopping rules and presents a new stopping rule based on static Bayesian technique. The new stopping rule was applied to verifying 14 complex VHDL mode...
Conference Paper
Verification of complex behavioral models has become a critical and time-consuming process. Determine when to switch to different testing strategy phase is the key to improving efficiency. This paper presents an overview of the existing statistical stopping rules that can be used for behavioral model verification. We examined the stopping rules usi...
Article
Full-text available
We present more evidence in a 0.25 μm CMOS technology that the pass-transistor logic (PTL) structure that mixes conventional PTL structure with static logic gates can achieve better performance and lower power consumption compared to conventional PTL structure. The goal is to use the static gates to perform both logic functions as well as buffering...
Article
Full-text available
This paper proposes criteria for the verification of behavioral designs for hardware written in VHDL. The criteria are analogous to testing criteria for software, but were adapted to the specific needs and constructs of hardware designs written in VHDL. We examine the potential value of these criteria with respect to desirable properties for evalua...
Article
Full-text available
During behavioral model verification, it is important to determine the stopping point for the current test strategy and for moving to a different test strategy. It has been shown that the location of the stopping point is highly dependent on the statistical model one should choose to describe the coverage behavior during the verification process. T...
Article
We propose an image sequence segmentation scheme which can provides region information for object based coding, content based access and manipulations. The scheme consists of two stages: in the initial stage, a multiple feature space consisting of color, texture, motion is transformed to one dimensional label space by using Self Organizing Feature...
Article
. We develop an image sequence segmentation scheme which uses intensity, motion, edge, and texture features. The proposed scheme is simple and inherently parallel in nature. Motion condence values are employed for a feature weighting scheme in order to suppress unreliable feature components. These feature vectors are quantized by training self-orga...
Article
Full-text available
When designing a system in the behavioral level, one of the most important steps to be taken is verifying its functionality before it is released to the logic/PD design phase. One may consider behavioral models as oracles in industries to test against when the final chip is produced. In this work, we use branch coverage as a measure for the quality...
Article
Semantic object segmentation is an important step for object based coding, content based access and manipulations. We propose a segmentation scheme for image sequences which provides initial region information for the semantic object representation of those applications. Our objective is to develop a segmentation method which has hardware friendly...
Article
We present a segmentation technique for image sequences using Self Organizing Feature Maps(SOFM). Our goal is to develop a method which can identify homogeneous regions in a frame to represent higher level objects for content based manipulation of image sequences. The proposed scheme extracts pixel based multiple features, such as motion and textur...
Article
Soft errors resulting from alpha-particle strikes are one of the major factors that reduces the reliability of memory chips. One way to improve reliability of memory chips is to employ an on-chip error-correcting code (ECC) structure. This paper presents a triple-error correcting and quadruple-error detecting (TEC–QED) code, that is capable of corr...
Conference Paper
This paper proposes criteria for the verification of behavioral designs for hardware written in VHDL. The criteria are analogous to testing criteria for software, but were adapted to the specific needs and constructs of hardware designs written in VHDL. We examine the potential value of these criteria with respect to desirable properties for evalua...
Conference Paper
During behavioral model verification, it is important to determine the stopping point for the current test strategy and for moving to a different test strategy. It has been shown that the location of the stopping point is highly dependent on the statistical model one should choose to describe the coverage behavior during the verification process. T...
Conference Paper
We propose an accurate measure of channel routing density and its application to global routing. Our congestion metric calculation method considers the wire scenarios in a channel.
Conference Paper
We propose a segmentation scheme and its VLSI edge fusion architecture for image sequences which provides initial region information for the semantic object representation of image sequences. The proposed scheme incorporates static and dynamic features simultaneously in one scheme. The segmentation results of both gray level image sequences and col...
Article
This article presents a test cost prediction model as a planning tool at an early stage of the design cycle to estimate manufacturing test cost of ICs. The proposed cost model estimates the IC manufacturing test cost based on test throughput. The model calculates test throughput by incorporating IC yield and fault coverage. Chip manufacturing infor...
Article
A yield prediction in the early stage of the design cycle can give positive impacts on cost and quality of IC manufacturing. However, the lack of prediction tool, that do not rely on layout data, makes it difficult to estimate the chip yield in the early design phase. This article describes yield prediction models for random logic and SRAM blocks u...
Article
This paper describes the impact of DRAM process on the logic circuit performance of Memory/Logic Merged Integrated Circuit and the alternative circuit design technology to offset the performance penalty. Extensive circuit and routing simulations have been performed to study the logic circuit performance degradation when the merged chip is implement...
Article
This paper presents an optimized column fast Fourier transform (FFT) architecture, which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, for a clock rate of 40 MHz, the system can compute a 24-b precision 1K point complex FFT transform in 9.2 /spl mu/s, far...
Article
Image recognition may consist of three main steps: edge detection, edge linking, and object/template matching. Edge detection algorithms usually produce thin edges with discontinuities. In this paper, a real-time algorithm and its VLSI implementation for linking broken edges is presented. First, all broken edge points inside a 12×12 moving window a...
Conference Paper
HDL model validation can involve billions of cycles of simulations. To improve validation efficiency we propose a stopping rule to determine when a validation phase using a specific type of patterns has reached a point of diminishing return.
Article
Virtual environments can be useful in many applications. For one, they allow designers to carry out design tasks without actually creating a physical prototype. This virtual prototyping approach leads to lower cost and a shorter time-to-market product development cycle. In order for virtual environments to be useful, it must include and integrate a...
Chapter
This chapter explores the possibilities of using neural networks to support various software testing activities. They range from automated test generation to evaluation of automatically generated test cases for their effectiveness in meeting test criteria or finding faults. Our motivation is that it would be useful to have a mechanism that is able...
Conference Paper
Full-text available
Anti-random testing has proved useful in a series of empirical evaluations. The basic premise of anti-random testing is to choose new test vectors that are as far away from existing test inputs as possible. The distance measure is the Hamming or Cartesian distance. Unfortunately, this method essentially requires emuneration of the input space and c...
Article
Using Java as the implementation language and the Netscape Communicator package, a client/server environment is established to allow requests from client stations to download the selected virtual environment to be run on the client. Various security measures, such as certification, are included in the environment to ensure proper transfer of files...
Article
The Stereoscopic Haptic Acoustic Real-Time Computer (SHARC) is a multi-sensory computer system which integrates technologies for autostereoscopic display, acoustic sensing and rendering, and haptic interfaces into the same computing environment. This paper describes the system organization and the interface between different sensory components. Thi...
Article
This paper describes the LEGOWORLD project, which is a multi-sensory virtual prototyping environment. The environment provides a multi-sensory dynamic rendering of a set of virtual LEGOTM blocks. The environment is rendered in real time on a multi-sensory computing platform, with integrated 3D-visual, audio, and haptic components. The environment i...