Thambipillai Srikanthan’s research while affiliated with Nanyang Technological University and other places

Despite the significant advancements in pre-training methods for point cloud understanding, directly capturing intricate shape information from irregular point clouds without reliance on external data remains a formidable challenge. To address this problem, we propose GPSFormer, an innovative Global Perception and Local Structure Fitting-based Transformer, which learns detailed shape information from point clouds with remarkable precision. The core of GPSFormer is the Global Perception Module (GPM) and the Local Structure Fitting Convolution (LSFConv). Specifically, GPM utilizes Adaptive Deformable Graph Convolution (ADGConv) to identify short-range dependencies among similar features in the feature space and employs Multi-Head Attention (MHA) to learn long-range dependencies across all positions within the feature space, ultimately enabling flexible learning of contextual representations. Inspired by Taylor series, we design LSFConv, which learns both low-order fundamental and high-order refinement information from explicitly encoded local geometric structures. Integrating the GPM and LSFConv as fundamental components, we construct GPSFormer, a cutting-edge Transformer that effectively captures global and local structures of point clouds. Extensive experiments validate GPSFormer's effectiveness in three point cloud tasks: shape classification, part segmentation, and few-shot learning. The code of GPSFormer is available at \url{https://github.com/changshuowang/GPSFormer}.

Robotic exploration in dynamic and complex environments requires advanced adaptive mapping strategies to ensure accurate representation of the environments. This paper introduces an innovative grid flex-graph exploration (GFGE) algorithm designed for single-robot mapping. This hardware-scheme-based algorithm leverages a combination of quad-grid and graph structures to enhance the efficiency of both local and global mapping implemented on a field-programmable gate array (FPGA). This novel research work involved using sensor fusion to analyze a robot’s behavior and flexibility in the presence of static and dynamic objects. A behavior-based grid construction algorithm was proposed for the construction of a quad-grid that represents the occupancy of frontier cells. The selection of the next exploration target in a graph-like structure was proposed using partial reconfiguration-based frontier-graph exploration approaches. The complete exploration method handles the data when updating the local map to optimize the redundant exploration of previously explored nodes. Together, the exploration handles the quadtree-like structure efficiently under dynamic and uncertain conditions with a parallel processing architecture. Integrating several algorithms into indoor robotics was a complex process, and a Xilinx-based partial reconfiguration approach was used to prevent computing difficulties when running many algorithms simultaneously. These algorithms were developed, simulated, and synthesized using the Verilog hardware description language on Zynq SoC. Experiments were carried out utilizing a robot based on a field-programmable gate array (FPGA), and the resource utilization and power consumption of the device were analyzed.

Mobile robots parking in indoor environments, trending towards complex problems, has motivated the development of new hardware computational paradigms. In this paper, we present a novel and effective research for addressing parking assistance in slot identification based on the geometry of a mobile robots using sensor data fusion with hardware schemes. This paper has been abstracted into three levels. Initially, the geometry of the mobile robots was analyzed using multi-sensory fusion at the gateway and parking slots of the indoor environment. A heuristic algorithm was developed to analyze the vehicle geometry patterns. Reconfigurable computing architectures have been developed for geometry analysis with respect to measurements of individuals or groups of robots as leader-follower and rendezvous approaches. The next level of the proposed algorithm estimates the availability of parking slots as per mobile robots geometry using a customized accelerator approach. Mobile robots navigate parking spaces using parking assistance and environmental maps. Parking assistance is integrated with direction-based path planning and odometer techniques are embedded in a known environmental navigation map. A Zynq XC7Z020-CLG484-1 Field Programmable Gate Array (FPGA) was deployed to validate and implemented the design using Xilinx Vivado 2017.4. This paper presents essential information for indoor logistics industries, hospital services, and domestic services at home.

The use of smart indoor robotics services is gradually increasing in real-time scenarios. This paper presents a versatile approach to multi-robot backing crash prevention in indoor environments, using hardware schemes to achieve greater competence. Here, sensor fusion was initially used to analyze the state of multi-robots and their orientation within a static or dynamic scenario. The proposed novel hardware scheme-based framework integrates both static and dynamic scenarios for the execution of backing crash prevention. A round-robin (RR) scheduling algorithm was composed for the static scenario. Dynamic backing crash prevention was deployed by embedding a first come, first served (FCFS) scheduling algorithm. The behavioral control mechanism of the distributed multi-robots was integrated with FCFS and adaptive cruise control (ACC) scheduling algorithms. The integration of multiple algorithms is a challenging task for smarter indoor robotics, and the Xilinx-based partial reconfiguration method was deployed to avoid computational issues with multiple algorithms during the run-time. These methods were coded with Verilog HDL and validated using an FPGA (Zynq)-based multi-robot system.

Service robots perform versatile functions in indoor environments. This study focuses on obstacle avoidance using flock-type indoor-based multi-robots. Each robot was developed with rendezvous behavior and distributed intelligence to perform obstacle avoidance. The hardware scheme-based obstacle-avoidance algorithm was developed using a bio-inspired flock approach, which was developed with three stages. Initially, the algorithm estimates polygonal obstacles and their orientations. The second stage involves performing avoidance at different orientations of obstacles using a heuristic based Bug2 algorithm. The final stage involves performing a flock rendezvous with distributed approaches and linear movements using a behavioral control mechanism. VLSI architectures were developed for multi-robot obstacle avoidance algorithms and were coded using Verilog HDL. The novel design of this article integrates the multi-robot’s obstacle approaches with behavioral control and hardware scheme-based partial reconfiguration (PR) flow. The experiments were validated using FPGA-based multi-robots.

Synchronous communication is one of the most important issues in high performance architectures for large scale of parallel computing, such as matrix computing, image processing, etc. Mesh-connected processor array is characteristic of synchronous communication due to the same length of the interconnects between the neighboring processing elements (PEs) in rows/columns. But long interconnects caused by faulty PEs clearly impact the synchronous communication between the adjacent rows/columns. If long interconnects exist between two adjacent rows, we say that a synchronous communication delay is caused. This paper contributes algorithms to construct logical arrays with synchronous communication in a given host array. Specifically, an algorithm for synchronous communication array (ASCA) is firstly presented, to construct a maximum logical array with synchronous communication. When all of the long interconnects are independent each other, the proposed algorithm is proved to be optimal. After that, two heuristic algorithms are also proposed, to construct a logical array with given size, by integrating the proposed ASCA and two exclusion schemes. The proposed two exclusion schemes are based on strategies of divide-and-conquer and the longest logical column first, respectively. In addition, the lower bound of synchronous communication delay for a logical array is calculated by an algorithm also developed in this paper, in order to evaluate the synchronous performance of reconfiguration algorithms. Simulation results show that, the proposed two heuristic algorithms have their own advantages for different cases. The synchronous communication delay of the logical arrays is significantly reduced, and it is very close to the lower bound for the cases of small fault density and larger exclusion rate. For 32 × 32 physical arrays with exclusion rates that are larger than 15%, the synchronous communication delay of logical array is reduced from 11.09 to 6.97, which is more closer to the lower bound 4.43, for different fault densities on average.