Susmit Sarkar's research while affiliated with University of St Andrews and other places

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Publication (1)

Figure 2: Example instruction description, in vendor documentation and...
An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors
Conference Paper
Full-text available
  • Dec 2015
Weakly consistent multiprocessors such as ARM and IBM POWER have been with us for decades, but their subtle programmer-visible concurrency behaviour remains challenging, both to implement and to use; the traditional architecture documentation, with its mix of prose and pseudocode, leaves much unclear. In this paper we show how a precise architectur...

Citations

... Making relaxed-memory semantics exhaustively executable is essential for exploring their behaviour on examples [67,54,53,20,9,36,66,23,64,49,57]. Handling relaxed virtual memory 8 Experimental testing of hardware 50 brings several new challenges. ...
Reference: Relaxed virtual memory in Armv8-A (extended version)