Sung-Hou Kim’s research while affiliated with Korea Advanced Institute of Science and Technology and other places

An electrochemical approach to determine the lanthanide concentrations by normal pulse voltammetry was presented in the binary system of gadolinium (Gd) and lanthanum (La) as a part of the long-term goal to predict the total lanthanide concentrations in multi-component molten salt. The experimental conditions were optimized in terms of the pulse width and pulse period and a calibration curve was constructed in the molten salt with gadolinium ions. The limiting current of normal pulse voltammetry increased with gadolinium concentration with an excellent linearity in a concentration range of below 2 wt %. In addition, the total concentration of lanthanides in the binary solutions was estimated on the basis of the calibration curve. The maximum currents taken in the binary solutions of Gd and La were excellently fitted to the calibration curve, indicating that the total amount of lanthanides can be determined by normal pulse voltammetry technique.

In this paper, a unified media application processor (UMAP) is presented for 2D/3D image analysis/synthesis applications on handheld devices. UMAP integrates parallel and sequential processing layers which consist of heterogeneous functional IPs for general media contents processing on today's application processors (AP). Based on the heterogeneous many-core platform, UMAP supports not only graphics and vision processing for real-time augmented reality (AR) but also disparity estimation and 3D display synthesis for 3D-view AR acceleration. A new concept of 3D-view AR which synthesizes 3D display contents from two vertically aligned stereo images and a self-constructed disparity map is introduced to achieve true realism for next generation mobile devices. For low-cost 3D-view AR processing, a homography-based disparity estimation (HDE) algorithm is proposed to construct a disparity map between two stereo images with small implementation overhead. For real-time and energy-efficient system organization, workload-balanced 3-stage pipelined architecture and a mixed-mode feature extraction engine (FEE) are also implemented in UMAP. The 3-stage pipelined system which consists of graphics, vision, and display operation stages reduces per-frame execution latency, while dynamic analog/digital mode reconfiguration based on mixed-mode FEE reduces per-frame energy dissipation, so real-time energy-efficient 3D-view AR can be realized in UMAP. FEE performs high-speed corner detection for vision processing based on four pairs of analog current contention logics (CCLs). Especially, a diode-connected current sensing stabilizer (CSS) in each CCL reduces minimum sensing current for corner detection, so average power consumed in CCL is reduced by 44.9%. In 2D or 3D-view AR processing, FEE with four CCLs replaces the parallel processing core cluster which is the most power hungry IP in UMAP, so 96.7% of cluster power and 99.1% of target detection time are saved in real operation. Based- on the 3-stage pipelined architecture with the dynamic mode reconfiguration technique, the entire UMAP achieves up to 64.4% of energy reduction compared to the previous state-of-the-art media processors in full operation.

A unified media application processor (UMAP) with a low-power mixed-mode feature extraction engine (FEE) is presented for 2D/3D image analysis/synthesis applications on handheld devices. UMAP supports not only graphics and vision for augmented reality (AR) but also 3D reconstruction and 3D display for 3D-view AR based on heterogeneous many-core platform. A frame-level 3-stage pipelined architecture enables real-time (50fps in VGA) performance in 3D-view AR, while a mixed-mode FEE dynamically saves active power by reconfiguring operation modes between analog and digital processing. Especially for low power operation in media processing, four pairs of analog current contention logics (CCL) are implemented in FEE. The implemented CCL does not require digital-to-analog or analog-to-digital converters (DAC/ADC) in interfacing digital and analog domains. It includes a diode-connected sensing stabilizer which reduces minimum sensing current. Therefore, average power consumed in CCL is reduced by 44.9%. In the implemented UMAP, the proposed FEE replaces the parallel processing core cluster in the analog processing mode, as a result, 96.5% of cluster power and 99.1% of target detection time are saved. The dynamic mode transition between analog and digital processing based on run-time tracking of region-of-interest (ROI) reduces system energy dissipation by up to 84.2% compared to the state-of-the-art embedded media processors.

We embed special function units (SFUs) in homogeneous stream processors (SPs) within a graphics processing unit (GPU), to improve its performance in running modern programmable shaders, which make poor use of a single-instruction multiple-data (SIMD) architecture. We also compact instructions, so as to reduce the size of the instruction memory, and reduce area requirements by using a partial SFU in SPs, and a lookup table which is shared between multiple SFUs. The result is an increase of 88% in utilization and a reduction in the normalized area-delay product of 27%, compared to a baseline SIMD architecture. We verified our architecture on an field-programmable gate-array evaluation platform with an ARM9 host processor and a full 3-D graphics pipeline.

A mobile 3-D display processor with a subdivider is presented for higher visual quality on handhelds. By combining a subdivision technique with a 3-D display, the processor can support viewers see realistic smooth surfaces in the air. However, both the subdivision and the 3-D display processes require a high number of memory operations to mobile memory architecture. Therefore, we make efforts to save the bandwidth between the processor and off-chip memory. In the subdivider, we propose a recomputing based depth-first scheme that has much smaller working set than prior works. The proposed scheme achieves about 100:1 bandwidth reduction over the prior subdivision methods. Also the designed 3-D display engine reduces the bandwidth to 27% by reordering the operation sequence of the 3-D display process. This bandwidth saving translates into reductions of off-chip access energy and time. Consequently the overall bandwidth of both the subdivision and the 3-D display processes is affordable to a commercial mobile bus. In addition to saving bandwidth, our work provides enough visual quality and performance. Overall the 3-D display engine achieves 325 fps for 480 times 320 display resolution.

In this paper, a heterogeneous 3D-media processor is presented, which supports all 3-D display applications by combining a 3-D display IP with a 3-D graphics IP and a stereo video decoder. For mobile environments, adaptive power management scheme is proposed, which saves power consumption up to 186 mW by turning off idle functional blocks based on a target application, a target performance, and the run-time ratio between different IPs. As a result, the minimum power consumption of the processor is only 15 mW, while the overall power consumption is 201 mW. As well as the reduction of power consumption, this work shows impressive performance improvement. The proposed fast modulo operators and adopted division-free algorithm reduces the critical latencies of 3-D display image processing. The proposed fast datapath with parallel architecture increase synthesis rate up to 116 fps which is 17 times faster than a previous work. In addition, reordered operation sequence fixes memory bandwidth regardless of the number of images to be produced. In the 3-D graphics IP and the decoding IP, redundant datapath are merged using an IEEE 754 compliant floating-point vector unit to save both chip area and power consumption, which even reduces the critical latency by 30%.

A unified vision and graphics processor with three layers is shown to provide a fast pipeline for augmented reality. In the image-level layer, a 153.6 GOPS massively parallel processing unit with eight SIMD processors, each containing 128 processing elements, performs highly data-parallel operations. In the sub-image layer, a rasterizer and a pixel arranger respectively generate and reduce data-level parallelism. In the descriptor-level layer, a pose estimation engine executes sequential programs. Our processor can provide images for augmented reality at 100 fps, for a power consumption of 413 mW. This is 39% faster than a comparable smartphone implementation. Our chip is fabricated in a 0.18 mu m CMOS process and contains 0.95 M gates.

In this paper, a power efficient vertex processor for mobile graphics applications is presented. A four-threaded and four-issue expanded VLIW datapath with a quad-float vertex texture fetcher is proposed by exploiting graphics specific characteristics after evaluation of several candidate architectures. Instruction-level power control methods such as operand sharing and writeback re-allocation along with operand isolations and gated clocks result in 40.4% and 82% reduction in energy dissipation and energy delay product compared to the most widely used single threaded SIMD. The proposed processor with the optimized datapath and vertex caches implemented in a 0.18- mum 1P4M CMOS process achieves 186-Mvertices/s geometry performance which is the best result among the processors that are IEEE-754 compliant.

A mobile heterogeneous 3D-media processor which supports all 3D display contents by combining a 3D display IP with a stereo video decoder and a 3D graphics IP is proposed. For mobile environment, adaptive power management scheme is adopted, saving 165mW. For high-end applications, fast modulo operators are designed to synthesize 3D images at 116fps, 17 times faster than the previous work. An IEEE 754 compliant floating point vector unit reduces critical latency by 30%.

In this paper, a 3D display processor embedding a programmable 3D graphics rendering engine is proposed. The proposed processor combines a 3D graphics rendering engine and a 3D image synthesis engine to support both true realism and interactivity for the future multimedia applications. Using high coherence between 3D graphics data and 3D display inputs, both pipelines are merged by sharing buffers such that a 3D display engine directly uses the output of a 3D graphics rendering engine. The merged architecture has synergetic coupling effects such as freely providing various rendering effects to 3D images and easily computing disparities without complex extraction processes. In the 3D image synthesis engine, we adopt view interpolation algorithm and propose real-time synthesis method, pixel-by-pixel process. The view interpolation algorithm reduces the number of images to be rendered, resulting in the reduction of external memory size to 64.8% compared to conventional synthesis process. The proposed pixel-by-pixel process synthesizes 3D images at 36 fps through bandwidth reduction of 26.7% and decreases internal memory size to 64.2% compared to typical image-by-image process. The 3D graphics rendering engine is programmable and supports the instruction sets of the latest 3D graphics standard APIs, Pixel Shader 3.0 and OpenGL|ES 2.0. The die contains about 1.7 M transistors, occupies 5 mm times 5 mm in 0.18 mum CMOS and dissipates 379 mW at 1.85 V.