Stephan W. Gehring’s research while affiliated with Computer Systems Institute and other places

In our digital design laboratory we have replaced the traditional wired circuit modules by workstations equipped with an extension board containing a single FPGA. This hardware is supplemented with a set of software tools consisting of a compiler for the circuit specification language Lola, a graphical layout editor for design entry, and a checker to verify conformity of a layout with its specification in Lola. The new laboratory has been used with considerable success in digital design courses for computer science students. Not only is this solution much cheaper than collections of modules to be wired, but it also allows for more substantial and challenging exercises.

To implement high-density and high-speed FPGA circuits, designers need tight control over the circuit implementation process. However, current design tools are unsuited for this purpose as they lack fast turnaround times, interactiveness, and integration. We present a system for the Xilinx XC6200 FPGA, which addresses these issues. It consists of a suite of tightly integrated tools for the XC6200 architecture centered around an architecture-independent tool framework. The system lets the designer easily intervene at various stages of the design process and features design cycle times (from an HDL specification to a complete layout) in the order of seconds. 1 Introduction Fully automatic circuit synthesis from an HDL description is a difficult and computationally intensive task, especially for FieldProgrammable Gate Arrays (FPGAs). Ideally, circuits are mapped, placed and routed without human intervention. However, to implement high-density or high-speed circuits with FPGAs, today's d...

To implement high-density and high-speed FPGA circuits, designers need tight control over the circuit implementation process. However, current design tools are unsuited for this purpose as they lack fast turnaround times, interactiveness, and integration. We present a system for the Xilinx XC6200 FPGA, which addresses these issues. It consists of a suite of tightly integrated tools for the XC6200 architecture centered around an architectureindependent tool framework. The system lets the designer easily intervene at various stages of the design process and features design cycle times (from an HDL specification to a complete layout) in the order of seconds. y Interval Research Corporation, Palo Alto, California z DEC Systems Research Center, Palo Alto, California Copyright c fl1998 by the Association for Computing Machinery, Inc. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are...

The implementation of a number of FIR filter structures in the Xilinx XC6200 technology is presented. The designs have been implemented using a combination of IRIS, an architectural synthesis tool and Trianus/Hades a set of integrated tools for implementing algorithms on Custom Computing Machines. The main attraction of this approach is that it allows algorithms to be compiled quickly allowing performance changes to be made at the architectural level in IRIS rather than at the FPGA layout level

We describe the Trianus software system which consists of a suite of tightly integrated tools for the efficient design and implementation of algorithms using a custom computing machine. The software is built upon a generic framework for FPGA circuit design and comprises a compiler for the Lola hardware description language, a layout editor, a circuit checker, a technology mapper, a placer, a router, and a bit-stream generator and loader for the Xilinx XC6200 architecture. We argue that a tight coupling of design tools provides a base for fast iterative and interactive circuit design, a feature which current systems provide only in a very limited form.

Diss. no. 12188 techn. sc. SFIT Zürich. Literaturverz.