Stephan Dobritz’s research while affiliated with Fraunhofer Institute for Reliability and Microintegration and other places

The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

Many semiconductor companies are currently engaged in 3D system integration. The assembly of 3D compliant chips becomes a vital factor of the 3D application success and reliability. Major challenges are provided by very low chip thickness, large die size, small interconnect diameter and pitch. Diverse 3D assembly technologies and methods are currently under investigations which address these specific technical challenges. Stable and volume capable assembly processes must be developed in order to manufacture such products in future with reasonable cost. Wafer-to-wafer (W2W) assembly is not yet recommended for most of the advanced 3D applications since it still suffering from too high yield losses what would translate into unacceptable W2W stack yield. For that reason the die-to-die (D2D) assembly is considered as the more efficient way for the time being. For that reason we're developing integrated assembly and test concepts on 300 mm wafer size to evaluate and validate various assembly technologies regarding to their capabilities with respect to interconnect materials, dimension, pitch and I/O density.

In this work a compact microprobe for advanced chip-inspection applications is introduced. The probe features integrated photoconductive switches for Terahertz pulse generation and detection. Device application is demonstrated for contact-free high-resolution time-domain reflectometry measurements at silicon-chip test structures.

3D integration is now a realistic, mainstream solution to tackle the issue of device scaling and achieve decreased RC delay times and reduced power consumption, by using through-silicon-vias (TSV). In this architecture, a via liner performs multiple functions as an insulator, a Cu diffusion barrier and an adhesion promoter. The dielectric layer is the key element in fulfilling the electrical requirements for TSV when a high aspect ratio of more than 5:1 is used. This paper presents a new methodology for creating a dielectric liner by using a dual plasma-enhanced/high-pressure chemical vapour deposition (PE/HPCVD) layer of SiO2 to produce a better 3D integration solution than today’s commonly used SiO2 deposition process.

The chip integration design has changed from long, wired, two-dimensional packaging to short, vertical, three-dimensional stacking. New challenges have to be mastered with the introduction of Through Silicon Vias (TSVs) as a key element in 3D Integration. Though-silicon via (TSV) technology has received the most attention because this technique offers system design flexibility, low cost, and integration of heterogeneous chips. [1] This includes the development and validation of concepts for 1) TSV formation, 2) metal layer build-up, 3) various types of assembly and packaging concepts and methods, as well as 4) process characterization. Goal was to develop a flexible and modular technological concept which allows the execution and characterization of the above mentioned processes by using a test- and characterization wafer (ASSID-TC). This paper will focus on the influence of the anneal temperature on the copper surface around the filled TSV holes by using the ATEC for process optimization. After TSV fill by ECD the copper surface appears rough and shows non-uniformities around the TSV holes (??dip??- shape or ??groove??). These irregularities were measured after ECD up to 2micrometer depth. Without a temperature treatment prior CMP the ??dip?? gets transferred down to the barrier and reduced in depth also to the isolation layer. The dimension of this ??groove?? after CMP is similar to erosion and dishing. It has been be demonstrated that a temperature treatment is advised as well to avoid not just copper protrusion but rather also the ??dip?? influence to the planarization if these planarization parameters are important for the integration (depending from product). Keywords: Through Silicon Via (TSV), Anneal, CMP, Test Chip, ECD, Copper, Erosion, Dishing, Protrusion