Shuichi Oikawa’s research while affiliated with University of Tsukuba and other places

A fork bomb attack is a denial of service attack. An attacker generates many processes rapidly, exhausting the resources of the target computer systems. There are several previous work to detect and remove the processes that cause fork bomb attacks. However, the operating system with the previous methods have the risks to terminate inappropriate processes that do not fork bomb processes. In this paper, we propose a new method that named process resource quarantine. With the proposed method, the operating systems don't terminate the detected fork bomb processes. Instead of the termination, the operating systems make resource limitations for the detected processes and inspect them periodically. We implemented the proposed method on Linux kernel and executed several evaluation experiments. The results show that the proposed method is effective for fork bomb attacks mitigation.

The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory NVM, which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the price and capacity of NVM are problematic. Therefore, the authors provide a large memory space without performance degradation by combining NVM with other memory devices. In this study, they propose a design for non-volatile main memory systems that use DRAM as a swap space. This enables both high performance and energy efficient memory management through dynamic power management in NVM and DRAM.

The amount of free memory have a great influence on system stability because out of memory occurs performance degradation phenomena, unexpected process terminations and so on. Thus, It is an important administration task to design the memory utilization plan based on the characteristics of the processes. However, in sometimes, processes demand a large amount of main memory rapidly and unexpectedly due to various reasons (e.g. memory leaks, malicious programs, denial of service attacks to network servers). These unexpected large memory demands cause out of memory and make the systems unstable. Existing memory management mechanisms are somewhat effective to prevent such out of memory with the unexpected memory demands. However, the existing mechanisms have several problems arising from the difficulty in the discrimination between the expected and unexpected large memory demands. As a solution, we propose a new memory resource management method at the operating system level. The proposed method utilizes memory allocation rate to detect unexpected large memory demands, i.e., the operating system with the proposed methods regard the processes that demand memory rapidly as offending processes. In this paper, we will discuss the problem of existing memory management mechanism and describe the proposed method and show the evaluation experiments.

The energy consumption of memory is one of the important metrics to evaluate memory systems. However, previous approaches such as using cycle accurate CPU and memory simulators require a long execution time for simulation. We are developing a model of energy consumption of DRAM-and NVM-based main memory, which allows estimating the energy consumption of a memory subsystem from easily observable performance metrics in real computer systems. In this paper, we conducted preliminary experiments using various types of workloads and observed the correlation of the memory throughput and energy consumption of DRAM. We used hardware performance counters to obtain memory throughput and energy consumption with minimum performance overhead.

Non-volatile memory devices (NVM) devices, such as PCM, STT-MRAM, and ReRAM, enable the integration of secondary storage into main memory. This integration reduces I/O access to slow block devices; however, it is currently unrealistic to construct a large capacity main memory with a single NVM, because such devices have certain write access limitations. Combining NVM and other memory devices is necessary to overcome such disadvantages. Several researches discussed NVM/DRAM hybrid memory, combining NVM and DRAM. To use NVM/DRAM hybrid memory, the placement of data between NVM and DRAM must be determined. In particular, write-hot data should be allocated to DRAM and write-cold data to NVM. For data placement, programming language runtime supports are useful because they possess more detailed information about write access than the operating systems. A previous research proposed the individual counting method to manage NVM/DRAM hybrid memory with programming language runtime support that determine data placement based on the number of write accesses to each object. However, it is difficult to determine dynamically threshold values for data placements using the individual counting method. Here we propose a multi-level queue method to distinguish between write-hot and write-cold data. Experimental results show that the proposed method resolves the limitations of the individual counting method.

In this research, we propose the flash memory aware memory management unit (MMU) that enables an efficient hybrid memory architecture. We design the proposed MMU based on the SSDAlloc hybrid memory architecture to make flash memory aware. Our challenge is to make flash memory suitable for hybrid memory architecture, which consists of DRAM and flash memory and works as main memory. The proposed MMU can reduce the overhead of the runtime library implementation, and improve the DRAM utilization efficiency. As a result, the proposed MMU can reduces more than half of page fault.