Sangwoo Pae’s research while affiliated with Nanjing Nari-Relays Electric CO., LTD and other places

... For example, in fig. 5 (b), TSV_256 denotes the arrangement of 256 TSV copper pillars within the silicon layer, with a volume filling fraction of 50.30%, indicating the proportion of copper pillars relative to the silicon area. Power dissipation per chip layer ranges from 2 W to 8 W [18], covering both peak power during high-speed operations and idle power during standby modes [19]. Environmental factors, including an ambient temperature of 25℃and a heat transfer coefficient (HTC) ranging from 200 to 10,000 W/m²·K, were incorporated to represent external cooling conditions, which critically influence heat dissipation and overall thermal stability; however, due to the exponential growth in computational requirements and experimental complexity with the increasing number of variables and their ranges, the exhaustive combinatorial analysis of all possible parameter combinations within this vast multidimensional design space is infeasible within a practical time frame. ...

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Neural Network Surrogate Model for Junction Temperature and Hotspot Position in $3$D Multi-Layer High Bandwidth Memory (HBM) Chiplets under Varying Thermal Conditions

... However, there exists a need to expand this research to the latest generation, such as DDR5. DDR5 DRAM undergoes a more aggressive scaling process, aiming for increased density and larger bandwidth [84][85][86][87]. The increased scaling of the DRAM cell in DDR5 renders it more susceptible to data retention failures. ...

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Rowhammer Attacks in Dynamic Random-Access Memory and Defense Methods

... Thus, the error rate due to neutrons is higher than due to particles in the terrestrial environment. In [29], it was reported that particles have a higher rate of change in SER with respect to crit than neutrons due to the difference of the LET of the particles. Therefore, the tolerance to particle irradiation of the proposed FFs is better than that to neutron irradiation. ...

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Radiation-Hardened Flip-Flops in a 65 nm Bulk Process for Terrestrial Applications Coping With Radiation Hardness and Performance Overheads

... As semiconductor systems become more highly integrated, the width of the interconnects decreases, and their complexity increases, highlighting the growing importance of optimizing interconnects. The interconnect and junction structures that make up semiconductor systems ultimately have a relatively simple form, consisting of the bonding between metal layers [27][28][29][30][31]. The findings of this study provide insights into improving power efficiency in the connection between two metal layers and the plug that connects them, making it practical for real-world applications. ...

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Analysis of Signal Transmission Efficiency in Semiconductor Interconnect and Proposal of Enhanced Structures

... Corresponding test keys are put on scribe lanes to facilitate process reliability tests before shipping the wafers. However, unlike process reliability assessments, product reliability is usually measured by using an ingenious static random access memory (SRAM), which needs assembly and comparably time-consuming accelerated life testing (ALT); these altogether usually take more than one month [8,9]. In addition, quantitative relations between process reliability and the final product reliability have not been properly built due to the complex interactions among multiple features (e.g., transistors, interconnections, and films). ...

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An Extended Building-In Reliability Methodology on Evaluating SRAM Reliability by Wafer-Level Reliability System

... On the other hand, research indicates that HCI exhibits more pronounced thermal acceleration effects in PMOS devices (as further confirmed by the higher Ea value in p-FET). Consequently, at elevated temperatures, HCI has a more significant impact on PMOS device degradation [24]. ...

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Aging Analysis and Degradation Prediction of PLL Circuits in 14-nm FinFET Technology

... HfO 2 -based materials are promising for DRAM capacitors due to several benefits including a wide bandgap (E g , ~5.3-5.7 eV), relatively high dielectric constant (κ, ~20-40), excellent CMOS compatibility and mature atomic layer deposition (ALD) process for three-dimensional (3D) structures [2,3]. How to obtain high-κ (equivalent oxide layer thickness EOT < 0.5 nm) and reduced leakage current density (J leak < 10 − 7 A/cm 2 at an operation voltage of 0.5 V) in HfO 2 -based materials with a thin physical thickness (<5 nm) is one of the main challenges in DRAM development [4][5][6]. ...

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High-κ Hf0.3Zr0.7O2 Film with Morphotropic Phase Boundary for DRAM Capacitor by Controlling H2O Dose

... Advancements in DRAM chip storage density have been central to increasing demands for memory capacity since the inception of DRAM technology [9,172]. Today's emerging data-intensive applications and systems in domains such as AI, cloud, and HPC continue to demand greater memory capacity at an unprecedented scale [173][174][175][176][177]. Unfortunately, technology shrinkage throughout the past two decades has yielded diminishing benefits for chip storage capacity, access latency, and refresh overheads because of the growing costs and overheads of maintaining reliable chip operation at smaller technology node sizes [10,11]. ...

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Rethinking the Producer-Consumer Relationship in Modern DRAM-Based Systems

... Several studies have demonstrated this by heating MOSFETs either through special on-chip Joule heaters [11], or by forcing a large body-drain current [13]. At least once study suggests that partial recovery from HCI is possible by heating unpowered ICs in an oven for a short time [14]. Despite this, we believe that exploiting HCI presents a fruitful strategy for combatting recycling. ...

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A Small Tamper-Resistant Anti-Recycling IC Sensor With a Reused I/O Interface and DC Signalling

... IGZO can be synthesized using a range of thin-film deposition techniques such as sputtering, atomic layer deposition (ALD) [10,11], pulsed laser deposition (PLD) [12,13], and chemical vapor deposition (CVD) [14,15]. By precisely controlling the ratios of In, Ga, Zn, and O during deposition, it is possible to tailor the channel properties to meet the requirements of specific applications. ...

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IGZO-Based Electronic Device Application: Advancements in Gas Sensor, Logic Circuit, Biosensor, Neuromorphic Device, and Photodetector Technologies