S.K. Tewksbury's research while affiliated with Stevens Institute of Technology and other places

Publications (84)

Conference Paper
Defect and fault tolerance techniques have played a substantial role in the evolution of silicon digital integrated circuits (ICs). The complex and several mechanisms causing defects in the as-manufactured IC could be represented by simple functional defects ("stuck-at" faults, etc.) and. given these simple functional defects, a variety of testing...
Chapter
The sections in this article are
Conference Paper
The capabilities of switched networks for parallel and distributed computers are evolving rapidly towards networks with various forms of intelligence in support of parallel execution of programs. This paper presents a perspective on intelligent networks, including reconfiguration of the network to adapt to the needs of successive computational algo...
Conference Paper
A testbed for investigation of heterogeneous and reconfigurable data network fabrics supporting a parallel DSP computational accelerator is described. The DSP processors are large-grained processors (Analog Devices SHARC DSPs), with a variety of parallel DSP array architectures possible. The network fabric is intended to be reconfigurable (within a...
Article
Full-text available
Techniques for distribution of optical signals, both free space and guided, within electronic systems has been extensively investigated over more than a decade. Particularly at the lower levels of packaging (intra- chip and chip-to-chip), miniaturized optical elements including difiractive optics and micro-refractive optics have received considerab...
Article
Realization of future applications indicated by roadmaps of present mainstream circuit and system technologies implies surmounting major practical barriers of higher power dissipation and density, higher densities of interchip and inter-module connections, and high-speed system operation. Both in combination or separately, optical interconnections...
Conference Paper
Suggests various ways in which conventional silicon electronics might be used in an MCM daughterboard configuration to support optical interconnection modules for MCM-to-MCM optical interconnections. The emphasis is on achieving a synergistic merging of silicon electronic functions and III-V optoelectronics within a compact module that appears to b...
Article
A barrier that has faced insertion of optical interconnections within MCM environments is the absence of generic system-level building blocks suitable for inclusion by system designers within prototype MCM architectures. To obtain system-level acceptance, a stable digital interface with built-in self test, fault tolerance, and relaxation of optomec...
Article
Full-text available
Activation in the early summer of 1994 of the awarded Reactive Ion Etch (RIE) and magnetron sputtering systems, coupled with major corporate donations of other critical equipment, has put in place the first microfabrication laboratory at West Virginia University. The System Microfabrication Laboratory is one of three major labs within the Microelec...
Conference Paper
The SWAN (silicon wafer-area network) project described explores the application of the high speed and high density of interconnections in WSI and MCM technologies to new communications schemes for general purpose, parallel arrays of computing nodes. The SWAN architecture seeks to provide on-demand, point-to-point communications through dynamically...
Conference Paper
A barrier that has faced insertion of optical interconnections within MCM environments is the absence of generic system-level building blocks suitable for inclusion by system designers within prototype MCM architectures. To obtain system-level acceptance, a stable digital interface with built-in self test, fault tolerance, and relaxation of optomec...
Article
Full-text available
The rapid emergence of multichip modules (MCMs) and the continuing interest in wafer scale integration (WSI) provide important opportunities for successful insertion of high performance optical interconnections into real systems. The large area substrates and the distances between packaged wafer-level modules introduce distances of sufficient lengt...
Article
Routine use of optical interconnections in MCM based computing systems ideally favors monolithic integration to achieve both high density and manufacturability. The central issue facing this monolithic evolutionary path is the compatibility of both III-V semiconductor growth and subsequent optoelectronic device and passive optical interconnection p...
Article
Si systems are rapidly evolving toward more efficient, compact parallel architectures as silicon technology evolves toward ultra-large-scale integration (ULSI) and as advanced packaging technologies such as multichip modules (MCMs) are developed. Such advanced microelectronic systems will confront increasingly complex interconnection constraints. O...
Conference Paper
Two specific issues impacting the eventual application of optical interconnection in full-wafer systems are addressed. The first issue is growth of GaAs semiconductor regions within a silicon wafer scale integration (WSI) or multichip module (MCM) substrate containing high performance silicon CMOS circuitry, in order to cointegrate optical and sili...
Conference Paper
An overview of interconnections within microelectronic systems is provided from the viewpoint of a communications-oriented audience, drawing on the expected evolution to ULSI systems. General issues and opportunities arising in the area of interconnections and packaging are discussed, along with some important characteristics suggesting the need fo...
Article
Si systems are rapidly evolving towards more efficient, compact parallel architectures characterized by a mix of both monolithic and hybrid technologies as silicon technology moves into the ultra large scale integration (ULSI) era. Previous distinctions between active chips and passive packaging will disappear within multi-chip modules (MCM) in whi...
Article
Fault tolerant semiconductor memory array designs are proposed for enhancing yield and improving reliability. Reconfiguration is achieved through redundancy in memory cell clusters, single and multiple rows, and single and multiple columns. The factors that affect the amount of redundancy are analytically determined and the effect of reconfiguratio...
Conference Paper
It is pointed out that, as MCMs (multi-chip modules) develop, a suitable design-for-manufacturability strategy will need to emerge, reducing MCM costs while retaining the performance advantages of MCMs. Three issues are considered: (1) a suitable analytic model of defects (and their generation of faults) suitable for application of `design for defe...
Conference Paper
Several interconnection issues relating to faults and reliability are reviewed. Whereas the occurrence of opens in interconnections or shorts between interconnections is well understood within conventional models of digital systems, the faults originating from the analog characteristics of signals propagating across interconnection lines (particula...
Conference Paper
The evolution of silicon to 0.25-μm technologies will yield very powerful, single-chip ULSI arrays of high-performance processors and high-capacity wafer-scale memories. The very compact, distributed computing systems which result will require very-high-performance communication networks, scaled to the much smaller size and more monolithic realizat...
Article
The maturation of silicon as a system wide "macrointegrated" technology suggests extremely compact, powerful computing systems in which communication will be among the most importantfunctions. A silicon wafer area communication net-work which has the transmission function performedoptically, ideally offers significant performance ad- vantages over...
Article
Two important issues will greatly influence the success of mapping optical interconnections into future waferlevel distributed computing systems: (1), the scalability of active optical devices with cointegration along side ULSI components, and (2), the scalability of optical networks and components to the wafer level. If these criteria can be met,...
Article
The evolution of silicon submicron technologies will yield very powerful single chip U LSI processors (possibly processor arrays) and high performance advanced packaging technologies, providing significant opportunities to realize very compact, distributed computing systems. However, exploiting that opportunity will require development of very high...
Article
Continued scaling of silicon CMOS technologies to smaller feature sizes will provide impressive opportunities for integration of very compex processing systems on single ICs and single wafers. This suggests a considerable scaling of "large-scale" systems such as distributed computing environments to much smaller, more highly monolithic real-ization...
Article
Summary form only given. The authors contrast the results of work on long (30 cm) YBaCuO microstrip interconnections and short (<10 cm) waveguided optical interconnections. 4000-AA YBaCuO films were coevaporated on 1-in<sup>2</sup> LaGaO<sub>3</sub> substrates and a 30-cm microstrip was patterned by lift-off. Measurements suggest (1) that flux moti...
Article
Electrical time domain measurements and transmission response measurements were made using a 31‐cm‐long, YBaCuO superconducting thin‐film microstrip line and a YBaCuO ground plane, each on separate 1‐cm LaGaO 3 substrates, with a 125‐μm sapphire substrate serving as the dielectric insulator. Degradation of the performance of the line for currents u...
Article
Superconducting transmission lines at Tc > 90 K may provide a high performance interconnection fabric for the intermediate interconnection levels (chip-to-chip, board-to-board, rack-to-rack, etc.) for high performance digital systems. The potential performance of high-Tc superconductors in such applications can be estimated by assuming that their i...
Article
Highlights the major trends and issues affecting monolithic wafer-scale circuits and hybrid wafer-scale circuits, i.e. pretested chips mounted on silicon wafer circuit boards. An extensive set of references is provided to avoid repeating detailed discussions available in the cited literature. Instead, a broad overview of the objectives and motivati...
Conference Paper
It is noted that, with semiconductor logic at 77 K providing an optimized, local active device behavior for logical operations, high- T <sub>c</sub> superconducting transmission lines and Josephson tunnel junction drivers/receivers can provide a similarly optimized communications environment at 77 K. This combination of low-temperature active elect...
Conference Paper
Electrical time-domain measurements and transmission response measurements were made using a 31-cm-long YBaCuO superconducting thin-film microstrip line and a YBaCuO ground plane, each on separate 1-cm LaGaO<sub>3</sub> substrates, with a 125-μm sapphire substrate serving as the dielectric insulator. Degradation of the performance of the line for c...
Conference Paper
Drawing on advanced packaging and interconnection schemes along with advances in VLSI technologies, the authors consider some examples of novel interconnection technologies. Novel polymer waveguides requiring only exposure to deep UV to fabricate a waveguide are emphasized as a potentially important material compatible with overlaying complex VLSI...
Chapter
In this chapter, techniques to generate test stimuli, apply those test to circuit functions and to evaluate the test results [1,2,3,4] are reviewed. The emphasis is on general purpose schemes, such as scan path design of VLSI circuits and syndrome test compression. Special purpose testing schemes (e.g. [5,6,7,8]) developed for specific system funct...
Chapter
This chapter reviews the several models which have been developed to predict the yield of monolithic circuits. Circuit faults arise from a variety of effects. Defects during patterning or film depositions can lead to shorts, open lines or defective transistors, as discussed in the previous chapter. Such defect-based faults are considered in this ch...
Chapter
The design of reliable systems has been a major topic of systems research and development. Though a complex topic, several general principles of analysis and modeling have been developed (e.g. [1,2]). WSI provides reconfiguration or other repair strategies to avoid faulty components, assuming that the faults are known. The emphasis has been on init...
Chapter
The objective of fault modeling is to evaluate the various errors which can occur in digital circuits as a result of the various physical faults in fabricated devices and interconnections [l]–[7]. Conceptually, this involves the three principal steps illustrated in Figure 6.1.
Chapter
This chapter reviews several system performance limits imposed on electronic digital systems by their electrical interconnection fabric. Relaxing such limits is perhaps the major motivation for WSI, though different WSI projects typically address different interconnection issues.
Chapter
Although physical reconfiguration/restructuring switches dominate most commercial reconfigured VLSI circuits (e.g. memory repair), electronic switches are prominently used in experimental logic circuits designed for yield enhancement. Figure 10.1 shows the general model of an electronic switch for reconfiguration of interconnections. In addition to...
Article
Reviews simple models for understanding the intrinsic behavior of superconducting striplines for frequencies much less than the gap frequency ω<sub>g</sub>, and low reduced temperatures. The effects of extrinsic factors such as nonideal stripline geometries and dielectrics are also examined. It is concluded that although based upon classical theory...
Chapter
The previous chapter emphasized general purpose testing schemes for combinational and sequential logic circuits. This chapter describes several special-purpose testing schemes. Three distinct circuit functions (memory arrays, regular logic arrays and programmable logic arrays) are used as examples of the various techniques which can be used. A majo...
Chapter
Chapter 2 reviewed several limits imposed by electrical connections on the performance of systems. Given the severity of several of those limits, it is natural to consider alternative approaches to provide communications within a high-performance system. Optical interconnects have received considerable attention [1] – [11]. Already, optical network...
Chapter
A vast number of defect mechanisms arise in any modern VLSI fabrication process. Defects associated with the starting wafer and with lithography steps (i.e. resist-level patterns) are common to virtually all fabrication processes. Wafer defects are considered in Section 3.1 while lithography defects are discussed in Section 3.2. There are also majo...
Chapter
This section reviews several of the fundamental results on the “reconfigurability” of linear or 2-dimensional arrays of N cells as N becomes large. Details of the actual reconfiguration mechanisms (i.e. switches and redundant interconnection lines) are not emphasized, since the principal objective here is to obtain general bounds which can be used...
Chapter
Several workers have considered a hybridized version of wafer-scale integration in which the discrete IC’s are still mounted on circuit boards but with the circuit board fabricated on a silicon wafer. Lewis [1], at the conclusion of his study of package performance, suggests flip-chip, beam lead or tape (TAB) mounting of unpackaged ICs directly on...
Chapter
This chapter considers physical alterations of a fabricated integrated circuit to correct for fabrication faults and increase the yield of functional monolithic IC/WSI circuits. The term “physical restructuring” is generally here used to represent physical alteration of the circuit interconnection links, including switches along interconnection pat...
Article
Massively parallel computing systems will emerge over the next decade as the scaling of individual logic devices to smaller sizes and/or higher speeds approach fundamental limits and further improvements in the cost and/or performance of sequential computing become more difficult. Present efforts to implement such massively parallel systems confron...
Chapter
Using graph-based representations of computation problems [1]–[3], the communication function of a “pseudo-general purpose,” massively parallel computing environment is discussed to help define technology-focussed realizations of that communication function. Compatible computation problems are neither constrained to highly regular structures (such...
Article
The desire to achieve a high degree of parallelism in multiwafer wafer-scale-integrated (WSI) based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While the...
Article
This paper presents several current interconnection issues as well as future technological directions for improved interconnection/communication performance. The physical hierarchy of interconnections and the corresponding communication environment are highlighted. General issues concerning chip-to-chip and on-chip interconnections are reviewed, wi...
Article
Future high-performance large-scale digital systems will increasingly require high-density multichip hybrid packaging techniques. Chip attachment by flip-chip mounting, as in the well-established eontrolled-collapse solder-bump contact approach, has several fundamental advantages over the more familiar wire-bonded hybrid assembly approach. However,...
Conference Paper
Hybrid mounting of optical components, combined perhaps with integrated optical waveguides and lenses on a large area silicon, wafer-scale integrated (WSI) electronic circuit provides one potential approach to combine advanced electronic and photonic functions. The desire to achieve a high degree of parallelism in multi-wafer WSI-based architecture...
Article
Previous estimates of the performance limits of MOSFET logic devices, including the possibility of low temperature operation, have used the conventional static electrical behavior as a starting point. Typically, such studies conclude that the minimum voltage swing is ∼ 200 mV, leading to practical limits on power dissipation and switching speed tha...
Article
Semiconductor devices are almost universally based on an assumption of full ionization of dopant impurities, a natural condition at room temperature for conventional shallow-energy-level (activation energy ∼ 0.05 eV) dopant species. At temperature T < 30 K for conventional dopants, freezeout of the equilibrium carrier density becomes severe and unc...
Article
The properties of NMOS polycrystalline silicon gate transistors, fabricated in large-area laser-crystallised silicon layers on an insulating substrate, are described. The transistor characteristics reveal the influence of parasitic side transistors. The influence of the side-channel transistors becomes more pronounced with decreasing channel width,...
Article
A simple model of the low temperature (T≪30 °K), static and nonequilibrium transient conductance of the potential minimum region in a silicon, buried channel, metal‐oxide‐semiconductor field effect transistor is developed and experimental measurements of these conductances under carrier freeze‐out conditions are presented. The transient, nonequilib...
Article
Measurements of depletion layer formation rates in buried channel silicon, metal-oxide-semiconductor devices at carrier freeze-out temperatures are presented. The procedure is based on the current injected into the gate region by a pulsed gate bias and the dependence of this injection current on the pulse frequency. This method avoids strong electr...
Article
Isolated thin Si layers have been grown by laser µ-zone crystallization at high bias temperature. The influence of light on the properties of NMOS silicon gate transistors fabricated in these crystallized silicon layers is investigated. Both leakage current and threshold voltage are light sensitive. The influence of light on the threshold voltage r...
Article
Device quality isolated thin Si layers have been achieved by laser μ-zone crystallisation under high bias temperature. The influence of light on the properties of NMOS polycrystalline silicon gate transistors fabricated in these large area laser crystallised silicon layers is investigated. Both leakage current and threshold voltage are found to be...
Article
Metal-gate NMOS transistors have been fabricated in isolated silicon layers prepared in high-temperature biased laser crystallization. The transistor parameters are strongly influenced by the substrate material, in our case simultaneously processed silica and silicon wafers. Stress built up in the silicon layer strongly affects the carrier mobility...
Article
Adaptive filters, employing the transversal filter structure and the least mean square (LMS) adaptation algorithm, or its variations, have found wide application in data transmission equalization, echo cancellation, prediction, spectral estimation, on-line system identification, and antenna arrays. Recently, in response to requirements of fast star...
Article
Freezeout of substrate doping impurities, at T≪25 °K for conventional shallow level impurities in silicon, creates an insulating substrate in silicon metal‐oxide‐semiconductor (MOS) transistors. With the flow of majority carriers (holes for p‐type substrates) through the substrate impeded, the accumulated majority carrier density in the MOS transis...
Article
PMOS transistors have been fabricated in device-worthy Si which was achieved by large-area laser-crystallisation of Si on silica. The crystallised Si contains few large-angle grain boundaries due to laser-beam inhomogeneity but exhibits subgrain boundaries aligned along the laser track. Cracking of the Si, a result of the mismatch of the thermal ex...
Article
The design of an architecture for an integrated digital signal processor requires attention to details of processing algorithms. Starting with their conventional representation in either graphical or algebraic form, one can decompose algorithms to determine the essential requirements of processor architecture. This process may also serve as a means...
Article
A discrete conductance effect in the transient response of an n‐channel metal‐oxide‐ semiconductor field‐effect transistor (MOSFET) switched from accumulation to weak surface inversion between 10 and 25 K is described. The discrete conductance appears as a set of equally spaced current levels superimposed on the steady state and transient currents....
Article
The transient, excess source‐drain current which occurs under freeze‐out conditions when a metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is switched into a conducting state is described. The major features of the observed transient response for n‐channel MOSFET’s in the temperature range 10–25 °K are explained in terms of a simple one‐...
Article
Operation of MOSFET circuits at the liquid nitrogen temperature (77 K) has been suggested as a means of improving circuit and system performance. Previously reported work emphasizes mobility and threshold voltage at 77 K. However, small MOSFET's require several (≳10) parameters for circuit design. Since a full set of MOSFET model parameters have no...
Article
A number of the basic considerations involved in the selection of an overall digital signal processor architecture are reviewed.
Article
A number of the basic considerations involved in the selection of an overall digital signal processor architecture are reviewed. First, the major design constraints are considered: real-time processing, cost, performance, and reliability. Second, some of the alternatives regarding the overall processor architecture are discussed, and finally some a...
Article
In keeping with the trend to greater use of digital circuits for signal processing, a project was undertaken to realize in an exploratory way an important telecommunication function using as great a proportion of digital hardware as possible. The function chosen is that of the A -channel bank; viz., the frequency division multiplexing (FDM) of 12 v...
Article
In keeping with the trend toward greater use of digital circuits for signal processing, a project was undertaken to realize an important telecommunication function using as great a proportion of digital hardware as possible. The function in question concerns the translation between the traditional analog frequency division multiplex (FDM) format an...
Article
Following is a continuation of the list of titles and authors: Coded Digital Communication System for Manned Space Flight. By R. W. Moorehead and B. H. Batson. Experimental Application Large Capacity Digital Multiplexer for an Optical Transmission System. By B. G. King and H. J. Schulte. Experimental Tests of a Digital A-Type Channel Bank. By R. b....
Article
Adaptive filters, employing the transversal filter structure and the LMS adaptation algorithm, or its variations, have found application in data transmission equalization, echo cancellation, prediction, spectral estimation, on-line system identification and antenna arrays. Recently, however, in response to requirements of fast start-up or fast trac...
Article
Full-text available
In 1993, the Semiconductor Industries Association (SIA) formally developed a roadmap (1) of evolutionary milestones for silicon CMOS integrated circuits to become commercially available over the next 15 years. This roadmap was updated (2) in 1994 by the SIA, with the projections summarized in Table 1 representing some of the conclusions. The projec...
Article
For digital electronic computer interconnection fabrics, the advent of superconductivity at T/sub c/ > 90 K may hold promise for providing a high-performance interconnection fabric for the intermediate interconnection levels characteristic of chip-to-chip, board-to-board, and rack-to-rack line lengths, given their intrinsic characteristics are simi...

Citations

... They simultaneously generate outputs for all equalizer lengths (number of taps, or order) up to a specified maximum. They are configured very suitably for hardware pipelining [21]. Also, they were the first, recursive-least-square-error algorithm/ configuration to be developed with computational complexity proportional to N, the equalizer (maximum) length. ...
... Several wafers were also provided to researchers investigating GaAs heteroepitaxial growth at AT&T Bell Laboratories. Preliminary results from evaluations at AT&T Bell Laboratories have been reported in [23, 24]. However, the set of evaluations reported here have not yet been performed on those wafers.Figure 4 shows the thermal simulation schedule originally planned and the schedule actually used. ...
... Quantum well modulators were quite successfully grown on silicon substrates, however, with apparently good lifetimes [42] (a fact that is perhaps less well known than it ought to be). Despite this success, and subsequent success integrating with actual circuits [43], these workers soon realized that the problem of integration with silicon VLSI was not really solved in a practical sense. The issue is that in such a practical monolithic integration the VLSI process is changed in some ways. ...
... If the clock signal arrives at before it reaches [see Fig. 6(B)], the clock skew is defined as being negative. Negative clock skew can be used to improve the maximum performance of a synchronous system by decreasing the delay of a critical path; however, a potential minimum constraint can occur, creating a race condition [11], [12], [31], [138], [139], [145], [176], [179], [181]. In this case, when lags , the clock skew must be less than the time required for the data signal to leave the initial register, propagate through the interconnect, combinatorial logic, and setup in the final register (see Fig. 1). ...
... In this example, long wavelength light passes directly through the MCM substrates (assumed silicon) and is focussed using diffractive lenses etched directly on the backside of the MCM (WSI) substrates (e.g., SiN Fresnel zone plate lenses in [44]). Figure 14 illustrates an approach suggested in [45], mounting a preassembled optical module within an MCM package to provide parallel optical free space connections through optical ports in the MCM package. To eliminate the need for precision mechanical alignment of the MCM substrate to the optical elements, wire (or TAB) bonding connects the optoelectronics of the optical I/O module to the fully electrical MCM substrate. ...
... One method of combining OE materials with Si CMOS VLSI circuits utilizes hybrid epitaxial growth of III-V optoelectronic materials directly onto Si circuitry. The devices reported in the literature suffer from short lifetimes and low efficiencies due to lattice constant mismatch and differing coefficients of thermal expansion [9], or the Si CMOS is damaged by the relatively high-temperature growth process [10], which often causes additional CMOS junction diffusion, although there have been reports of hybrid growth success for modulators on Si substrates [11]. ...
... S.K. Tewksbury, Dept of Electrical & Computer Engineering, West Virginia University, "Interconnections With Microelectronic Systems", Microelectronic System Interconnections Performance & Modeling, IEEE Press, 1993 [14].Work & Results:-This paper combines two intuitively familiar terms "microelectronic systems" & "system interconnections" providing a basis for bounding the range of interconnection performance issues considered here. In addition, this review emphasizes those interconnections that are viewed as limiting system performance typically long 9 | P a g e interconnections (i.e.; "System level" interconnections) and/or those carrying very high data rates[14].2.1.10] Juliusz Poltz, OptEM Engineering Inc, "Optimizing VLSI InterconnectModel for SPICE Simulation", Analog Integrated Circuits and Signal Processing 5, pp. ...
... There have been several works on multi-processor based implementation of adaptive filters. Lawrence and Tewkbury suggested a multi-processor based solution that divides the filters into several partitions and assigns each of them to a single processor [4]. This multi-processor based method employs sample by sample processing, which requires small delay between the processing elements. ...
... Therefore, a number of efficient TMUX systems have been developed to minimize the system cost, overall computational complexity needed to design a TMUX system. In the early stage of research, TMUX systems were designed using non-DFT based Freeny et al. (1971) and DFT based Cruz-Roldan et al. (2012) and Lim et al. (2005)) methods. In the non DFT based approach (Freeny et al., 1971), analog filters were employed that cause a large interference between adjacent channels of TMUX, while the DFT based technique for designing TMUX systems (Cruz-Roldan et al., 2012;Lim et al., 2005) employs Fast Fourier Transform (FFT), which results in fast implementation of TMUX and efficient channel equalization (Parker, 2007;Jian and Zaichen, 2009). ...
... Innovations in the integration of passive optical elements directly as part of the MCM package to propagate light from the interior to the exterior of the MCM package are emphasized. The representative approach described reflects a desire to minimize excessive constraints on physical alignment [13,19,20] relative to another but also of VLSI ICs within the package to the optical interconnection interface. In the case of free-space optical beams between MCMs, this requires a transition from the small spacing between optoelectronic devices in source and detector arrays to the larger spacing between optical I/O ports of MCM packages, dictated by worst case MCM-to-MCM alignment tolerances. ...